DE3778388D1 - Halbleiter speichergeraet. - Google Patents

Halbleiter speichergeraet.

Info

Publication number
DE3778388D1
DE3778388D1 DE8787101309T DE3778388T DE3778388D1 DE 3778388 D1 DE3778388 D1 DE 3778388D1 DE 8787101309 T DE8787101309 T DE 8787101309T DE 3778388 T DE3778388 T DE 3778388T DE 3778388 D1 DE3778388 D1 DE 3778388D1
Authority
DE
Germany
Prior art keywords
storage device
semiconductor storage
power supply
mos transistor
supply terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787101309T
Other languages
English (en)
Inventor
Taizo C O Patent Divisio Okuda
Shinji C O Patent Divisi Saito
Nobuo C O Patent Di Shishikura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3778388D1 publication Critical patent/DE3778388D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
DE8787101309T 1986-01-30 1987-01-30 Halbleiter speichergeraet. Expired - Lifetime DE3778388D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61018717A JPS62177799A (ja) 1986-01-30 1986-01-30 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE3778388D1 true DE3778388D1 (de) 1992-05-27

Family

ID=11979408

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787101309T Expired - Lifetime DE3778388D1 (de) 1986-01-30 1987-01-30 Halbleiter speichergeraet.

Country Status (4)

Country Link
US (1) US4802137A (de)
EP (1) EP0231903B1 (de)
JP (1) JPS62177799A (de)
DE (1) DE3778388D1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62229599A (ja) * 1986-03-31 1987-10-08 Toshiba Corp 不揮発性半導体記憶装置
JPH01113999A (ja) * 1987-10-28 1989-05-02 Toshiba Corp 不揮発性メモリのストレステスト回路
JPH01208795A (ja) * 1988-02-16 1989-08-22 Toshiba Corp 半導体記憶装置
US5051995A (en) * 1988-03-14 1991-09-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having a test mode setting circuit
JP3384409B2 (ja) * 1989-11-08 2003-03-10 富士通株式会社 書換え可能な不揮発性半導体記憶装置及びその制御方法
JPH0679440B2 (ja) * 1990-03-22 1994-10-05 株式会社東芝 不揮発性半導体記憶装置
JPH0756759B2 (ja) * 1990-12-27 1995-06-14 株式会社東芝 スタティック型半導体記憶装置
JP3237127B2 (ja) * 1991-04-19 2001-12-10 日本電気株式会社 ダイナミックランダムアクセスメモリ装置
KR950003014B1 (ko) * 1992-07-31 1995-03-29 삼성전자 주식회사 반도체 메모리 장치의 번-인 테스트회로 및 번-인 테스트방법

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57172598A (en) * 1981-04-17 1982-10-23 Toshiba Corp Nonvolatile semiconductor memory
GB2094086B (en) * 1981-03-03 1985-08-14 Tokyo Shibaura Electric Co Non-volatile semiconductor memory system
EP0089397B1 (de) * 1982-03-24 1985-12-04 Deutsche ITT Industries GmbH Integrierte Speichermatrix mit nichtflüchtigen, umprogrammierbaren Speicherzellen
JPS59107493A (ja) * 1982-12-09 1984-06-21 Ricoh Co Ltd テスト回路付きｅｐｒｏｍメモリ装置
JPS59198597A (ja) * 1983-04-22 1984-11-10 Nec Corp 半導体メモリ
JPS6059599A (ja) * 1983-09-13 1985-04-05 Nec Corp 不揮発性半導体メモリ
KR900005666B1 (ko) * 1984-08-30 1990-08-03 미쓰비시전기 주식회사 반도체기억장치

Also Published As

Publication number Publication date
EP0231903A2 (de) 1987-08-12
US4802137A (en) 1989-01-31
JPS62177799A (ja) 1987-08-04
EP0231903A3 (en) 1989-03-22
JPH0468720B2 (de) 1992-11-04
EP0231903B1 (de) 1992-04-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee