DE3880003T2 - Halbleiteranordnung mit einer leiterschicht unter dem kontaktfleck. - Google Patents

Halbleiteranordnung mit einer leiterschicht unter dem kontaktfleck.

Info

Publication number
DE3880003T2
DE3880003T2 DE8888107501T DE3880003T DE3880003T2 DE 3880003 T2 DE3880003 T2 DE 3880003T2 DE 8888107501 T DE8888107501 T DE 8888107501T DE 3880003 T DE3880003 T DE 3880003T DE 3880003 T2 DE3880003 T2 DE 3880003T2
Authority
DE
Germany
Prior art keywords
region
contact hole
semiconductor substrate
emitter
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888107501T
Other languages
German (de)
English (en)
Other versions
DE3880003D1 (de
Inventor
Hiroshi Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3880003D1 publication Critical patent/DE3880003D1/de
Publication of DE3880003T2 publication Critical patent/DE3880003T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H10W20/42—
    • H10W72/07532—
    • H10W72/07553—
    • H10W72/531—
    • H10W72/536—
    • H10W72/5522—
    • H10W72/59—
    • H10W72/934—
    • H10W72/952—
    • H10W72/983—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Bipolar Transistors (AREA)
  • Local Oxidation Of Silicon (AREA)
DE8888107501T 1987-05-15 1988-05-10 Halbleiteranordnung mit einer leiterschicht unter dem kontaktfleck. Expired - Fee Related DE3880003T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62116727A JPS63283040A (ja) 1987-05-15 1987-05-15 半導体装置

Publications (2)

Publication Number Publication Date
DE3880003D1 DE3880003D1 (de) 1993-05-13
DE3880003T2 true DE3880003T2 (de) 1993-09-16

Family

ID=14694302

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888107501T Expired - Fee Related DE3880003T2 (de) 1987-05-15 1988-05-10 Halbleiteranordnung mit einer leiterschicht unter dem kontaktfleck.

Country Status (4)

Country Link
US (1) US4984061A (enExample)
EP (1) EP0291014B1 (enExample)
JP (1) JPS63283040A (enExample)
DE (1) DE3880003T2 (enExample)

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JP2593965B2 (ja) * 1991-01-29 1997-03-26 三菱電機株式会社 半導体装置
CA2101850C (fr) * 1991-02-25 1999-06-29 Ake Gustafson Procede de fixation d'un bobinage a un circuit electronique
US5281855A (en) * 1991-06-05 1994-01-25 Trovan Limited Integrated circuit device including means for facilitating connection of antenna lead wires to an integrated circuit die
US5223851A (en) * 1991-06-05 1993-06-29 Trovan Limited Apparatus for facilitating interconnection of antenna lead wires to an integrated circuit and encapsulating the assembly to form an improved miniature transponder device
US5149674A (en) * 1991-06-17 1992-09-22 Motorola, Inc. Method for making a planar multi-layer metal bonding pad
FR2687009B1 (fr) * 1992-01-31 1994-04-29 Sgs Thomson Microelectronics Composant de protection pour circuit automobile.
US5309025A (en) * 1992-07-27 1994-05-03 Sgs-Thomson Microelectronics, Inc. Semiconductor bond pad structure and method
SE500523C2 (sv) * 1992-10-09 1994-07-11 Elsa Elektroniska Systems And Halvledarkomponent med minst en första och en andra komponentelektrod innefattande ett flertal på en halvledarbricka integrerade halvledarelement, som vart och ett innefattar minst en första och en andra elementelektrod på samma sida av halvledarbrickan, varid de första elementelektroderna är förbundna med den första komponentelektroden och de andra elementelektroderna är förbundna med den andra komponentelektroden.
JP2807396B2 (ja) * 1993-05-25 1998-10-08 ローム株式会社 半導体装置
EP0637840A1 (en) * 1993-08-05 1995-02-08 AT&T Corp. Integrated circuit with active devices under bond pads
DE69330603T2 (de) * 1993-09-30 2002-07-04 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno, Catania Verfahren zur Metallisierung und Verbindung bei der Herstellung von Leistungshalbleiterbauelementen
US5523604A (en) * 1994-05-13 1996-06-04 International Rectifier Corporation Amorphous silicon layer for top surface of semiconductor device
DE69426293T2 (de) * 1994-07-13 2001-04-05 United Microelectronics Corp., Hsinchu Verfahren zur Reduzierung des Antenneneffekts während der Fabrikation
US5767546A (en) * 1994-12-30 1998-06-16 Siliconix Incorporated Laternal power mosfet having metal strap layer to reduce distributed resistance
US5665996A (en) * 1994-12-30 1997-09-09 Siliconix Incorporated Vertical power mosfet having thick metal layer to reduce distributed resistance
US5650355A (en) * 1995-03-30 1997-07-22 Texas Instruments Incorporated Process of making and process of trimming a fuse in a top level metal and in a step
US5965903A (en) * 1995-10-30 1999-10-12 Lucent Technologies Inc. Device and method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated therein
JP3510039B2 (ja) * 1996-03-15 2004-03-22 株式会社デンソー 半導体装置およびその製造方法
JPH10135270A (ja) * 1996-10-31 1998-05-22 Casio Comput Co Ltd 半導体装置及びその製造方法
US5900643A (en) * 1997-05-19 1999-05-04 Harris Corporation Integrated circuit chip structure for improved packaging
US6731007B1 (en) * 1997-08-29 2004-05-04 Hitachi, Ltd. Semiconductor integrated circuit device with vertically stacked conductor interconnections
TW411602B (en) * 1998-02-07 2000-11-11 Winbond Electronics Corp Semiconductor manufacturing process and its structure which can prevent bonding pad fall-off due to the plug process
US5986343A (en) * 1998-05-04 1999-11-16 Lucent Technologies Inc. Bond pad design for integrated circuits
US5942800A (en) * 1998-06-22 1999-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Stress buffered bond pad and method of making
US6037668A (en) * 1998-11-13 2000-03-14 Motorola, Inc. Integrated circuit having a support structure
TW445616B (en) * 1998-12-04 2001-07-11 Koninkl Philips Electronics Nv An integrated circuit device
US6965165B2 (en) 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US6936531B2 (en) 1998-12-21 2005-08-30 Megic Corporation Process of fabricating a chip structure
US8021976B2 (en) * 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
DE19908188A1 (de) * 1999-02-25 2000-09-07 Siemens Ag Verfahren zum Herstellen einer integrierten elektronischen Schaltung und integrierte elektronische Schaltung
US6486051B1 (en) 1999-03-17 2002-11-26 Intel Corporation Method for relieving bond stress in an under-bond-pad resistor
US6054721A (en) * 1999-07-14 2000-04-25 Advanced Micro Devices, Inc. Detection of undesired connection between conductive structures within multiple layers on a semiconductor wafer
US6693350B2 (en) 1999-11-24 2004-02-17 Denso Corporation Semiconductor device having radiation structure and method for manufacturing semiconductor device having radiation structure
US6703707B1 (en) * 1999-11-24 2004-03-09 Denso Corporation Semiconductor device having radiation structure
US6198170B1 (en) * 1999-12-16 2001-03-06 Conexant Systems, Inc. Bonding pad and support structure and method for their fabrication
KR100734250B1 (ko) * 2001-01-09 2007-07-02 삼성전자주식회사 단차를 구비하는 반도체 장치의 본딩 패드 및 이를제조하는 방법
JP2002222811A (ja) * 2001-01-24 2002-08-09 Seiko Epson Corp 半導体装置およびその製造方法
JP4479121B2 (ja) * 2001-04-25 2010-06-09 株式会社デンソー 半導体装置の製造方法
JP2003100756A (ja) * 2001-09-27 2003-04-04 Sanyo Electric Co Ltd 半導体装置
EP1306898A1 (en) * 2001-10-29 2003-05-02 Dialog Semiconductor GmbH Sub-milliohm on-chip interconnection
US7932603B2 (en) * 2001-12-13 2011-04-26 Megica Corporation Chip structure and process for forming the same
US6614091B1 (en) * 2002-03-13 2003-09-02 Motorola, Inc. Semiconductor device having a wire bond pad and method therefor
JP2003347351A (ja) * 2002-05-29 2003-12-05 Mitsubishi Electric Corp 半導体装置
US20040036131A1 (en) * 2002-08-23 2004-02-26 Micron Technology, Inc. Electrostatic discharge protection devices having transistors with textured surfaces
JP4445189B2 (ja) * 2002-08-29 2010-04-07 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US7023090B2 (en) * 2003-01-29 2006-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding pad and via structure design
US7495343B1 (en) 2003-07-31 2009-02-24 Nvidia Corporation Pad over active circuit system and method with frame support structure
US7453158B2 (en) * 2003-07-31 2008-11-18 Nvidia Corporation Pad over active circuit system and method with meshed support structure
US20060055056A1 (en) * 2003-11-21 2006-03-16 Denso Corporation Semiconductor equipment having a pair of heat radiation plates
US7560808B2 (en) * 2005-10-19 2009-07-14 Texas Instruments Incorporated Chip scale power LDMOS device
JP2007300139A (ja) * 2007-08-06 2007-11-15 Matsushita Electric Ind Co Ltd 半導体装置
US7998852B2 (en) 2008-12-04 2011-08-16 Freescale Semiconductor, Inc. Methods for forming an RF device with trench under bond pad feature

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5833705B2 (ja) * 1975-08-27 1983-07-21 株式会社日立製作所 タソウハイセンオ ユウスルハンドウタイソウチ
JPS5447476A (en) * 1977-09-21 1979-04-14 Hitachi Ltd Semiconductor device
JPS5553441A (en) * 1978-10-14 1980-04-18 Sony Corp Semiconductor device
JPS57176746A (en) * 1981-04-21 1982-10-30 Nippon Telegr & Teleph Corp <Ntt> Semiconductor integrated circuit and manufacture thereof
DE3280233D1 (de) * 1981-09-11 1990-10-04 Toshiba Kawasaki Kk Verfahren zum herstellen eines substrats fuer multischichtschaltung.
JPS5921034A (ja) * 1982-07-27 1984-02-02 Toshiba Corp 半導体装置
US4617193A (en) * 1983-06-16 1986-10-14 Digital Equipment Corporation Planar interconnect for integrated circuits
JPS6045048A (ja) * 1983-08-22 1985-03-11 Nec Corp 半導体装置
JPS6079746A (ja) * 1983-10-07 1985-05-07 Hitachi Ltd 半導体装置及びその機能変更方法
JPS60115245A (ja) * 1983-11-28 1985-06-21 Toshiba Corp 半導体装置の製造方法
US4656496A (en) * 1985-02-04 1987-04-07 National Semiconductor Corporation Power transistor emitter ballasting
JPS61239656A (ja) * 1985-04-16 1986-10-24 Citizen Watch Co Ltd 半導体装置
JPS6290950A (ja) * 1985-10-16 1987-04-25 Mitsubishi Electric Corp 半導体装置
US4795722A (en) * 1987-02-05 1989-01-03 Texas Instruments Incorporated Method for planarization of a semiconductor device prior to metallization
JPS63293930A (ja) * 1987-05-27 1988-11-30 Hitachi Ltd 半導体装置における電極

Also Published As

Publication number Publication date
EP0291014B1 (en) 1993-04-07
US4984061A (en) 1991-01-08
EP0291014A2 (en) 1988-11-17
JPS63283040A (ja) 1988-11-18
DE3880003D1 (de) 1993-05-13
EP0291014A3 (en) 1989-07-12
JPH0546973B2 (enExample) 1993-07-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee