JP3510039B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法

Info

Publication number
JP3510039B2
JP3510039B2 JP05878396A JP5878396A JP3510039B2 JP 3510039 B2 JP3510039 B2 JP 3510039B2 JP 05878396 A JP05878396 A JP 05878396A JP 5878396 A JP5878396 A JP 5878396A JP 3510039 B2 JP3510039 B2 JP 3510039B2
Authority
JP
Japan
Prior art keywords
insulating film
interlayer insulating
electrode
bonding
alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP05878396A
Other languages
English (en)
Other versions
JPH09252019A (ja
Inventor
康生 石原
晴夫 川北
直人 岡部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP05878396A priority Critical patent/JP3510039B2/ja
Priority to DE19709764A priority patent/DE19709764B4/de
Priority to US08/818,729 priority patent/US5801445A/en
Publication of JPH09252019A publication Critical patent/JPH09252019A/ja
Application granted granted Critical
Publication of JP3510039B2 publication Critical patent/JP3510039B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05073Single internal layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • H01L2224/05558Shape in side view conformal layer on a patterned surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48699Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48717Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48724Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85205Ultrasonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01018Argon [Ar]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049Nitrides composed of metals from groups of the periodic table
    • H01L2924/050414th Group
    • H01L2924/05042Si3N4
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • H01L2924/12036PN diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20Parameters
    • H01L2924/207Diameter ranges
    • H01L2924/2076Diameter ranges equal to or larger than 100 microns

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【発明の詳細な説明】
【0001】
【発明の属する技術分野】本発明は、半導体基板上に形
成された層間絶縁膜上にシリコン微粒子(以下Si微粒
子と称す)を含む金属材料よりなる電極を有する半導体
装置およびその製造方法に関するものである。
【0002】
【従来の技術】従来、集積回路(IC)装置(以下、I
Cチップという)は、半導体基板に抵抗・トランジス
タ・コンデンサ等の素子が形成され、それら素子上に
は、これら素子を保護するとともに、素子間の絶縁性を
保持するために、層間絶縁膜3が形成されている。さら
に、この層間絶縁膜3上には、上記ICチップと外部回
路とを電気的に接続するための金属材料としてアルミニ
ウム(以下Alと称す)等の薄膜から成る電極5が形成
されている。しかし、この電極に不純物を含まないAl
(以下純Alという)を用いた場合には、図4に示した
ように、Si半導体基板を構成するSi基板1と電極5
中に含有されるAlが直接接触するコンタクト部7にS
iがAl中に溶解することで生じたアロイスパイク9と
よばれるAlの突き抜けが発生する。このアロイスパイ
ク9がSi基板1に発生するとPN接合を破壊し素子の
特性に大きな影響を与える。
【0003】そのため、従来では、電極5のAl中にあ
らかじめSiを1〜2wt%程度含ませた合金(以下A
l- Si合金という)を使用することで、この現象を防
いでいた。
【0004】
【発明が解決しようとする課題】しかしながら、上述の
電極5には過剰のSiが含有されているため、図5に示
すようにAl結晶粒界などにSi微粒子10が必ず析出
して問題が生じる。この問題を図6を用いて説明する。
即ち、半導体基板にAlワイヤ12を超音波接合させよ
うとする場合において、この電極5上にワイヤボンディ
ングを施すこととなる。
【0005】しかしながら、ワイヤボンディングの箇所
がトランジスタセル14上で行われた場合には、層間絶
縁膜3上に析出したSi微粒子10が、ボンディングの
際の振動のエネルギーAを受け、層間絶縁膜3にクラッ
ク16を生じさせる。そして、このクラック16がトラ
ンジスタセル14を破壊し、その結果リークを生じ、I
Cチップを不良とさせてしまうという問題が生じるので
ある。
【0006】本発明は、上記の課題を解決するために成
されたものであり、その目的とするところは、アロイス
パイクの発生を抑制すると同時に層間絶縁膜上に析出し
たSi微粒子によるボンディング時の不良をなくした半
導体装置を提供することである。
【0007】
【課題を解決するための手段】我々は、はじめにこれら
の原因に対して鋭意研究した結果、以下のような新規な
知見を見いだした。即ち、従来においては、Si微粒子
10が析出した層間絶縁膜3上にワイヤボンディングな
どを行っても必ずしもICチップ不良とはならない。
【0008】このような品質上の不安定要因を解明した
ところ、我々発明者らはボンディング用電極における層
間絶縁膜のクラック発生メカニズムが以下のようなもの
であることを見いだしたのである。この研究成果とし
て、図7に示すようにSi微粒子10の析出位置が層間
絶縁膜3上にあり、そのSi微粒子10と層間絶縁膜3
との接触界面に反応接合層18を生じている場合におい
てワイヤボンディング時に不良となることを見出し、以
下のように新規なボンディング電極を提供するに至った
のである。
【0009】即ち、発明の構成としては、層間絶縁膜と
ワイヤとによって挟まれた部分の電極の成分として、主
成分がアルミニウムであって、さらにシリコン微粒子が
0.1〜0.6wt%含有されている電極とすることに
よって、ワイヤ接合時において、ボンディング用電極に
大きな超音波パワーや大きな荷重等を作用させたとき、
下地の層間絶縁膜に直接パワーを伝えることがなく、ク
ラックなどのダメージが生じ難くすることができる。即
ち、本発明のボンディング用電極が形成されたICチッ
プなどのデバイスにおいては、ボンディング不良が低減
され、かつアロイスパイクの発生を抑えた信頼性の高い
ものとすることができる。
【0010】さらに、本発明においては、シリコン微粒
子が0.1〜0.6wt%よりなるターゲットを用い
て、前記層間絶縁膜上に電極を形成することにより、ボ
ンディング不良が低減され、かつアロイスパイクの発生
を抑えた信頼性の高い半導体装置を得ることができる。
【0011】
【発明の実施の形態】以下、本発明を具体的な実施例に
基づいて説明する。図1は本発明に係る半導体装置を構
成するボンディング用電極におけるSi微粒子の発生状
態を示した断面模式図である。図1において、半導体基
板であるSi基板1には、その内部或いは上部に公知の
パワーMOSやIGBT等によって形成された、図に示
されないトランジスタ・抵抗・コンデンサなどの素子が
形成されている。また、上記Si基板1上には、CVD
法などにより層間絶縁膜3が形成されている。この層間
絶縁膜3は、例えば、BPSG(Boron-Phosphorus S
ilicate Glass)膜やPSG(Phosphorus Silicate
Glass)膜などから成る。そして、この上にスパッタリ
ング法によりボンディング用電極となるAl−Si合金
材料から成るAl−Si膜である電極5を堆積する。
【0012】尚、上記スパッタリング条件としては、パ
ワー7.2kw、ガス圧6mTorr、基板加熱温度1
50℃にて、0.5wt%のSiを含有するAl−Si
合金から成るターゲットを用いた。又、基板加熱は半導
体基板をチャックするステージのヒーターにより加熱さ
れたArガスを基板裏面に吹き付けることにより行い、
温度はヒーターに通電する電流量により制御した。
【0013】次に、上記電極5をフォトエッチングによ
り所定のパターンにパターニングする。この後、450
℃で30分のシンタリングを施す。このシンタリングに
より、コンタクト7ではSi基板1と電極5とが電気的
に良好に接続されるのである。得られた半導体装置は、
アルミニウムを主成分とし、平均粒径1μmのSi微粒
子が0.5wt%含有された電極を有している。本実施
例においては、電極として、Si微粒子の低い含有量と
することによって、不良がなく良好なボンディング構造
を有した半導体素子とすることができた。
【0014】本発明においては、電極に含有させるSi
微粒子量としては、0.1〜0.6wt%が良い。その
理由を以下詳述する。ここで、図2において、ボンディ
ング用電極における層間絶縁膜上のSi微粒子と層間絶
縁膜との間に形成された反応接合層の数とAl−Si合
金ターゲット中のSi含有量の関係を示す。
【0015】ここで、層間絶縁膜上のSi微粒子と層間
絶縁膜の間に形成された反応接合層の数は、ボンディン
グ用電極を塩酸等によりウェットエッチングし、更に、
超音波洗浄によってSi微粒子を完全除去した後、SE
M等によりその表面を観察し、Si微粒子により生じた
くぼみの数(個/2000μm2 )によって確認した。
これは、ボンディングにより不良を生じたサンプルの
Si微粒子と層間絶縁膜の界面を実験分析により詳細に
観察したところ、図7に示す反応接合層18ができてい
ることが観察さるので、層間絶縁膜上のSi微粒子と層
間絶縁膜の間に反応接合層が生じていれば超音波洗浄に
よるSi微粒子の除去がされたとき、反応接合層ととも
に除去されるために層間絶縁膜上にくぼみが生じること
となり、結合の数を数えることが可能となることを利用
したものである。
【0016】図2から、Al−Si合金ターゲット中の
Si含有量を0.6wt%以下とすることによって、層
間絶縁膜上のSi微粒子と層間絶縁膜の間に形成された
反応接合層の数が低減することがわかる。図3はボンデ
ィング用電極に対してAlワイヤ径400μm ×6本、
荷重500〜600gf、超音波パワー90〜110でワ
イヤボンディングを実施した場合の不良率とAl−Si
合金ターゲット中のSi含有量の関係を示した特性図で
ある。
【0017】図3から、Al−Si合金ターゲット中の
Si含有量を0.6wt%以下とすることによって、不
良率を大幅に低減させることができることがわかる。即
ち、図2と図3を照らし合わせると、層間絶縁膜上のS
i微粒子と層間絶縁膜の結合界面の反応接合層を低減す
れば、不良率が低減することは明白であり、反応接合層
の低減も、Al−Si合金ターゲット中のSi含有量を
0.6wt%以下とすることによって、達成することが
できることがわかる。
【0018】また、Si含有量0.5wt%のAl−S
i合金を電極に用いた時の、アロイスパイクの深さを測
定したところその深さは0.2〜0.5μmであり、パ
ワー素子などのデバイスで用いる場合、特に問題の生じ
ない深さであることが確認された。ここで、Al−Si
合金ターゲット中のSi含有量とこのターゲットから得
られる電極の成分とはほぼ相関関係があり、例えば、S
iが0.5wt%含有されたAl−Si合金ターゲット
を用いた場合には、それから得られた電極もSiがほぼ
0.5wt%含有された電極とすることができることが
確認されている。
【0019】尚、本発明のボンディング用電極において
は、Al−Si合金中のSi含有量を0.1〜0.6w
t%の間の極微量で正確に調整されたターゲットを用い
ることにより成膜される。そのため、成膜時に発生する
Si微粒子は非常に小さく、膜中に均一に分散されてい
る。 さらに、その後の熱処理においてSi微粒子は、
固溶限界まで膜中に溶解する。そして冷却過程で再析出
する際、Si含有量を0.1〜0.6wt%と極微量に
抑えてあるため、層間絶縁膜上の成長核は非常に少なく
なっており、層間絶縁膜上でのSi微粒子の成長は抑制
される。そして、Si微粒子の成長が抑制されているこ
とにより、Si微粒子と層間絶縁膜の間に発生する応力
が小さいため接触界面の反応接合層は形成されないこと
となる。
【0020】このため、Al−Si膜中にSi微粒子が
発生しても、Si微粒子と層間絶縁膜の接合界面に反応
接合層が形成されないため、ワイヤボンディングなどに
おいて層間絶縁膜のクラック発生を極めて少なくでき
る。また、電極中にSiが最低でも0.1wt%含まれ
ているため、Si基板から溶出するSiを抑えることが
可能となり、アロイスパイクの発生も抑制できる。
【0021】即ち、本発明によるボンディング用電極を
用いることにより、ボンディングにおける品質を極めて
安定したものとすることができると同時にデバイスの信
頼性も安定したものとすることができる。尚、上述の実
施例においては、Al−Si膜上にワイヤボンディング
する際について述べたが、この他、バンプ等にAl−S
i膜上から超音波・荷重が作用し、下地にクラックなど
のダメージが生じる場合にも本発明を適用してダメージ
を緩和することができる。
【0022】また、上記実施例においては、Si微粒子
として平均粒径1μmのものを採用したが、Si微粒子
が0.1〜3.5μmであっても、本願発明の作用・効
果を有することができる。
【図面の簡単な説明】
【図1】本発明の半導体素子の一部を示す模式断面図
【図2】Si含有量に対する反応接合層の数の関係を示
す関係図。
【図3】Si含有量に対する不良率の関係を示す関係
図。
【図4】従来の不良発生を説明する説明図。
【図5】従来の構造を説明する説明図。
【図6】従来の問題発生過程を説明する説明図。
【図7】従来の問題発生原因を説明する説明図。
【符号の説明】
1 半導体基板 3 層間絶縁膜 5 電極 12 ワイヤ
───────────────────────────────────────────────────── フロントページの続き (72)発明者 岡部 直人 愛知県刈谷市昭和町1丁目1番地 日本 電装株式会社内 (56)参考文献 特開 平7−240432(JP,A) 特開 平4−367224(JP,A) 特開 平6−132508(JP,A)

Claims (2)

    (57)【特許請求の範囲】
  1. 【請求項1】 パワー素子デバイスが形成されたシリコ
    ン基板と、該シリコン基板上に設けられた層間絶縁膜
    と、該層間絶縁膜上に形成され、前記シリコン基板とコ
    ンタクト部にて電気的に接続する電極と、該電極上に接
    合されたワイヤとからなる半導体装置であって、 前記電極の成分は、主成分がアルミニウムでシリコンが
    含有されたものであって、前記層間絶縁膜上のシリコン
    微粒子と層間絶縁膜との間の反応接合層を低減させるべ
    くシリコンの含有量が0.1〜0.6wt%とされてお
    り、 前記パワー素子デバイスは、0.2〜0.5μmの深さ
    のアロイスパイクで前記コンタクト部のPN接合が破壊
    されないことを特徴とする半導体装置。
  2. 【請求項2】 シリコン基板に0.2〜0.5μmの深
    さのアロイスパイクでコンタクト部のPN接合が破壊さ
    れないパワー素子デバイスを形成し、 該シリコン基板上に層間絶縁膜を形成し、 シリコン含有量が0.1〜0.6wt%の間で調整され
    アルミニウム−シリコン合金ターゲットを用いて、前
    記コンタクト部にて前記シリコン基板に電気的に接続す
    る電極を前記層間絶縁膜上に形成し、 前記層間絶縁膜上に、前記電極を介してワイヤを超音波
    振動によって接合することを特徴とする半導体装置の製
    造方法。
JP05878396A 1996-03-15 1996-03-15 半導体装置およびその製造方法 Expired - Fee Related JP3510039B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP05878396A JP3510039B2 (ja) 1996-03-15 1996-03-15 半導体装置およびその製造方法
DE19709764A DE19709764B4 (de) 1996-03-15 1997-03-10 Halbleitervorrichtung mit Elektrode aus Aluminium und feinkörnigem Silizium und ihr Herstellungsverfahren
US08/818,729 US5801445A (en) 1996-03-15 1997-03-14 Semiconductor device and method of manufacturing same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP05878396A JP3510039B2 (ja) 1996-03-15 1996-03-15 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
JPH09252019A JPH09252019A (ja) 1997-09-22
JP3510039B2 true JP3510039B2 (ja) 2004-03-22

Family

ID=13094178

Family Applications (1)

Application Number Title Priority Date Filing Date
JP05878396A Expired - Fee Related JP3510039B2 (ja) 1996-03-15 1996-03-15 半導体装置およびその製造方法

Country Status (3)

Country Link
US (1) US5801445A (ja)
JP (1) JP3510039B2 (ja)
DE (1) DE19709764B4 (ja)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000106401A (ja) * 1998-09-29 2000-04-11 Sony Corp メモリ素子およびその製造方法ならびに集積回路
US6693350B2 (en) 1999-11-24 2004-02-17 Denso Corporation Semiconductor device having radiation structure and method for manufacturing semiconductor device having radiation structure
US6703707B1 (en) * 1999-11-24 2004-03-09 Denso Corporation Semiconductor device having radiation structure
JP4479121B2 (ja) * 2001-04-25 2010-06-09 株式会社デンソー 半導体装置の製造方法
US6650010B2 (en) * 2002-02-15 2003-11-18 International Business Machines Corporation Unique feature design enabling structural integrity for advanced low K semiconductor chips

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4546374A (en) * 1981-03-23 1985-10-08 Motorola Inc. Semiconductor device including plateless package
US4558345A (en) * 1983-10-27 1985-12-10 Rca Corporation Multiple connection bond pad for an integrated circuit device and method of making same
JPS6095947A (ja) * 1983-10-31 1985-05-29 Tanaka Denshi Kogyo Kk 半導体素子のボンデイング用Al線
JPS63283040A (ja) * 1987-05-15 1988-11-18 Toshiba Corp 半導体装置
US5260604A (en) * 1988-09-27 1993-11-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with improved immunity to contact and conductor defects
US5229646A (en) * 1989-01-13 1993-07-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with a copper wires ball bonded to aluminum electrodes
JPH06132508A (ja) * 1992-10-20 1994-05-13 Sony Corp 固体撮像素子とその製造方法
JP3371504B2 (ja) * 1993-01-25 2003-01-27 株式会社デンソー 合金電極にワイヤボンディングされた半導体装置及び合金電極の製造方法
JPH0845874A (ja) * 1994-07-30 1996-02-16 Mitsumi Electric Co Ltd 半導体装置

Also Published As

Publication number Publication date
DE19709764A1 (de) 1997-11-06
JPH09252019A (ja) 1997-09-22
US5801445A (en) 1998-09-01
DE19709764B4 (de) 2007-08-30

Similar Documents

Publication Publication Date Title
US4937652A (en) Semiconductor device and method of manufacturing the same
JP3787366B2 (ja) 背面を金属化した半導体及びその製造方法
US20030049923A1 (en) Method to improve the reliability of thermosonic gold to aluminum wire bonds
JP3510039B2 (ja) 半導体装置およびその製造方法
JPH03127843A (ja) 半導体集積回路装置
JP2976931B2 (ja) 半導体装置の製造方法
JPH05218021A (ja) 半導体装置
JP3371504B2 (ja) 合金電極にワイヤボンディングされた半導体装置及び合金電極の製造方法
JP2000100816A (ja) 半導体装置
JP4231580B2 (ja) 半導体装置
JPH07135234A (ja) パワー半導体モジュール
JPS62130248A (ja) ボンデイング用銅細線
JPH06196526A (ja) 半導体装置の製造方法
JPH0682704B2 (ja) 半導体装置
JP3394155B2 (ja) 金属薄膜形成方法
JPH0648880Y2 (ja) 半導体装置
JP3373701B2 (ja) 半導体素子、半導体装置およびその製造方法
JP3879658B2 (ja) 電子部品製造方法
JP3688335B2 (ja) 半導体集積回路装置およびその製造方法ならびに半導体ウエハ
JP2723023B2 (ja) 半導体装置およびその製造方法
JP2727605B2 (ja) 半導体装置及びその製造方法
JPH06333977A (ja) 半導体装置及びその製造方法
JPH0964033A (ja) 半導体装置の製造方法
TW200305266A (en) Semiconductor device and a method of manufacturing the same
JPH05251497A (ja) 半導体装置

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20020212

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20031224

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110109

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120109

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130109

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140109

Year of fee payment: 10

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees