DE69125047T2 - Halbleiteranordnung mit einer isolierenden Schicht - Google Patents

Halbleiteranordnung mit einer isolierenden Schicht

Info

Publication number
DE69125047T2
DE69125047T2 DE69125047T DE69125047T DE69125047T2 DE 69125047 T2 DE69125047 T2 DE 69125047T2 DE 69125047 T DE69125047 T DE 69125047T DE 69125047 T DE69125047 T DE 69125047T DE 69125047 T2 DE69125047 T2 DE 69125047T2
Authority
DE
Germany
Prior art keywords
insulating layer
semiconductor arrangement
semiconductor
arrangement
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69125047T
Other languages
English (en)
Other versions
DE69125047D1 (de
Inventor
Kenichi Shirai
Satoshi Shibahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Publication of DE69125047D1 publication Critical patent/DE69125047D1/de
Application granted granted Critical
Publication of DE69125047T2 publication Critical patent/DE69125047T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Formation Of Insulating Films (AREA)
DE69125047T 1990-03-23 1991-03-25 Halbleiteranordnung mit einer isolierenden Schicht Expired - Fee Related DE69125047T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7213490 1990-03-23
JP07868591A JP3144817B2 (ja) 1990-03-23 1991-02-18 半導体装置

Publications (2)

Publication Number Publication Date
DE69125047D1 DE69125047D1 (de) 1997-04-17
DE69125047T2 true DE69125047T2 (de) 1997-07-31

Family

ID=26413262

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69125047T Expired - Fee Related DE69125047T2 (de) 1990-03-23 1991-03-25 Halbleiteranordnung mit einer isolierenden Schicht

Country Status (4)

Country Link
US (1) US5296745A (de)
EP (1) EP0453787B1 (de)
JP (1) JP3144817B2 (de)
DE (1) DE69125047T2 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2268327A (en) * 1992-06-30 1994-01-05 Texas Instruments Ltd Passivated gallium arsenide device
CA2106025A1 (en) * 1992-09-14 1994-03-15 Jack S. Kilby Packaged integrated circuits
JPH06151616A (ja) * 1992-11-14 1994-05-31 Toshiba Corp 半導体集積回路装置及びその製造方法
US5891745A (en) * 1994-10-28 1999-04-06 Honeywell Inc. Test and tear-away bond pad design
TW293152B (en) * 1995-07-28 1996-12-11 Hitachi Ltd Semiconductor integrated circuit device and fabricating method thereof
KR100230984B1 (ko) * 1996-07-24 1999-11-15 김광호 반도체장치의 비피에스지에 포함된 불순물 측정시 이용되는 계측설비 설정값 보정용 기준 샘플 제조 방법
US5994762A (en) * 1996-07-26 1999-11-30 Hitachi, Ltd. Semiconductor integrated circuit device including boron-doped phospho silicate glass layer and manufacturing method thereof
EP0856886B1 (de) * 1997-01-31 2003-06-25 STMicroelectronics S.r.l. Verfahren zur Herstellung von einer Randstruktur um ein integriertes elektronisches Bauelement zu versiegeln, sowie ein entsprechendes Bauelement
EP0856887B1 (de) * 1997-01-31 2004-04-28 SGS-THOMSON MICROELECTRONICS S.r.l. Verfahren zur Herstellung von einer morphologischen Randstruktur um ein integriertes elektronisches Bauelement zu versiegeln, sowie ein entsprechendes Bauelement
KR100314133B1 (ko) 1999-11-26 2001-11-15 윤종용 가장자리에 흡습방지막이 형성된 반도체 칩 및 이흡습방지막의 형성방법
US6369453B1 (en) * 2000-08-11 2002-04-09 Advanced Micro Devices, Inc. Semiconductor wafer for measurement and recordation of impurities in semiconductor insulators
US6492247B1 (en) * 2000-11-21 2002-12-10 International Business Machines Corporation Method for eliminating crack damage induced by delaminating gate conductor interfaces in integrated circuits
JP2004296905A (ja) 2003-03-27 2004-10-21 Toshiba Corp 半導体装置
US7968146B2 (en) 2006-11-01 2011-06-28 The Trustees Of Princeton University Hybrid layers for use in coatings on electronic devices or other articles
KR20150038544A (ko) 2008-05-07 2015-04-08 더 트러스티즈 오브 프린스턴 유니버시티 전자 장치들 또는 다른 물품들 위의 코팅들에 사용하기 위한 혼성 층들
US8649820B2 (en) 2011-11-07 2014-02-11 Blackberry Limited Universal integrated circuit card apparatus and related methods
US8936199B2 (en) 2012-04-13 2015-01-20 Blackberry Limited UICC apparatus and related methods
USD703208S1 (en) 2012-04-13 2014-04-22 Blackberry Limited UICC apparatus
USD701864S1 (en) * 2012-04-23 2014-04-01 Blackberry Limited UICC apparatus
CN103426908A (zh) * 2012-05-24 2013-12-04 上海宏力半导体制造有限公司 一种能保护硼磷硅玻璃层的半导体结构及其制造方法
CN105679756B (zh) * 2015-11-25 2018-08-10 杭州立昂微电子股份有限公司 一种半导体器件顶层金属的终端结构及其制造方法
KR101796514B1 (ko) * 2016-03-21 2017-12-01 주식회사 신명프라텍 클리어 파일 제조방법

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS501872B1 (de) * 1970-01-30 1975-01-22
US4001872A (en) * 1973-09-28 1977-01-04 Rca Corporation High-reliability plastic-packaged semiconductor device
JPS5943557A (ja) * 1982-09-06 1984-03-10 Hitachi Ltd 半導体装置
JPS5955037A (ja) * 1982-09-24 1984-03-29 Hitachi Ltd 半導体装置
US4984039A (en) * 1985-05-03 1991-01-08 Texas Instruments Incorporated Tapered trench structure and process
JPS62181436A (ja) * 1986-02-05 1987-08-08 Matsushita Electronics Corp 半導体装置
US4916509A (en) * 1987-11-13 1990-04-10 Siliconix Incorporated Method for obtaining low interconnect resistance on a grooved surface and the resulting structure
JPH07114240B2 (ja) * 1987-11-17 1995-12-06 三菱電機株式会社 半導体記憶装置およびその製造方法
JPH02137364A (ja) * 1988-11-18 1990-05-25 Toshiba Corp 半導体記憶装置
JPH02181925A (ja) * 1989-01-07 1990-07-16 Mitsubishi Electric Corp 半導体装置
US4985740A (en) * 1989-06-01 1991-01-15 General Electric Company Power field effect devices having low gate sheet resistance and low ohmic contact resistance
US5017999A (en) * 1989-06-30 1991-05-21 Honeywell Inc. Method for forming variable width isolation structures

Also Published As

Publication number Publication date
EP0453787A3 (en) 1992-07-08
EP0453787B1 (de) 1997-03-12
DE69125047D1 (de) 1997-04-17
US5296745A (en) 1994-03-22
EP0453787A2 (de) 1991-10-30
JP3144817B2 (ja) 2001-03-12
JPH04279050A (ja) 1992-10-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee