EP0291014A3 - Semiconductor device in which wiring layer is formed below bonding pad - Google Patents
Semiconductor device in which wiring layer is formed below bonding pad Download PDFInfo
- Publication number
- EP0291014A3 EP0291014A3 EP88107501A EP88107501A EP0291014A3 EP 0291014 A3 EP0291014 A3 EP 0291014A3 EP 88107501 A EP88107501 A EP 88107501A EP 88107501 A EP88107501 A EP 88107501A EP 0291014 A3 EP0291014 A3 EP 0291014A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- semiconductor device
- wiring layer
- bonding pad
- formed below
- below bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
- H01L2224/48624—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85203—Thermocompression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0504—14th Group
- H01L2924/05042—Si3N4
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
- Bipolar Transistors (AREA)
- Local Oxidation Of Silicon (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62116727A JPS63283040A (en) | 1987-05-15 | 1987-05-15 | Semiconductor device |
JP116727/87 | 1987-05-15 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0291014A2 EP0291014A2 (en) | 1988-11-17 |
EP0291014A3 true EP0291014A3 (en) | 1989-07-12 |
EP0291014B1 EP0291014B1 (en) | 1993-04-07 |
Family
ID=14694302
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP88107501A Expired - Lifetime EP0291014B1 (en) | 1987-05-15 | 1988-05-10 | Semiconductor device in which wiring layer is formed below bonding pad |
Country Status (4)
Country | Link |
---|---|
US (1) | US4984061A (en) |
EP (1) | EP0291014B1 (en) |
JP (1) | JPS63283040A (en) |
DE (1) | DE3880003T2 (en) |
Families Citing this family (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2593965B2 (en) * | 1991-01-29 | 1997-03-26 | 三菱電機株式会社 | Semiconductor device |
BR9205671A (en) * | 1991-02-25 | 1994-02-17 | Ake Gustafson | Process of fixing a winding to an electronic circuit |
US5223851A (en) * | 1991-06-05 | 1993-06-29 | Trovan Limited | Apparatus for facilitating interconnection of antenna lead wires to an integrated circuit and encapsulating the assembly to form an improved miniature transponder device |
US5281855A (en) * | 1991-06-05 | 1994-01-25 | Trovan Limited | Integrated circuit device including means for facilitating connection of antenna lead wires to an integrated circuit die |
US5149674A (en) * | 1991-06-17 | 1992-09-22 | Motorola, Inc. | Method for making a planar multi-layer metal bonding pad |
FR2687009B1 (en) * | 1992-01-31 | 1994-04-29 | Sgs Thomson Microelectronics | PROTECTIVE COMPONENT FOR AUTOMOTIVE CIRCUIT. |
US5309025A (en) * | 1992-07-27 | 1994-05-03 | Sgs-Thomson Microelectronics, Inc. | Semiconductor bond pad structure and method |
SE500523C2 (en) * | 1992-10-09 | 1994-07-11 | Elsa Elektroniska Systems And | Semiconductor component having at least one first and second component electrode comprising a plurality of semiconductor chip integral elements, each comprising at least one first and second element electrode on the same side of the semiconductor chip, wherein the first element electrodes are connected to the first component electrode and the second element electrode are connected to the second component electrode. |
JP2807396B2 (en) * | 1993-05-25 | 1998-10-08 | ローム株式会社 | Semiconductor device |
EP0637840A1 (en) * | 1993-08-05 | 1995-02-08 | AT&T Corp. | Integrated circuit with active devices under bond pads |
EP0646959B1 (en) * | 1993-09-30 | 2001-08-16 | Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno | Metallization and bonding process for manufacturing power semiconductor devices |
US5523604A (en) * | 1994-05-13 | 1996-06-04 | International Rectifier Corporation | Amorphous silicon layer for top surface of semiconductor device |
EP0693782B1 (en) * | 1994-07-13 | 2000-11-15 | United Microelectronics Corporation | Method for reducing process antenna effect |
US5665996A (en) * | 1994-12-30 | 1997-09-09 | Siliconix Incorporated | Vertical power mosfet having thick metal layer to reduce distributed resistance |
US5767546A (en) * | 1994-12-30 | 1998-06-16 | Siliconix Incorporated | Laternal power mosfet having metal strap layer to reduce distributed resistance |
US5650355A (en) * | 1995-03-30 | 1997-07-22 | Texas Instruments Incorporated | Process of making and process of trimming a fuse in a top level metal and in a step |
US5965903A (en) * | 1995-10-30 | 1999-10-12 | Lucent Technologies Inc. | Device and method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated therein |
JP3510039B2 (en) * | 1996-03-15 | 2004-03-22 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
JPH10135270A (en) * | 1996-10-31 | 1998-05-22 | Casio Comput Co Ltd | Semiconductor device and manufacture thereof |
US5900643A (en) * | 1997-05-19 | 1999-05-04 | Harris Corporation | Integrated circuit chip structure for improved packaging |
US6731007B1 (en) * | 1997-08-29 | 2004-05-04 | Hitachi, Ltd. | Semiconductor integrated circuit device with vertically stacked conductor interconnections |
TW411602B (en) * | 1998-02-07 | 2000-11-11 | Winbond Electronics Corp | Semiconductor manufacturing process and its structure which can prevent bonding pad fall-off due to the plug process |
US5986343A (en) * | 1998-05-04 | 1999-11-16 | Lucent Technologies Inc. | Bond pad design for integrated circuits |
US5942800A (en) * | 1998-06-22 | 1999-08-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Stress buffered bond pad and method of making |
US6037668A (en) * | 1998-11-13 | 2000-03-14 | Motorola, Inc. | Integrated circuit having a support structure |
TW445616B (en) * | 1998-12-04 | 2001-07-11 | Koninkl Philips Electronics Nv | An integrated circuit device |
US6936531B2 (en) * | 1998-12-21 | 2005-08-30 | Megic Corporation | Process of fabricating a chip structure |
US8021976B2 (en) * | 2002-10-15 | 2011-09-20 | Megica Corporation | Method of wire bonding over active area of a semiconductor circuit |
US6965165B2 (en) * | 1998-12-21 | 2005-11-15 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
DE19908188A1 (en) * | 1999-02-25 | 2000-09-07 | Siemens Ag | Integrated electronic circuit manufacturing method |
US6486051B1 (en) * | 1999-03-17 | 2002-11-26 | Intel Corporation | Method for relieving bond stress in an under-bond-pad resistor |
US6054721A (en) * | 1999-07-14 | 2000-04-25 | Advanced Micro Devices, Inc. | Detection of undesired connection between conductive structures within multiple layers on a semiconductor wafer |
US6703707B1 (en) * | 1999-11-24 | 2004-03-09 | Denso Corporation | Semiconductor device having radiation structure |
US6693350B2 (en) | 1999-11-24 | 2004-02-17 | Denso Corporation | Semiconductor device having radiation structure and method for manufacturing semiconductor device having radiation structure |
US6198170B1 (en) | 1999-12-16 | 2001-03-06 | Conexant Systems, Inc. | Bonding pad and support structure and method for their fabrication |
KR100734250B1 (en) * | 2001-01-09 | 2007-07-02 | 삼성전자주식회사 | Bonding pad of semiconductor memory device for improving adhesive strength bonding pad and bonding wire and method of manufacturing the same |
JP2002222811A (en) * | 2001-01-24 | 2002-08-09 | Seiko Epson Corp | Semiconductor device and manufacturing method therefor |
JP4479121B2 (en) | 2001-04-25 | 2010-06-09 | 株式会社デンソー | Manufacturing method of semiconductor device |
JP2003100756A (en) * | 2001-09-27 | 2003-04-04 | Sanyo Electric Co Ltd | Semiconductor device |
EP1306898A1 (en) * | 2001-10-29 | 2003-05-02 | Dialog Semiconductor GmbH | Sub-milliohm on-chip interconnection |
US7932603B2 (en) | 2001-12-13 | 2011-04-26 | Megica Corporation | Chip structure and process for forming the same |
US6614091B1 (en) * | 2002-03-13 | 2003-09-02 | Motorola, Inc. | Semiconductor device having a wire bond pad and method therefor |
JP2003347351A (en) * | 2002-05-29 | 2003-12-05 | Mitsubishi Electric Corp | Semiconductor device |
US20040036131A1 (en) * | 2002-08-23 | 2004-02-26 | Micron Technology, Inc. | Electrostatic discharge protection devices having transistors with textured surfaces |
JP4445189B2 (en) | 2002-08-29 | 2010-04-07 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
US7023090B2 (en) * | 2003-01-29 | 2006-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding pad and via structure design |
US7453158B2 (en) * | 2003-07-31 | 2008-11-18 | Nvidia Corporation | Pad over active circuit system and method with meshed support structure |
US7495343B1 (en) | 2003-07-31 | 2009-02-24 | Nvidia Corporation | Pad over active circuit system and method with frame support structure |
DE102004055908A1 (en) * | 2003-11-21 | 2005-07-28 | Denso Corp., Kariya | Semiconductor device such as an Insulating Gate Bipolar Transistor has pair of heat dissipating plates and heat dissipating block placed close to the device |
US7560808B2 (en) * | 2005-10-19 | 2009-07-14 | Texas Instruments Incorporated | Chip scale power LDMOS device |
JP2007300139A (en) * | 2007-08-06 | 2007-11-15 | Matsushita Electric Ind Co Ltd | Semiconductor device |
US7998852B2 (en) * | 2008-12-04 | 2011-08-16 | Freescale Semiconductor, Inc. | Methods for forming an RF device with trench under bond pad feature |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0100100A2 (en) * | 1982-07-27 | 1984-02-08 | Kabushiki Kaisha Toshiba | Semiconductor device with an improved bonding section |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5833705B2 (en) * | 1975-08-27 | 1983-07-21 | 株式会社日立製作所 | Hands-on-hand training |
JPS5447476A (en) * | 1977-09-21 | 1979-04-14 | Hitachi Ltd | Semiconductor device |
JPS5553441A (en) * | 1978-10-14 | 1980-04-18 | Sony Corp | Semiconductor device |
JPS57176746A (en) * | 1981-04-21 | 1982-10-30 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor integrated circuit and manufacture thereof |
DE3280233D1 (en) * | 1981-09-11 | 1990-10-04 | Toshiba Kawasaki Kk | METHOD FOR PRODUCING A SUBSTRATE FOR MULTI-LAYER SWITCHING. |
US4617193A (en) * | 1983-06-16 | 1986-10-14 | Digital Equipment Corporation | Planar interconnect for integrated circuits |
JPS6045048A (en) * | 1983-08-22 | 1985-03-11 | Nec Corp | Semiconductor device |
JPS6079746A (en) * | 1983-10-07 | 1985-05-07 | Hitachi Ltd | Semiconductor device and modification of function thereof |
JPS60115245A (en) * | 1983-11-28 | 1985-06-21 | Toshiba Corp | Manufacture of semiconductor device |
US4656496A (en) * | 1985-02-04 | 1987-04-07 | National Semiconductor Corporation | Power transistor emitter ballasting |
JPS61239656A (en) * | 1985-04-16 | 1986-10-24 | Citizen Watch Co Ltd | Semiconductor device |
JPS6290950A (en) * | 1985-10-16 | 1987-04-25 | Mitsubishi Electric Corp | Semiconductor device |
US4795722A (en) * | 1987-02-05 | 1989-01-03 | Texas Instruments Incorporated | Method for planarization of a semiconductor device prior to metallization |
JPS63293930A (en) * | 1987-05-27 | 1988-11-30 | Hitachi Ltd | Electrode in semiconductor device |
-
1987
- 1987-05-15 JP JP62116727A patent/JPS63283040A/en active Granted
-
1988
- 1988-05-10 EP EP88107501A patent/EP0291014B1/en not_active Expired - Lifetime
- 1988-05-10 US US07/192,665 patent/US4984061A/en not_active Expired - Lifetime
- 1988-05-10 DE DE8888107501T patent/DE3880003T2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0100100A2 (en) * | 1982-07-27 | 1984-02-08 | Kabushiki Kaisha Toshiba | Semiconductor device with an improved bonding section |
Non-Patent Citations (1)
Title |
---|
IEDM INTERNATIONAL ELECTRON DEVICES MEETING, 7th-9th December 1981, pages 62-65, IEEE, Washington, D.C., US; K. MUKAI et al.: "A new integration technology that enables forming bonding pads on active areas", "Film strength" * |
Also Published As
Publication number | Publication date |
---|---|
JPS63283040A (en) | 1988-11-18 |
JPH0546973B2 (en) | 1993-07-15 |
US4984061A (en) | 1991-01-08 |
DE3880003D1 (en) | 1993-05-13 |
DE3880003T2 (en) | 1993-09-16 |
EP0291014B1 (en) | 1993-04-07 |
EP0291014A2 (en) | 1988-11-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0291014A3 (en) | Semiconductor device in which wiring layer is formed below bonding pad | |
GB2201546B (en) | Semiconductor integrated circuit device | |
EP0303193A3 (en) | Semiconductor integrated circuit device | |
EP0301565A3 (en) | Semiconductor device comprising a wiring layer | |
EP0250269A3 (en) | Integrated circuit semiconductor device having improved wiring structure | |
EP0173980A3 (en) | Semiconductor integrated circuit device | |
GB8507524D0 (en) | Semiconductor integrated circuit device | |
EP0409173A3 (en) | Semiconductor ic device having an improved interconnection structure | |
EP0295708A3 (en) | Semiconductor device having a superconductive wiring | |
EP0180776A3 (en) | Chip-on-chip semiconductor device | |
GB8720041D0 (en) | Semiconductor integrated circuit device | |
EP0295707A3 (en) | Semiconductor integrated circuit device having multilayer power supply lines | |
EP0243024A3 (en) | Metallized semiconductor device including an interface layer | |
HK89595A (en) | Methods of manufacture of a resin-sealed semiconductor device | |
EP0299775A3 (en) | Tab bonded semiconductor chip package | |
EP0273725A3 (en) | Encapsulated semiconductor device | |
DE3370240D1 (en) | Bonding leads to semiconductor devices | |
GB8506105D0 (en) | Semiconductor integrated circuit device | |
EP0311088A3 (en) | Semiconductor integrated circuit device having power down mode | |
EP0186411A3 (en) | Semiconductor device in which a semiconductor chip is fixed to a base | |
EP0304930A3 (en) | Semiconductor integrated circuit device having signal lines | |
IL85892A0 (en) | Bonding of integrated circuit chips | |
HK176295A (en) | Semiconductor integrated circuit device | |
EP0281739A3 (en) | Semiconductor device comprising a thyristor | |
EP0283915A3 (en) | Semiconductor circuit device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 19880510 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE FR GB |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
RHK1 | Main classification (correction) |
Ipc: H01L 23/48 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): DE FR GB |
|
17Q | First examination report despatched |
Effective date: 19910304 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE FR GB |
|
REF | Corresponds to: |
Ref document number: 3880003 Country of ref document: DE Date of ref document: 19930513 |
|
ET | Fr: translation filed | ||
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed | ||
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 19970501 Year of fee payment: 10 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 19970516 Year of fee payment: 10 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 19980510 |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 19980510 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 19990302 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: D6 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20060515 Year of fee payment: 19 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST Effective date: 20080131 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20070531 |