JPS6079746A - Semiconductor device and modification of function thereof - Google Patents
Semiconductor device and modification of function thereofInfo
- Publication number
- JPS6079746A JPS6079746A JP18671683A JP18671683A JPS6079746A JP S6079746 A JPS6079746 A JP S6079746A JP 18671683 A JP18671683 A JP 18671683A JP 18671683 A JP18671683 A JP 18671683A JP S6079746 A JPS6079746 A JP S6079746A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- semiconductor device
- layers
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔゛技術分野〕
本発明は配線のパターンの変更により機能変更を容易に
行ない得る半導体装置及び機能変更方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device and a method for changing functions, in which functions can be easily changed by changing wiring patterns.
一般に10.LSI等の半導体装置の製造に際してはホ
) 13ソグラフイ技術が利用され、半導体ウェーハ主
面に形成する素子や配線はホトマスクのパターンに沿つ
℃形成される。Generally 10. When manufacturing semiconductor devices such as LSIs, e) 13 lithography technology is used, and elements and interconnections to be formed on the main surface of a semiconductor wafer are formed at temperatures along the pattern of a photomask.
ところで、近年の半導体装置では少量多品種化が進み、
同一素子パターンの半導体装置の配線ノ・ターンを変え
るととKより装置の機能を変更する試みがなされている
。このため、各品種に応じて最適なホトマスクを用意し
ておぎ、要求に応じ℃必要な配線パターンを得るマスタ
ースライス方式の半導体装置が提案されるに到っている
。By the way, in recent years semiconductor devices have become more diverse in small quantities,
Attempts have been made to change the function of a semiconductor device by changing the wiring no. and turns of a semiconductor device having the same element pattern. For this reason, a master slicing type semiconductor device has been proposed in which an optimal photomask is prepared for each type of semiconductor device, and the required wiring pattern can be obtained according to the demand.
しかしながら、本発明者の検討によればこの方式では一
旦配線まで形成された半導体装置の回路の一部を変更し
又その機能を変えたい要求の場合にはこれに対応するこ
とは困難である。これを強いて行なうには配線の形成を
再度やり直さなければならず、このための手数、特にホ
トマスクの作り直し、同一工程の反復等の作業に多大な
時間を必要とし、設計変更時間の増大、効率の低下の原
因となる。However, according to the studies of the present inventors, it is difficult with this method to respond to requests for changing a part of the circuit of a semiconductor device, which has been formed up to the wiring, or changing its function. To force this, the wiring must be formed again, which requires a lot of time and effort, especially remaking photomasks and repeating the same process, which increases design change time and reduces efficiency. This causes a decrease in the temperature.
本発明の目的は配線層まで形成した半導体装置の機能を
部分的圧しかも容易に変更することができる半導体装置
を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which the functions of a semiconductor device including wiring layers can be changed easily and locally.
また本発明の他の目的は配線層まで形成された半導体装
置の機能を容易に変更することのできる機能変更方法を
提供することにある。Another object of the present invention is to provide a function changing method that can easily change the function of a semiconductor device formed up to the wiring layer.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明ずれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
′すなわち、半導体装置の素子に接続される信号線の少
なくとも一部を複数の導体層の最上層として構成するこ
とにより、この最上層部位において配線を切断し又は接
続でき、これにより装置の機能変更を容易に行ない得る
ようにしたものである。'In other words, by configuring at least part of the signal lines connected to the elements of the semiconductor device as the top layer of multiple conductor layers, the wiring can be cut or connected at this top layer, thereby changing the function of the device. It is designed so that it can be carried out easily.
また、本発明は最上層部の配線なレーザにより切断しお
よび他の部位で部分配線をパターン形成して接続を行な
うことにより、機能変更方法易にかつ高信頼性に行ない
得るものである。Further, in the present invention, the function can be changed easily and with high reliability by cutting the wiring in the uppermost layer with a laser and forming a pattern of partial wiring in other parts to make connections.
第1図ないし第4図は本発明の一実施例を示し、第1図
および第2図は第3図囚の論理回路の一部を示し℃いる
。即ち、第3図(5)のように論理回路は2個のNAN
Dゲート1,2を有し、これに夫々入力信号線3,4.
5と6.7.8を接続し、またゲート1の出力信号線9
を前記入力信号線6に接続している。A、 B、 0は
入力端である。そし壬、前記入力信号W43と7は、第
1図及び第2図に示すように、夫々最下層の導体層io
、ii、中層の導体層12.13にコンタクトホールを
通して接続した上で、一方の導体層3はブリッジ状に形
成した最上層の導体層14.14’によって他の中層の
導体層15(入力端AVc接続している)に接続してい
る。換言すれば信号線3,7はその一部を最−F層の導
体層として構成していることになる。図中、16.17
は半導体基板18の主面に形成したMISFET等の半
導体素子の一部例えばそのソース、ドレイン領域として
の半導体領域、19はSin、膜、20.21はPSG
等からなる層間絶縁膜である。なお、第1図はA/配線
24の形成される前の第2図のA−A切断線に沿う断面
である。1 to 4 show one embodiment of the present invention, and FIGS. 1 and 2 show part of the logic circuit of FIG. 3. In other words, as shown in Figure 3 (5), the logic circuit consists of two NAN
It has D gates 1 and 2, and input signal lines 3, 4 .
5 and 6.7.8, and also the output signal line 9 of gate 1.
is connected to the input signal line 6. A, B, 0 are input terminals. As shown in FIGS. 1 and 2, the input signals W43 and W7 are input to the bottom conductor layer io, respectively.
, ii. After connecting to the middle conductor layer 12.13 through the contact hole, one conductor layer 3 is connected to the other middle conductor layer 15 (input terminal) by the top conductor layer 14.14' formed in a bridge shape. AVc connection). In other words, part of the signal lines 3 and 7 is configured as the F-most conductive layer. In the figure, 16.17
19 is a semiconductor region as a source and drain region of a semiconductor element such as a MISFET formed on the main surface of the semiconductor substrate 18, 19 is a Si film, and 20.21 is a PSG.
It is an interlayer insulating film consisting of etc. Note that FIG. 1 is a cross section taken along the line AA in FIG. 2 before the A/wiring 24 is formed.
以上の構成の半導体装置を例えば第3図(Blの回路構
成としてその機能を変更する場合には、同図のように入
力信号線3をゲート1との接続から切断する一方で、ゲ
ート1には新たに入力端Aに接続さ1する入力信号82
2を接続することが行なわれる。この変更方法を第2図
のA−A切断線に沿う断面に対応する断面を工程毎に示
す第4図(4)〜葭により説明する。When changing the function of the semiconductor device having the above configuration, for example, as shown in FIG. is the input signal 82 newly connected to input terminal A.
2 is connected. This modification method will be explained with reference to FIGS. 4(4) to 4(a), which show cross sections corresponding to the cross section along the line A--A in FIG. 2 for each process.
先ず、同図囚のように入力信号線3の最上層導体層14
にレーザビームX、タスポット的に照射する。これによ
り、レーザエネルギによって最上層導体層14′は焼損
され入力信号線3は選択的に切断され、導体層3と14
は非導通状態とされる。First, as shown in the figure, the top conductor layer 14 of the input signal line 3 is
Laser beam As a result, the uppermost conductor layer 14' is burnt out by the laser energy, the input signal line 3 is selectively cut, and the conductor layers 3 and 14' are selectively cut.
is in a non-conducting state.
次いで、同図(■のように全面にホトレジスト膜23を
形成した上で新たに導体層を形成した部位、本例では導
体層14と7の間に紫外線又は電子線X、を当射させ、
その部分のホトレジスト膜23aを選択的に感光除去し
てバターニングを完成させる。その上で、導体層材料と
してのA/層24を同図(Qのように全面に蒸着形成す
る。Next, as shown in the figure (■), a photoresist film 23 is formed on the entire surface, and then ultraviolet rays or electron beams
The photoresist film 23a in that area is selectively removed by exposure to light to complete the patterning. Thereafter, an A/layer 24 as a conductor layer material is formed by vapor deposition over the entire surface as shown in the figure (see Q).
そして、残存ホトレジスト膜23を除去すれば所謂リフ
トオフ法によりホトレジスト膜23上の導体層も一体的
に除去され、同図(口のように残存された導体層24に
よりて導体層14と7が接続され新たな配線お・よび回
路が構成されることになる。本例ではゲート2と入力端
Aとが入力信号線22、つまりA1層24によって接続
される。なお、通常では変更後にPSG膜等のファイナ
ルパツシベーション膜を形成するが図示は省略する。Then, when the remaining photoresist film 23 is removed, the conductor layer on the photoresist film 23 is also removed integrally by a so-called lift-off method, and the conductor layers 14 and 7 are connected by the remaining conductor layer 24 like the hole shown in the figure. Then, new wiring and circuits are constructed. In this example, the gate 2 and the input terminal A are connected by the input signal line 22, that is, the A1 layer 24. Note that normally, after the change, the PSG film etc. A final passivation film is formed, but illustration thereof is omitted.
したがって、この変更方法によれば、レーザビームによ
り導体層を切断しかつホトレジスト膜のバターニングを
行なうので、異なるパターンのホトマスクビ作成する必
要もな(、配線の部分的な変更を極めて容易に行なうこ
とができる。Therefore, according to this modification method, the conductor layer is cut with a laser beam and the photoresist film is patterned, so there is no need to create a photomask pattern with a different pattern (partial modification of wiring can be done extremely easily). Can be done.
+11 複数の導体配線層を形成してなる半導体装置の
信号線の少なくとも一部を導体配線層の最上層として構
成し℃いるので、装置の機能変更に際しては最上層配線
の一部を切断或いは新設にょっ°(変更するだけでよく
、容易にとt′Lを行なうことができる。+11 At least some of the signal lines of a semiconductor device formed with multiple conductor wiring layers are configured as the top layer of the conductor wiring layers. Therefore, when changing the function of the device, it is necessary to cut a part of the top layer wiring or create a new one. (You only need to change it, and you can easily perform t'L.)
(2)最り層の導体層の配線変更に際し、レーザを利用
して導体層の切断を行なう一方、レーザを利用してホト
レジスト膜および新設配線のバターニングを行なうので
、配線変更に際してホトマスクの作り直しは不要であり
、装置の機能変更を極めて容易に行なうことができる。(2) When changing the wiring in the last conductive layer, a laser is used to cut the conductive layer, and a laser is also used to pattern the photoresist film and new wiring, so the photomask is remade when changing the wiring. is not necessary, and the functions of the device can be changed extremely easily.
(3) ホトマスクを必要としないで装置の部分的な機
能変更ができるので、少品種の半導体装置、特にカスタ
ムIO,LSIの製造に有効である。(3) Since the function of a device can be partially changed without the need for a photomask, it is effective in manufacturing a small number of semiconductor devices, especially custom IOs and LSIs.
(4)部分的なレーザ当射およびリフトオフ法により配
線変更ができるので、変更時間の短縮と迅速な設計変更
が可能になる。(4) Since wiring can be changed by partial laser irradiation and lift-off methods, change time can be shortened and design changes can be made quickly.
以上本発明者によってなされた発明な実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。たとえば、配線層は3
層の多層構造である必要はなく1層のみのものでもよい
。配#!ヲ新設するためのリフトオフ法に代えてマスク
蒸着法やレーザを用いた直接バターニング法を利用して
もよい。Although the invention has been specifically explained above based on the embodiments of the invention made by the present inventor, it goes without saying that the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Nor. For example, the wiring layer is 3
It is not necessary to have a multilayer structure, and it may be only one layer. Delivery #! Instead of the lift-off method for new installation, a mask vapor deposition method or a direct patterning method using a laser may be used.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるロジックICの機能
変更に適用した場合につ(・℃説明したが、それに限定
されるものではなく、アナ、ログ10等穏々の半導体装
置に適用できる。また回路機能の変更方法としてのみな
らず、種々の10において誤った配線パターンの修正方
法とじ又使用することができる。The above explanation has mainly focused on the case where the invention made by the present inventor is applied to the functional change of logic ICs, which is the field of application that formed the background of the invention. The present invention can be applied to semiconductor devices of moderate quality, such as log 10. Furthermore, it can be used not only as a method for changing circuit functions, but also as a method for correcting incorrect wiring patterns in various types of 10.
さらに、本発明は半導体装置に限らず、セラミックやガ
ラスエポキシ等の絶縁性配線基板、又はシリコンよりな
る配線基板上に形成された配線にも、その機能変更ある
いは配線パターンを修正する方法として適用することが
可能である。Furthermore, the present invention is applicable not only to semiconductor devices, but also to wiring formed on insulating wiring substrates such as ceramic or glass epoxy, or wiring substrates made of silicon, as a method for changing the function or modifying the wiring pattern. Is possible.
第1図は本発明の−゛実施例の断面図、第2図は平面図
、
第3図へ)、[F])は夫々機能変更前、後の回路図、
第4図四〜県は本発明方法を工程順に示す断面図である
。Fig. 1 is a sectional view of the embodiment of the present invention, Fig. 2 is a plan view, Fig. 3) and [F]) are circuit diagrams before and after the functional change, respectively.
FIG. 4 is a sectional view showing the method of the present invention in the order of steps.
Claims (1)
、その上面に複数の導体配線層を形成してなる半導体装
置において、前記回路素子に接続される信号線の少な(
とも一部を前記導体配線層の最上層として構成したこと
t特徴とする半導体装置。 2、最上層に形成した配線部位は中、下層の配線をブリ
ッジ状に接続した構成とじ℃なる特許請求の範囲第1項
記載の半導体装置。 3、半導体ウェーハの最上層に形成された回路素子の信
号線の一部を選択的に切断する一方、他部には導体層を
新たにパターン形成して他部間での接続を行ない、配線
パターンの変更を行なうことを特徴とする半導体装置の
機能変更方法。 4、新たに形成する配線は、ホトレジストv選択感光し
バターニングした後、導体層を全面形成し、しかる上で
ホトレジストを除去するリフトオフ法により形成し1な
る特許請求の範囲第3項記載の半導体装置の機能変更方
法。[Claims] 1. In a semiconductor device in which circuit elements are formed on the main surface of a semiconductor wafer and a plurality of conductor wiring layers are formed on the upper surface thereof, the number of signal lines connected to the circuit elements (
A semiconductor device characterized in that a portion of each of the conductor wiring layers is formed as the uppermost layer of the conductive wiring layer. 2. The semiconductor device according to claim 1, wherein the wiring portion formed in the uppermost layer has a structure in which middle and lower layer wirings are connected in a bridge shape. 3. Selectively cut some of the signal lines of the circuit elements formed on the top layer of the semiconductor wafer, while forming new patterns of conductor layers on other parts to make connections between other parts, and create wiring. A method for changing the function of a semiconductor device, the method comprising changing a pattern. 4. The newly formed wiring is formed by a lift-off method in which a photoresist is selectively exposed and patterned, a conductive layer is formed on the entire surface, and then the photoresist is removed. How to change the functionality of the device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18671683A JPS6079746A (en) | 1983-10-07 | 1983-10-07 | Semiconductor device and modification of function thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18671683A JPS6079746A (en) | 1983-10-07 | 1983-10-07 | Semiconductor device and modification of function thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6079746A true JPS6079746A (en) | 1985-05-07 |
Family
ID=16193384
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18671683A Pending JPS6079746A (en) | 1983-10-07 | 1983-10-07 | Semiconductor device and modification of function thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6079746A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4931845A (en) * | 1987-11-05 | 1990-06-05 | Fujitsu Limited | Semiconductor memory device having an ohmic contact between an aluminum-silicon alloy metallization film and a silicon substrate |
US4984061A (en) * | 1987-05-15 | 1991-01-08 | Kabushiki Kaisha Toshiba | Semiconductor device in which wiring layer is formed below bonding pad |
-
1983
- 1983-10-07 JP JP18671683A patent/JPS6079746A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4984061A (en) * | 1987-05-15 | 1991-01-08 | Kabushiki Kaisha Toshiba | Semiconductor device in which wiring layer is formed below bonding pad |
US4931845A (en) * | 1987-11-05 | 1990-06-05 | Fujitsu Limited | Semiconductor memory device having an ohmic contact between an aluminum-silicon alloy metallization film and a silicon substrate |
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