DE3853392T2 - Verbindungsstruktur eines Halbleiterbauelementes und Verfahren zu ihrer Herstellung. - Google Patents

Verbindungsstruktur eines Halbleiterbauelementes und Verfahren zu ihrer Herstellung.

Info

Publication number
DE3853392T2
DE3853392T2 DE3853392T DE3853392T DE3853392T2 DE 3853392 T2 DE3853392 T2 DE 3853392T2 DE 3853392 T DE3853392 T DE 3853392T DE 3853392 T DE3853392 T DE 3853392T DE 3853392 T2 DE3853392 T2 DE 3853392T2
Authority
DE
Germany
Prior art keywords
production
connection structure
semiconductor component
semiconductor
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3853392T
Other languages
English (en)
Other versions
DE3853392D1 (de
Inventor
Katsuya Okumura
Toshinori Shinki
Toshiaki Toshiba Isogo D Idaka
Riichirou Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3853392D1 publication Critical patent/DE3853392D1/de
Publication of DE3853392T2 publication Critical patent/DE3853392T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/228—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/915—Active solid-state devices, e.g. transistors, solid-state diodes with titanium nitride portion or region
DE3853392T 1987-10-02 1988-09-30 Verbindungsstruktur eines Halbleiterbauelementes und Verfahren zu ihrer Herstellung. Expired - Fee Related DE3853392T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62249329A JPH0719841B2 (ja) 1987-10-02 1987-10-02 半導体装置

Publications (2)

Publication Number Publication Date
DE3853392D1 DE3853392D1 (de) 1995-04-27
DE3853392T2 true DE3853392T2 (de) 1995-09-07

Family

ID=17191388

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3853392T Expired - Fee Related DE3853392T2 (de) 1987-10-02 1988-09-30 Verbindungsstruktur eines Halbleiterbauelementes und Verfahren zu ihrer Herstellung.

Country Status (5)

Country Link
US (1) US4937652A (de)
EP (1) EP0310108B1 (de)
JP (1) JPH0719841B2 (de)
KR (1) KR920001174B1 (de)
DE (1) DE3853392T2 (de)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5273937A (en) * 1988-01-08 1993-12-28 Kabushiki Kaisha Toshiba Metal semiconductor device and method for producing the same
JPH0274039A (ja) * 1988-09-09 1990-03-14 Texas Instr Japan Ltd 電子回路装置
JPH038359A (ja) * 1989-06-06 1991-01-16 Fujitsu Ltd 半導体装置の製造方法
JPH03142934A (ja) * 1989-10-30 1991-06-18 Mitsubishi Electric Corp 半導体集積回路装置の配線接続構造
US5365110A (en) * 1989-11-07 1994-11-15 Kabushiki Kaisha Toshiba Semiconductor device with multi-layered wiring structure
KR930000309B1 (ko) * 1989-11-22 1993-01-15 삼성전자 주식회사 반도체 장치의 제조방법
EP0430403B1 (de) 1989-11-30 1998-01-07 STMicroelectronics, Inc. Verfahren zum Herstellen von Zwischenschicht-Kontakten
US5472912A (en) * 1989-11-30 1995-12-05 Sgs-Thomson Microelectronics, Inc. Method of making an integrated circuit structure by using a non-conductive plug
US5108951A (en) * 1990-11-05 1992-04-28 Sgs-Thomson Microelectronics, Inc. Method for forming a metal contact
US6271137B1 (en) 1989-11-30 2001-08-07 Stmicroelectronics, Inc. Method of producing an aluminum stacked contact/via for multilayer
US5658828A (en) * 1989-11-30 1997-08-19 Sgs-Thomson Microelectronics, Inc. Method for forming an aluminum contact through an insulating layer
US6242811B1 (en) 1989-11-30 2001-06-05 Stmicroelectronics, Inc. Interlevel contact including aluminum-refractory metal alloy formed during aluminum deposition at an elevated temperature
US5367179A (en) * 1990-04-25 1994-11-22 Casio Computer Co., Ltd. Thin-film transistor having electrodes made of aluminum, and an active matrix panel using same
JPH088301B2 (ja) * 1990-06-07 1996-01-29 株式会社東芝 半導体装置の製造方法
JP2563652B2 (ja) * 1990-07-17 1996-12-11 株式会社東芝 半導体装置及びその製造方法
JP2598335B2 (ja) * 1990-08-28 1997-04-09 三菱電機株式会社 半導体集積回路装置の配線接続構造およびその製造方法
KR960001601B1 (ko) * 1992-01-23 1996-02-02 삼성전자주식회사 반도체 장치의 접촉구 매몰방법 및 구조
DE69102851T2 (de) * 1990-10-09 1995-02-16 Nec Corp Verfahren zur Herstellung eines Ti/TiN/Al Kontaktes unter Benutzung eines reaktiven Zerstäubungsprozesses.
US6287963B1 (en) 1990-11-05 2001-09-11 Stmicroelectronics, Inc. Method for forming a metal contact
KR920010759A (ko) * 1990-11-16 1992-06-27 원본미기재 저 저항 접점을 제조하는 방법
JP2660359B2 (ja) * 1991-01-30 1997-10-08 三菱電機株式会社 半導体装置
JP3099406B2 (ja) * 1991-04-05 2000-10-16 ヤマハ株式会社 集積回路の多層配線構造
JPH0575061A (ja) * 1991-09-13 1993-03-26 Oki Electric Ind Co Ltd 半導体記憶装置の配線構造
US5200359A (en) * 1991-10-03 1993-04-06 Micron Technology, Inc. Method of decreasing contact resistance between a lower elevation aluminum layer and a higher elevation electrically conductive layer
JPH05206134A (ja) * 1991-11-12 1993-08-13 Nec Corp 半導体装置とその製造方法
JPH05275540A (ja) * 1992-03-28 1993-10-22 Yamaha Corp 集積回路装置
JP2885616B2 (ja) * 1992-07-31 1999-04-26 株式会社東芝 半導体装置およびその製造方法
GB9219267D0 (en) * 1992-09-11 1992-10-28 Inmos Ltd Manufacture of semiconductor devices
GB9219281D0 (en) * 1992-09-11 1992-10-28 Inmos Ltd Manufacture of semiconductor devices
EP0594300B1 (de) * 1992-09-22 1998-07-29 STMicroelectronics, Inc. Methode zur Herstellung eines Metallkontaktes
US5365111A (en) * 1992-12-23 1994-11-15 Advanced Micro Devices, Inc. Stable local interconnect/active area silicide structure for VLSI applications
US6690044B1 (en) * 1993-03-19 2004-02-10 Micron Technology, Inc. Approach to avoid buckling BPSG by using an intermediate barrier layer
JP3401843B2 (ja) * 1993-06-21 2003-04-28 ソニー株式会社 半導体装置における多層配線の形成方法
JP3599199B2 (ja) * 1994-08-31 2004-12-08 富士通株式会社 多層配線を有する半導体装置の製造方法
US5686761A (en) * 1995-06-06 1997-11-11 Advanced Micro Devices, Inc. Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology
US5899724A (en) * 1996-05-09 1999-05-04 International Business Machines Corporation Method for fabricating a titanium resistor
US5913146A (en) * 1997-03-18 1999-06-15 Lucent Technologies Inc. Semiconductor device having aluminum contacts or vias and method of manufacture therefor
US6274486B1 (en) * 1998-09-02 2001-08-14 Micron Technology, Inc. Metal contact and process
JP3277909B2 (ja) * 1999-02-08 2002-04-22 日本電気株式会社 半導体装置及びその製造方法
JP2002223014A (ja) * 2001-01-26 2002-08-09 Denso Corp 磁気検出装置
US6815818B2 (en) * 2001-11-19 2004-11-09 Micron Technology, Inc. Electrode structure for use in an integrated circuit
KR100573897B1 (ko) * 2003-12-30 2006-04-26 동부일렉트로닉스 주식회사 반도체 제조 방법
JP6040904B2 (ja) * 2013-09-27 2016-12-07 豊田合成株式会社 半導体装置およびその製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53121490A (en) * 1977-03-31 1978-10-23 Toshiba Corp Semiconductor device
EP0042926A1 (de) * 1980-07-01 1982-01-06 Rockwell International Corporation Aluminium-Aluminium-Ohmsche-Kontakte, Mehrlagen-Zwischenverbindungen
JPS57208161A (en) * 1981-06-18 1982-12-21 Fujitsu Ltd Semiconductor device
GB2135123B (en) * 1983-02-10 1987-05-20 Rca Corp Multi-level metallization structure for semiconductor device and method of making same
JPS59198734A (ja) * 1983-04-25 1984-11-10 Mitsubishi Electric Corp 多層配線構造
JPS605560A (ja) * 1983-06-23 1985-01-12 Fujitsu Ltd 半導体装置
US4507852A (en) * 1983-09-12 1985-04-02 Rockwell International Corporation Method for making a reliable ohmic contact between two layers of integrated circuit metallizations
US4845543A (en) * 1983-09-28 1989-07-04 Hitachi, Ltd. Semiconductor device and method of manufacturing the same
US4742023A (en) * 1986-08-28 1988-05-03 Fujitsu Limited Method for producing a semiconductor device

Also Published As

Publication number Publication date
JPH0191438A (ja) 1989-04-11
EP0310108B1 (de) 1995-03-22
EP0310108A2 (de) 1989-04-05
EP0310108A3 (de) 1991-02-06
DE3853392D1 (de) 1995-04-27
US4937652A (en) 1990-06-26
KR890007386A (ko) 1989-06-19
KR920001174B1 (ko) 1992-02-06
JPH0719841B2 (ja) 1995-03-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee