DE3787874D1 - Verfahren zur Herstellung eines Bauelementes mit einer tiefen Schicht aus Si02. - Google Patents

Verfahren zur Herstellung eines Bauelementes mit einer tiefen Schicht aus Si02.

Info

Publication number
DE3787874D1
DE3787874D1 DE87310125T DE3787874T DE3787874D1 DE 3787874 D1 DE3787874 D1 DE 3787874D1 DE 87310125 T DE87310125 T DE 87310125T DE 3787874 T DE3787874 T DE 3787874T DE 3787874 D1 DE3787874 D1 DE 3787874D1
Authority
DE
Germany
Prior art keywords
producing
component
deep layer
deep
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE87310125T
Other languages
English (en)
Other versions
DE3787874T2 (de
Inventor
Kenneth Thomas Short
Alice Elizabeth White
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Application granted granted Critical
Publication of DE3787874D1 publication Critical patent/DE3787874D1/de
Publication of DE3787874T2 publication Critical patent/DE3787874T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
DE87310125T 1986-11-26 1987-11-17 Verfahren zur Herstellung eines Bauelementes mit einer tiefen Schicht aus Si02. Expired - Fee Related DE3787874T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/935,273 US4749660A (en) 1986-11-26 1986-11-26 Method of making an article comprising a buried SiO2 layer
SG26594A SG26594G (en) 1986-11-26 1994-02-21 Method of making an article comprising a buried SIO2 layer

Publications (2)

Publication Number Publication Date
DE3787874D1 true DE3787874D1 (de) 1993-11-25
DE3787874T2 DE3787874T2 (de) 1994-02-10

Family

ID=26663905

Family Applications (1)

Application Number Title Priority Date Filing Date
DE87310125T Expired - Fee Related DE3787874T2 (de) 1986-11-26 1987-11-17 Verfahren zur Herstellung eines Bauelementes mit einer tiefen Schicht aus Si02.

Country Status (6)

Country Link
US (1) US4749660A (de)
EP (1) EP0269349B1 (de)
JP (1) JPH0727965B2 (de)
DE (1) DE3787874T2 (de)
HK (1) HK104994A (de)
SG (1) SG26594G (de)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920002350B1 (ko) * 1987-05-21 1992-03-21 마쯔시다덴기산교 가부시기가이샤 반도체장치의 제조방법
JPS6432622A (en) * 1987-07-28 1989-02-02 Mitsubishi Electric Corp Formation of soi film
US5066610A (en) * 1987-11-20 1991-11-19 Massachusetts Institute Of Technology Capping technique for zone-melting recrystallization of insulated semiconductor films
US5136344A (en) * 1988-11-02 1992-08-04 Universal Energy Systems, Inc. High energy ion implanted silicon on insulator structure
JP2858434B2 (ja) * 1989-03-31 1999-02-17 キヤノン株式会社 結晶の形成方法および結晶物品
US5196355A (en) * 1989-04-24 1993-03-23 Ibis Technology Corporation Simox materials through energy variation
US4976987A (en) * 1989-08-10 1990-12-11 The United States Of America As Represented By The Department Of Energy Process for forming one or more substantially pure layers in substrate material using ion implantation
US5124174A (en) * 1989-08-10 1992-06-23 The United States Of America As Represented By The United States Department Of Energy Process for forming one or more substantially pure layers in substrate material using ion implantation
JPH0377329A (ja) * 1989-08-19 1991-04-02 Fujitsu Ltd 半導体装置の製造方法
US5053627A (en) * 1990-03-01 1991-10-01 Ibis Technology Corporation Apparatus for ion implantation
JP3096050B2 (ja) * 1990-08-09 2000-10-10 富士通株式会社 半導体装置の製造方法
US5137837A (en) * 1990-08-20 1992-08-11 Hughes Aircraft Company Radiation-hard, high-voltage semiconductive device structure fabricated on SOI substrate
US5288650A (en) * 1991-01-25 1994-02-22 Ibis Technology Corporation Prenucleation process for simox device fabrication
JP3291510B2 (ja) * 1992-03-31 2002-06-10 シャープ株式会社 半導体装置
IT1255764B (it) * 1992-05-15 1995-11-15 Enichem Struttura soi con ossido sottile e profondo ottenuta per impiantazioneionica ad alta energia e successivi trattamenti termici.
US5429955A (en) * 1992-10-26 1995-07-04 Texas Instruments Incorporated Method for constructing semiconductor-on-insulator
JP3036619B2 (ja) * 1994-03-23 2000-04-24 コマツ電子金属株式会社 Ｓｏｉ基板の製造方法およびｓｏｉ基板
JP3427114B2 (ja) * 1994-06-03 2003-07-14 コマツ電子金属株式会社 半導体デバイス製造方法
JP3204855B2 (ja) * 1994-09-30 2001-09-04 新日本製鐵株式会社 半導体基板の製造方法
US5788763A (en) * 1995-03-09 1998-08-04 Toshiba Ceramics Co., Ltd. Manufacturing method of a silicon wafer having a controlled BMD concentration
US5856235A (en) * 1995-04-12 1999-01-05 Northrop Grumman Corporation Process of vacuum annealing a thin film metallization on high purity alumina
US5795813A (en) * 1996-05-31 1998-08-18 The United States Of America As Represented By The Secretary Of The Navy Radiation-hardening of SOI by ion implantation into the buried oxide layer
US6043166A (en) * 1996-12-03 2000-03-28 International Business Machines Corporation Silicon-on-insulator substrates using low dose implantation
JPH10223551A (ja) * 1997-02-12 1998-08-21 Nec Corp Ｓｏｉ基板の製造方法
EP0889505B1 (de) * 1997-07-03 2005-06-08 STMicroelectronics S.r.l. Verfahren zur Herstellung von Geräten in einem halbleitenden Substrat
US6486037B2 (en) 1997-12-22 2002-11-26 International Business Machines Corporation Control of buried oxide quality in low dose SIMOX
US5930643A (en) 1997-12-22 1999-07-27 International Business Machines Corporation Defect induced buried oxide (DIBOX) for throughput SOI
US6258693B1 (en) * 1997-12-23 2001-07-10 Integrated Device Technology, Inc. Ion implantation for scalability of isolation in an integrated circuit
US5939750A (en) * 1998-01-21 1999-08-17 Advanced Micro Devices Use of implanted ions to reduce oxide-nitride-oxide (ONO) etch residue and polystringers
KR100292818B1 (ko) * 1998-07-02 2001-11-05 윤종용 모오스트랜지스터제조방법
US6417078B1 (en) 2000-05-03 2002-07-09 Ibis Technology Corporation Implantation process using sub-stoichiometric, oxygen doses at different energies
US6541356B2 (en) 2001-05-21 2003-04-01 International Business Machines Corporation Ultimate SIMOX
US6855436B2 (en) * 2003-05-30 2005-02-15 International Business Machines Corporation Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal
US6846727B2 (en) 2001-05-21 2005-01-25 International Business Machines Corporation Patterned SOI by oxygen implantation and annealing
US6602757B2 (en) * 2001-05-21 2003-08-05 International Business Machines Corporation Self-adjusting thickness uniformity in SOI by high-temperature oxidation of SIMOX and bonded SOI
US20020190318A1 (en) 2001-06-19 2002-12-19 International Business Machines Corporation Divot reduction in SIMOX layers
US6495429B1 (en) * 2002-01-23 2002-12-17 International Business Machines Corporation Controlling internal thermal oxidation and eliminating deep divots in SIMOX by chlorine-based annealing
US7608927B2 (en) * 2002-08-29 2009-10-27 Micron Technology, Inc. Localized biasing for silicon on insulator structures
US20050170570A1 (en) * 2004-01-30 2005-08-04 International Business Machines Corporation High electrical quality buried oxide in simox
US7705427B2 (en) * 2005-11-16 2010-04-27 Stmicroelectronics Sa Integrated circuit comprising a gradually doped bipolar transistor
FR2978603B1 (fr) * 2011-07-28 2013-08-23 Soitec Silicon On Insulator Procede de transfert d'une couche semi-conductrice monocristalline sur un substrat support
DE102017212437B3 (de) 2017-07-20 2018-12-20 Infineon Technologies Ag Verfahren zum Herstellen einer vergrabenen Hohlraumstruktur

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5331971A (en) * 1976-09-06 1978-03-25 Nippon Telegr & Teleph Corp <Ntt> Forming method of metal oxide film or semiconductor oxide film
JPS55146936A (en) * 1979-05-04 1980-11-15 Chiyou Lsi Gijutsu Kenkyu Kumiai Treatment of semiconductor film
JPS55148464A (en) * 1979-05-08 1980-11-19 Chiyou Lsi Gijutsu Kenkyu Kumiai Mos semiconductor device and its manufacture
JPS5680126A (en) * 1979-12-05 1981-07-01 Chiyou Lsi Gijutsu Kenkyu Kumiai Formation of monocrystalline semiconductor
US4385937A (en) * 1980-05-20 1983-05-31 Tokyo Shibaura Denki Kabushiki Kaisha Regrowing selectively formed ion amorphosized regions by thermal gradient
US4412868A (en) * 1981-12-23 1983-11-01 General Electric Company Method of making integrated circuits utilizing ion implantation and selective epitaxial growth
JPS60213019A (ja) * 1984-04-09 1985-10-25 Nec Corp 半導体装置の製造方法
FR2563377B1 (fr) * 1984-04-19 1987-01-23 Commissariat Energie Atomique Procede de fabrication d'une couche isolante enterree dans un substrat semi-conducteur, par implantation ionique
US4588447A (en) * 1984-06-25 1986-05-13 Rockwell International Corporation Method of eliminating p-type electrical activity and increasing channel mobility of Si-implanted and recrystallized SOS films
FR2581795B1 (fr) * 1985-05-10 1988-06-17 Golanski Andrzej Procede de fabrication d'une couche isolante continue enterree dans un substrat semi-conducteur, par implantation ionique
US4676841A (en) * 1985-09-27 1987-06-30 American Telephone And Telegraph Company, At&T Bell Laboratories Fabrication of dielectrically isolated devices utilizing buried oxygen implant and subsequent heat treatment at temperatures above 1300° C.
JPH077748B2 (ja) * 1986-07-01 1995-01-30 富士通株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
JPS63142655A (ja) 1988-06-15
US4749660A (en) 1988-06-07
DE3787874T2 (de) 1994-02-10
EP0269349B1 (de) 1993-10-20
EP0269349A2 (de) 1988-06-01
HK104994A (en) 1994-10-07
JPH0727965B2 (ja) 1995-03-29
SG26594G (en) 1995-03-17
EP0269349A3 (en) 1990-08-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: BLUMBACH, KRAMER & PARTNER, 65193 WIESBADEN

8339 Ceased/non-payment of the annual fee