FR2581795B1 - Procede de fabrication d'une couche isolante continue enterree dans un substrat semi-conducteur, par implantation ionique - Google Patents

Procede de fabrication d'une couche isolante continue enterree dans un substrat semi-conducteur, par implantation ionique

Info

Publication number
FR2581795B1
FR2581795B1 FR8507120A FR8507120A FR2581795B1 FR 2581795 B1 FR2581795 B1 FR 2581795B1 FR 8507120 A FR8507120 A FR 8507120A FR 8507120 A FR8507120 A FR 8507120A FR 2581795 B1 FR2581795 B1 FR 2581795B1
Authority
FR
France
Prior art keywords
manufacturing
insulating layer
semiconductor substrate
ion implantation
layer buried
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8507120A
Other languages
English (en)
Other versions
FR2581795A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to FR8507120A priority Critical patent/FR2581795B1/fr
Publication of FR2581795A1 publication Critical patent/FR2581795A1/fr
Application granted granted Critical
Publication of FR2581795B1 publication Critical patent/FR2581795B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
FR8507120A 1985-05-10 1985-05-10 Procede de fabrication d'une couche isolante continue enterree dans un substrat semi-conducteur, par implantation ionique Expired FR2581795B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8507120A FR2581795B1 (fr) 1985-05-10 1985-05-10 Procede de fabrication d'une couche isolante continue enterree dans un substrat semi-conducteur, par implantation ionique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8507120A FR2581795B1 (fr) 1985-05-10 1985-05-10 Procede de fabrication d'une couche isolante continue enterree dans un substrat semi-conducteur, par implantation ionique

Publications (2)

Publication Number Publication Date
FR2581795A1 FR2581795A1 (fr) 1986-11-14
FR2581795B1 true FR2581795B1 (fr) 1988-06-17

Family

ID=9319150

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8507120A Expired FR2581795B1 (fr) 1985-05-10 1985-05-10 Procede de fabrication d'une couche isolante continue enterree dans un substrat semi-conducteur, par implantation ionique

Country Status (1)

Country Link
FR (1) FR2581795B1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4749660A (en) * 1986-11-26 1988-06-07 American Telephone And Telegraph Company, At&T Bell Laboratories Method of making an article comprising a buried SiO2 layer
US5080730A (en) * 1989-04-24 1992-01-14 Ibis Technology Corporation Implantation profile control with surface sputtering
US5441899A (en) * 1992-02-18 1995-08-15 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing substrate having semiconductor on insulator
US5429955A (en) * 1992-10-26 1995-07-04 Texas Instruments Incorporated Method for constructing semiconductor-on-insulator
US5989981A (en) * 1996-07-05 1999-11-23 Nippon Telegraph And Telephone Corporation Method of manufacturing SOI substrate
JP2856157B2 (ja) * 1996-07-16 1999-02-10 日本電気株式会社 半導体装置の製造方法
US6417078B1 (en) 2000-05-03 2002-07-09 Ibis Technology Corporation Implantation process using sub-stoichiometric, oxygen doses at different energies

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5721856B2 (en) * 1977-11-28 1982-05-10 Nippon Telegraph & Telephone Semiconductor and its manufacture

Also Published As

Publication number Publication date
FR2581795A1 (fr) 1986-11-14

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ST Notification of lapse