FR2599892B1 - Procede d'aplanissement d'un substrat semiconducteur revetu d'une couche dielectrique - Google Patents
Procede d'aplanissement d'un substrat semiconducteur revetu d'une couche dielectriqueInfo
- Publication number
- FR2599892B1 FR2599892B1 FR8608362A FR8608362A FR2599892B1 FR 2599892 B1 FR2599892 B1 FR 2599892B1 FR 8608362 A FR8608362 A FR 8608362A FR 8608362 A FR8608362 A FR 8608362A FR 2599892 B1 FR2599892 B1 FR 2599892B1
- Authority
- FR
- France
- Prior art keywords
- surfacing
- dielectric layer
- semiconductor substrate
- substrate coated
- coated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/40—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8608362A FR2599892B1 (fr) | 1986-06-10 | 1986-06-10 | Procede d'aplanissement d'un substrat semiconducteur revetu d'une couche dielectrique |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8608362A FR2599892B1 (fr) | 1986-06-10 | 1986-06-10 | Procede d'aplanissement d'un substrat semiconducteur revetu d'une couche dielectrique |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2599892A1 FR2599892A1 (fr) | 1987-12-11 |
FR2599892B1 true FR2599892B1 (fr) | 1988-08-26 |
Family
ID=9336185
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR8608362A Expired FR2599892B1 (fr) | 1986-06-10 | 1986-06-10 | Procede d'aplanissement d'un substrat semiconducteur revetu d'une couche dielectrique |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR2599892B1 (fr) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL8701717A (nl) * | 1987-07-21 | 1989-02-16 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een geplanariseerde opbouw. |
FR2627902B1 (fr) * | 1988-02-26 | 1990-06-22 | Philips Nv | Procede pour aplanir la surface d'un dispositif semiconducteur |
US4836885A (en) * | 1988-05-03 | 1989-06-06 | International Business Machines Corporation | Planarization process for wide trench isolation |
DE69004932T2 (de) * | 1989-10-25 | 1994-05-19 | Ibm | Verfahren zur Herstellung breiter mit Dielektrikum gefüllter Isolationsgraben für Halbleiteranordnungen. |
US5173439A (en) * | 1989-10-25 | 1992-12-22 | International Business Machines Corporation | Forming wide dielectric-filled isolation trenches in semi-conductors |
US5419803A (en) * | 1993-11-17 | 1995-05-30 | Hughes Aircraft Company | Method of planarizing microstructures |
DE19538005A1 (de) | 1995-10-12 | 1997-04-17 | Fraunhofer Ges Forschung | Verfahren zum Erzeugen einer Grabenisolation in einem Substrat |
US6284560B1 (en) * | 1998-12-18 | 2001-09-04 | Eastman Kodak Company | Method for producing co-planar surface structures |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4457820A (en) * | 1981-12-24 | 1984-07-03 | International Business Machines Corporation | Two step plasma etching |
FR2529714A1 (fr) * | 1982-07-01 | 1984-01-06 | Commissariat Energie Atomique | Procede de realisation de l'oxyde de champ d'un circuit integre |
JPS618946A (ja) * | 1984-06-25 | 1986-01-16 | Toshiba Corp | 半導体装置の製造方法 |
-
1986
- 1986-06-10 FR FR8608362A patent/FR2599892B1/fr not_active Expired
Also Published As
Publication number | Publication date |
---|---|
FR2599892A1 (fr) | 1987-12-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
TP | Transmission of property | ||
ST | Notification of lapse |