FR2630617B1 - Procede de fabrication d'un substrat conducteur multicouche - Google Patents

Procede de fabrication d'un substrat conducteur multicouche

Info

Publication number
FR2630617B1
FR2630617B1 FR8905357A FR8905357A FR2630617B1 FR 2630617 B1 FR2630617 B1 FR 2630617B1 FR 8905357 A FR8905357 A FR 8905357A FR 8905357 A FR8905357 A FR 8905357A FR 2630617 B1 FR2630617 B1 FR 2630617B1
Authority
FR
France
Prior art keywords
manufacturing
conductive substrate
multilayer conductive
multilayer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR8905357A
Other languages
English (en)
Other versions
FR2630617A1 (fr
Inventor
Okada Yoshitsugu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of FR2630617A1 publication Critical patent/FR2630617A1/fr
Application granted granted Critical
Publication of FR2630617B1 publication Critical patent/FR2630617B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y10T29/49167—Manufacturing circuit on or in base by forming conductive walled aperture in base with deforming of conductive path

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
FR8905357A 1988-04-22 1989-04-21 Procede de fabrication d'un substrat conducteur multicouche Expired - Fee Related FR2630617B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63100833A JPH0682926B2 (ja) 1988-04-22 1988-04-22 多層配線基板の製造方法

Publications (2)

Publication Number Publication Date
FR2630617A1 FR2630617A1 (fr) 1989-10-27
FR2630617B1 true FR2630617B1 (fr) 1993-10-08

Family

ID=14284318

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8905357A Expired - Fee Related FR2630617B1 (fr) 1988-04-22 1989-04-21 Procede de fabrication d'un substrat conducteur multicouche

Country Status (3)

Country Link
US (1) US4882839A (fr)
JP (1) JPH0682926B2 (fr)
FR (1) FR2630617B1 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2594646B2 (ja) * 1989-08-17 1997-03-26 シャープ株式会社 サーマルヘッドの製造方法
US5531020A (en) * 1989-11-14 1996-07-02 Poly Flex Circuits, Inc. Method of making subsurface electronic circuits
JPH0461293A (ja) * 1990-06-29 1992-02-27 Toshiba Corp 回路基板及びその製造方法
US5243143A (en) * 1990-11-13 1993-09-07 Compaq Computer Corporation Solder snap bar
CA2055148C (fr) * 1991-10-25 2002-06-18 Alain Langevin Methode utilisee pour obtenir un contact electrique sur un support
JPH05218644A (ja) * 1992-02-04 1993-08-27 Fujitsu Ltd 多層プリント配線板の製造方法
CA2137861A1 (fr) * 1994-02-21 1995-08-22 Walter Schmidt Procede de fabrication de structures
US5437999A (en) * 1994-02-22 1995-08-01 Boehringer Mannheim Corporation Electrochemical sensor
US5822856A (en) * 1996-06-28 1998-10-20 International Business Machines Corporation Manufacturing circuit board assemblies having filled vias
US6372999B1 (en) 1999-04-20 2002-04-16 Trw Inc. Multilayer wiring board and multilayer wiring package
JP2000357873A (ja) * 1999-06-17 2000-12-26 Hitachi Ltd 多層配線基板及びその製造方法
AT500259B1 (de) * 2003-09-09 2007-08-15 Austria Tech & System Tech Dünnschichtanordnung und verfahren zum herstellen einer solchen dünnschichtanordnung

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1191592B (de) * 1960-12-19 1965-04-22 Continental Elektro Ind Ag Verfahren zur Herstellung von Zeichen-, insbesondere Teilungs-Traegern
US3936531A (en) * 1973-05-01 1976-02-03 Union Carbide Corporation Masking process with thermal destruction of edges of mask
JPS5210568A (en) * 1974-12-28 1977-01-26 Hideo Machida Method of manufacturing multilayered printed wiring substrate
JPS5845810B2 (ja) * 1975-08-01 1983-10-12 日本電気株式会社 パタ−ンの形成方法
EP0003801B1 (fr) * 1978-02-17 1982-06-09 E.I. Du Pont De Nemours And Company Utilisation d'un support photosensible pour la réalisation de connexions de passage dans des panneaux à circuits imprimés
JPS561565A (en) * 1979-06-15 1981-01-09 Nec Corp Manufacture of hybrid integrated circuit
US4381327A (en) * 1980-10-06 1983-04-26 Dennison Manufacturing Company Mica-foil laminations
US4431685A (en) * 1982-07-02 1984-02-14 International Business Machines Corporation Decreasing plated metal defects
JPS60113993A (ja) * 1983-11-25 1985-06-20 三菱電機株式会社 多層回路基板の製造方法
US4526859A (en) * 1983-12-12 1985-07-02 International Business Machines Corporation Metallization of a ceramic substrate
US4693925A (en) * 1984-03-01 1987-09-15 Advanced Micro Devices, Inc. Integrated circuit structure having intermediate metal silicide layer
US4569876A (en) * 1984-08-08 1986-02-11 Nec Corporation Multi-layered substrate having a fine wiring structure for LSI or VLSI circuits
JPS61166075A (ja) * 1985-01-17 1986-07-26 Mitsubishi Electric Corp 半導体装置およびその製造方法
DE3689971T2 (de) * 1986-03-05 1994-12-08 Sumitomo Electric Industries Herstellung einer halbleiteranordnung.
US4801469A (en) * 1986-08-07 1989-01-31 The United States Of America As Represented By The Department Of Energy Process for obtaining multiple sheet resistances for thin film hybrid microcircuit resistors
DE3639604A1 (de) * 1986-11-20 1988-05-26 Bbc Brown Boveri & Cie Verfahren zur herstellung lotverstaerkter leiterbahnen
JPS63229897A (ja) * 1987-03-19 1988-09-26 古河電気工業株式会社 リジツド型多層プリント回路板の製造方法
US4824716A (en) * 1987-12-28 1989-04-25 General Electric Company Impermeable encapsulation system for integrated circuits
US4806188A (en) * 1988-03-04 1989-02-21 E. I. Du Pont De Nemours And Company Method for fabricating multilayer circuits
US4818335A (en) * 1988-05-13 1989-04-04 The United States Of America As Represented By The Director Of The National Security Agency Tapered wet etching of contacts using a trilayer silox structure

Also Published As

Publication number Publication date
US4882839A (en) 1989-11-28
JPH01270398A (ja) 1989-10-27
FR2630617A1 (fr) 1989-10-27
JPH0682926B2 (ja) 1994-10-19

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Legal Events

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