DE3874411D1 - Verfahren zur herstellung einer halbleiteranordnung mit einer schicht aus titan-wolfram. - Google Patents

Verfahren zur herstellung einer halbleiteranordnung mit einer schicht aus titan-wolfram.

Info

Publication number
DE3874411D1
DE3874411D1 DE8888200945T DE3874411T DE3874411D1 DE 3874411 D1 DE3874411 D1 DE 3874411D1 DE 8888200945 T DE8888200945 T DE 8888200945T DE 3874411 T DE3874411 T DE 3874411T DE 3874411 D1 DE3874411 D1 DE 3874411D1
Authority
DE
Germany
Prior art keywords
producing
layer
semiconductor arrangement
titanium tungsten
tungsten
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8888200945T
Other languages
English (en)
Other versions
DE3874411T2 (de
Inventor
Oekel Jacques Jules Van
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of DE3874411D1 publication Critical patent/DE3874411D1/de
Application granted granted Critical
Publication of DE3874411T2 publication Critical patent/DE3874411T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/10—Etching compositions
    • C23F1/14—Aqueous compositions
    • C23F1/16—Acidic compositions
    • C23F1/26—Acidic compositions for etching refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mechanical Engineering (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Weting (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • ing And Chemical Polishing (AREA)
DE8888200945T 1987-05-18 1988-05-11 Verfahren zur herstellung einer halbleiteranordnung mit einer schicht aus titan-wolfram. Expired - Fee Related DE3874411T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL8701184A NL8701184A (nl) 1987-05-18 1987-05-18 Werkwijze voor het vervaardigen van een halfgeleiderinrichting.

Publications (2)

Publication Number Publication Date
DE3874411D1 true DE3874411D1 (de) 1992-10-15
DE3874411T2 DE3874411T2 (de) 1993-04-08

Family

ID=19850032

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888200945T Expired - Fee Related DE3874411T2 (de) 1987-05-18 1988-05-11 Verfahren zur herstellung einer halbleiteranordnung mit einer schicht aus titan-wolfram.

Country Status (6)

Country Link
US (1) US4814293A (de)
EP (1) EP0292057B1 (de)
JP (1) JPS63305518A (de)
KR (1) KR970009862B1 (de)
DE (1) DE3874411T2 (de)
NL (1) NL8701184A (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5229311A (en) * 1989-03-22 1993-07-20 Intel Corporation Method of reducing hot-electron degradation in semiconductor devices
EP0517288B1 (de) * 1991-04-29 1996-04-10 Koninklijke Philips Electronics N.V. Erhöhung der Diffusionsbarriere einer Metallisierungsstruktur geeignet zur Herstellung von Halbleiterbauelementen
US5246732A (en) * 1991-07-16 1993-09-21 U.S. Philips Corporation Method of providing a copper pattern on a dielectric substrate
JP3135185B2 (ja) * 1993-03-19 2001-02-13 三菱電機株式会社 半導体エッチング液，半導体エッチング方法，及びＧａＡｓ面の判定方法
US5419808A (en) * 1993-03-19 1995-05-30 Mitsubishi Denki Kabushiki Kaisha Etching solution and etching method for semiconductors
US5374328A (en) * 1993-03-25 1994-12-20 Watkins Johnson Company Method of fabricating group III-V compound
US5462638A (en) 1994-06-15 1995-10-31 International Business Machines Corporation Selective etching of TiW for C4 fabrication
JPH08162425A (ja) 1994-12-06 1996-06-21 Mitsubishi Electric Corp 半導体集積回路装置の製造方法および製造装置
US5800726A (en) * 1995-07-26 1998-09-01 International Business Machines Corporation Selective chemical etching in microelectronics fabrication
US5759437A (en) * 1996-10-31 1998-06-02 International Business Machines Corporation Etching of Ti-W for C4 rework
JPH1187262A (ja) * 1997-09-03 1999-03-30 Toshiba Corp 半導体装置及びその製造方法
US6015505A (en) * 1997-10-30 2000-01-18 International Business Machines Corporation Process improvements for titanium-tungsten etching in the presence of electroplated C4's
US6436300B2 (en) 1998-07-30 2002-08-20 Motorola, Inc. Method of manufacturing electronic components
US6332988B1 (en) 1999-06-02 2001-12-25 International Business Machines Corporation Rework process
KR100379824B1 (ko) 2000-12-20 2003-04-11 엘지.필립스 엘시디 주식회사 식각용액 및 식각용액으로 패턴된 구리배선을 가지는전자기기용 어레이기판
US7521366B2 (en) * 2001-12-12 2009-04-21 Lg Display Co., Ltd. Manufacturing method of electro line for liquid crystal display device
DE10230252B4 (de) 2002-07-04 2013-10-17 Robert Bosch Gmbh Verfahren zur Herstellung integrierter Mikrosysteme
US7244671B2 (en) 2003-07-25 2007-07-17 Unitive International Limited Methods of forming conductive structures including titanium-tungsten base layers and related structures
US7727415B2 (en) * 2004-12-20 2010-06-01 Stella Chemifa Corporation Fine treatment agent and fine treatment method using same
US7425278B2 (en) * 2006-11-28 2008-09-16 International Business Machines Corporation Process of etching a titanium/tungsten surface and etchant used therein
US8025812B2 (en) * 2007-04-27 2011-09-27 International Business Machines Corporation Selective etch of TiW for capture pad formation
JP2009076601A (ja) * 2007-09-19 2009-04-09 Nagase Chemtex Corp エッチング溶液
CN102149851A (zh) * 2008-09-09 2011-08-10 昭和电工株式会社 钛系金属、钨系金属、钛钨系金属或它们的氮化物的蚀刻液
JP5169959B2 (ja) * 2009-04-08 2013-03-27 信越半導体株式会社 発光素子の製造方法
WO2015054464A1 (en) * 2013-10-11 2015-04-16 E. I. Du Pont De Nemours And Company Removal composition for selectively removing hard mask and methods thereof
US20150104952A1 (en) 2013-10-11 2015-04-16 Ekc Technology, Inc. Method and composition for selectively removing metal hardmask and other residues from semiconductor device substrates comprising low-k dielectric material and copper

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3841931A (en) * 1973-07-23 1974-10-15 Bell Telephone Labor Inc Mild acid etch for tungsten
SU707949A1 (ru) * 1976-12-14 1980-01-05 Институт химии Уральского научного центра АН СССР Раствор дл травлени вольфрама с поверхности алюмини
US4443295A (en) * 1983-06-13 1984-04-17 Fairchild Camera & Instrument Corp. Method of etching refractory metal film on semiconductor structures utilizing triethylamine and H2 O2

Also Published As

Publication number Publication date
EP0292057A1 (de) 1988-11-23
NL8701184A (nl) 1988-12-16
US4814293A (en) 1989-03-21
KR880014662A (ko) 1988-12-24
JPS63305518A (ja) 1988-12-13
KR970009862B1 (ko) 1997-06-18
JPH0257339B2 (de) 1990-12-04
EP0292057B1 (de) 1992-09-09
DE3874411T2 (de) 1993-04-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL

8327 Change in the person/name/address of the patent owner

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N

8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee