DE3381880D1 - Verfahren zur herstellung einer halbleiteranordnung mit einem diffusionsschritt. - Google Patents

Verfahren zur herstellung einer halbleiteranordnung mit einem diffusionsschritt.

Info

Publication number
DE3381880D1
DE3381880D1 DE8383111366T DE3381880T DE3381880D1 DE 3381880 D1 DE3381880 D1 DE 3381880D1 DE 8383111366 T DE8383111366 T DE 8383111366T DE 3381880 T DE3381880 T DE 3381880T DE 3381880 D1 DE3381880 D1 DE 3381880D1
Authority
DE
Germany
Prior art keywords
producing
diffusion step
semiconductor arrangement
semiconductor
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8383111366T
Other languages
English (en)
Inventor
Hidekazu Okabashi
Mitsutaka Morimoto
Eiji Nagasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP19857082A external-priority patent/JPS5988868A/ja
Priority claimed from JP6408583A external-priority patent/JPS59189623A/ja
Priority claimed from JP7048883A external-priority patent/JPS59195821A/ja
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE3381880D1 publication Critical patent/DE3381880D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/019—Contacts of silicides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/082—Ion implantation FETs/COMs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/147—Silicides
DE8383111366T 1982-11-12 1983-11-14 Verfahren zur herstellung einer halbleiteranordnung mit einem diffusionsschritt. Expired - Lifetime DE3381880D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP19857082A JPS5988868A (ja) 1982-11-12 1982-11-12 半導体装置の製造方法
JP6408583A JPS59189623A (ja) 1983-04-12 1983-04-12 半導体への不純物拡散法
JP7048883A JPS59195821A (ja) 1983-04-21 1983-04-21 半導体への不純物拡散方法

Publications (1)

Publication Number Publication Date
DE3381880D1 true DE3381880D1 (de) 1990-10-18

Family

ID=27298376

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383111366T Expired - Lifetime DE3381880D1 (de) 1982-11-12 1983-11-14 Verfahren zur herstellung einer halbleiteranordnung mit einem diffusionsschritt.

Country Status (3)

Country Link
US (1) US4558507A (de)
EP (1) EP0109082B1 (de)
DE (1) DE3381880D1 (de)

Families Citing this family (60)

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IT1213120B (it) * 1984-01-10 1989-12-14 Ates Componenti Elettron Processo per la fabbricazione di transistori mos complementari a basse tensioni di soglia in circuiti integrati ad alta densita' e struttura da esso risultante.
US4669176A (en) * 1984-07-30 1987-06-02 Seiko Epson Kabushiki Kaisha Method for diffusing a semiconductor substrate through a metal silicide layer by rapid heating
US4727038A (en) * 1984-08-22 1988-02-23 Mitsubishi Denki Kabushiki Kaisha Method of fabricating semiconductor device
EP0183995B1 (de) * 1984-11-02 1989-08-16 Hitachi, Ltd. Halbleiteranordnung mit einer Verbindungsschicht aus polykristallinem Silizium und Verfahren zu ihrer Herstellung
US5227316A (en) * 1985-01-22 1993-07-13 National Semiconductor Corporation Method of forming self aligned extended base contact for a bipolar transistor having reduced cell size
CA1216962A (en) * 1985-06-28 1987-01-20 Hussein M. Naguib Mos device processing
JPS62101026A (ja) * 1985-10-26 1987-05-11 Shin Etsu Chem Co Ltd 不純物拡散源
US4709467A (en) * 1986-03-13 1987-12-01 Advanced Micro Devices, Inc. Non-selective implantation process for forming contact regions in integrated circuits
US5094980A (en) * 1986-06-27 1992-03-10 Digital Equipment Corporation Method for providing a metal-semiconductor contact
US4788160A (en) * 1987-03-31 1988-11-29 Texas Instruments Incorporated Process for formation of shallow silicided junctions
JPH0616556B2 (ja) * 1987-04-14 1994-03-02 株式会社東芝 半導体装置
US5059546A (en) * 1987-05-01 1991-10-22 Texas Instruments Incorporated BICMOS process for forming shallow NPN emitters and mosfet source/drains
US4816423A (en) * 1987-05-01 1989-03-28 Texas Instruments Incorporated Bicmos process for forming shallow npn emitters and mosfet source/drains
KR920002350B1 (ko) * 1987-05-21 1992-03-21 마쯔시다덴기산교 가부시기가이샤 반도체장치의 제조방법
US4774204A (en) * 1987-06-02 1988-09-27 Texas Instruments Incorporated Method for forming self-aligned emitters and bases and source/drains in an integrated circuit
JPH01123417A (ja) * 1987-11-07 1989-05-16 Mitsubishi Electric Corp 半導体装置の製造方法
NL8800220A (nl) * 1988-01-29 1989-08-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij een metalen geleiderspoor op een oppervlak van een halfgeleiderlichaam wordt gebracht.
US4835112A (en) * 1988-03-08 1989-05-30 Motorola, Inc. CMOS salicide process using germanium implantation
JPH01298765A (ja) * 1988-05-27 1989-12-01 Fujitsu Ltd 半導体装置及びその製造方法
JPH0724261B2 (ja) * 1989-01-20 1995-03-15 株式会社東芝 半導体装置の製造方法
US4945070A (en) * 1989-01-24 1990-07-31 Harris Corporation Method of making cmos with shallow source and drain junctions
JPH02266562A (ja) * 1989-04-06 1990-10-31 Ricoh Co Ltd 半導体集積回路装置
US5217924A (en) * 1989-05-12 1993-06-08 Texas Instruments Incorporated Method for forming shallow junctions with a low resistivity silicide layer
JPH0727880B2 (ja) * 1989-11-10 1995-03-29 株式会社東芝 半導体装置の製造方法
JP2921889B2 (ja) * 1989-11-27 1999-07-19 株式会社東芝 半導体装置の製造方法
US5107321A (en) * 1990-04-02 1992-04-21 National Semiconductor Corporation Interconnect method for semiconductor devices
US5231042A (en) * 1990-04-02 1993-07-27 National Semiconductor Corporation Formation of silicide contacts using a sidewall oxide process
KR100214036B1 (ko) * 1991-02-19 1999-08-02 이데이 노부유끼 알루미늄계 배선형성방법
US5236872A (en) * 1991-03-21 1993-08-17 U.S. Philips Corp. Method of manufacturing a semiconductor device having a semiconductor body with a buried silicide layer
DE4113143C2 (de) * 1991-04-23 1994-08-04 Forschungszentrum Juelich Gmbh Verfahren zur Herstellung eines Schichtsystems und Schichtsystem
US5399526A (en) * 1991-06-28 1995-03-21 Sony Corporation Method of manufacturing semiconductor device by forming barrier metal layer between substrate and wiring layer
JP3285934B2 (ja) * 1991-07-16 2002-05-27 株式会社東芝 半導体装置の製造方法
DE69219529T2 (de) * 1991-08-06 1997-12-11 Nec Corp Verfahren zum Aufbringen einer Metall- oder Passivierenschicht mit hoher Haftung über einem isolierten Halbleitersubstrat
US5108954A (en) * 1991-09-23 1992-04-28 Micron Technology, Inc. Method of reducing contact resistance at silicide/active area interfaces and semiconductor devices produced according to the method
US5268317A (en) * 1991-11-12 1993-12-07 Siemens Aktiengesellschaft Method of forming shallow junctions in field effect transistors
US5316969A (en) * 1992-12-21 1994-05-31 Board Of Trustees Of The Leland Stanford Junior University Method of shallow junction formation in semiconductor devices using gas immersion laser doping
US5633177A (en) * 1993-11-08 1997-05-27 Advanced Micro Devices, Inc. Method for producing a semiconductor gate conductor having an impurity migration barrier
JP2891093B2 (ja) * 1994-02-17 1999-05-17 日本電気株式会社 半導体集積回路の製造方法
US5470794A (en) * 1994-02-23 1995-11-28 Advanced Micro Devices Method for forming a silicide using ion beam mixing
US5439831A (en) * 1994-03-09 1995-08-08 Siemens Aktiengesellschaft Low junction leakage MOSFETs
JP2614016B2 (ja) * 1994-05-31 1997-05-28 九州日本電気株式会社 半導体装置の製造方法
US5401674A (en) * 1994-06-10 1995-03-28 Advanced Micro Devices Germanium implant for use with ultra-shallow junctions
US5444024A (en) * 1994-06-10 1995-08-22 Advanced Micro Devices, Inc. Method for low energy implantation of argon to control titanium silicide formation
JPH0837164A (ja) * 1994-07-21 1996-02-06 Nec Corp 半導体装置の製造方法
JP2755185B2 (ja) * 1994-11-07 1998-05-20 日本電気株式会社 Ｓｏｉ基板
US5643821A (en) * 1994-11-09 1997-07-01 Harris Corporation Method for making ohmic contact to lightly doped islands from a silicide buried layer and applications
US5569624A (en) * 1995-06-05 1996-10-29 Regents Of The University Of California Method for shallow junction formation
US6303446B1 (en) * 1996-01-29 2001-10-16 The Regents Of The University Of California Method of making self-aligned lightly-doped-drain structure for MOS transistors
KR100527207B1 (ko) * 1996-05-08 2005-11-09 어드밴스드 마이크로 디바이시즈, 인코포레이티드 도펀트 확산을 가로막도록 생성된 격자간 변화도를 이용한접합 깊이 및 채널 길이의 제어
US5885896A (en) * 1996-07-08 1999-03-23 Micron Technology, Inc. Using implants to lower anneal temperatures
JPH10242081A (ja) * 1996-12-26 1998-09-11 Sony Corp 半導体装置の製造方法
US6027964A (en) * 1997-08-04 2000-02-22 Advanced Micro Devices, Inc. Method of making an IGFET with a selectively doped gate in combination with a protected resistor
US6482734B1 (en) * 1998-01-20 2002-11-19 Lg Semicon Co., Ltd. Diffusion barrier layer for semiconductor device and fabrication method thereof
KR100313510B1 (ko) * 1999-04-02 2001-11-07 김영환 반도체 소자의 제조방법
US6169005B1 (en) * 1999-05-26 2001-01-02 Advanced Micro Devices, Inc. Formation of junctions by diffusion from a doped amorphous silicon film during silicidation
US6380040B1 (en) 1999-08-02 2002-04-30 Advanced Micro Devices, Inc. Prevention of dopant out-diffusion during silicidation and junction formation
US6284611B1 (en) * 1999-12-20 2001-09-04 Taiwan Semiconductor Manufacturing Company Method for salicide process using a titanium nitride barrier layer
US6960528B2 (en) * 2002-09-20 2005-11-01 Academia Sinica Method of forming a nanotip array in a substrate by forming masks on portions of the substrate and etching the unmasked portions
US6982193B2 (en) * 2004-05-10 2006-01-03 Semiconductor Components Industries, L.L.C. Method of forming a super-junction semiconductor device
JP2014053557A (ja) * 2012-09-10 2014-03-20 Toshiba Corp 半導体装置およびその製造方法

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US3477886A (en) * 1964-12-07 1969-11-11 Motorola Inc Controlled diffusions in semiconductive materials
JPS567304B2 (de) * 1972-08-28 1981-02-17
US3881971A (en) * 1972-11-29 1975-05-06 Ibm Method for fabricating aluminum interconnection metallurgy system for silicon devices
US4026733A (en) * 1975-10-29 1977-05-31 Intel Corporation Process for defining polycrystalline silicon patterns
US4343082A (en) * 1980-04-17 1982-08-10 Bell Telephone Laboratories, Incorporated Method of making contact electrodes to silicon gate, and source and drain regions, of a semiconductor device
US4259680A (en) * 1980-04-17 1981-03-31 Bell Telephone Laboratories, Incorporated High speed lateral bipolar transistor
US4339869A (en) * 1980-09-15 1982-07-20 General Electric Company Method of making low resistance contacts in semiconductor devices by ion induced silicides
IE52791B1 (en) * 1980-11-05 1988-03-02 Fujitsu Ltd Semiconductor devices
JPS57111066A (en) * 1981-11-09 1982-07-10 Nec Corp Semiconuctor device
JPS58134427A (ja) * 1982-02-05 1983-08-10 Nec Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0109082A2 (de) 1984-05-23
EP0109082B1 (de) 1990-09-12
EP0109082A3 (en) 1986-06-25
US4558507A (en) 1985-12-17

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8364 No opposition during term of opposition