DE3020140A1 - Halbleiterstruktur, insbesondere transistor, und verfahren zu seiner herstellung - Google Patents

Halbleiterstruktur, insbesondere transistor, und verfahren zu seiner herstellung

Info

Publication number
DE3020140A1
DE3020140A1 DE19803020140 DE3020140A DE3020140A1 DE 3020140 A1 DE3020140 A1 DE 3020140A1 DE 19803020140 DE19803020140 DE 19803020140 DE 3020140 A DE3020140 A DE 3020140A DE 3020140 A1 DE3020140 A1 DE 3020140A1
Authority
DE
Germany
Prior art keywords
zone
doped
doped zone
semiconductor
isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19803020140
Other languages
German (de)
English (en)
Inventor
Wolfgang Martin Feist
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Raytheon Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raytheon Co filed Critical Raytheon Co
Publication of DE3020140A1 publication Critical patent/DE3020140A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/80—Heterojunction BJTs
    • H10D10/821—Vertical heterojunction BJTs
    • H10D10/861—Vertical heterojunction BJTs having an emitter region comprising one or more non-monocrystalline elements of Group IV, e.g. amorphous silicon
    • H10W10/0124—
    • H10W10/0126—
    • H10W10/13—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/168—V-Grooves

Landscapes

  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Weting (AREA)
  • Bipolar Integrated Circuits (AREA)
DE19803020140 1979-05-25 1980-05-27 Halbleiterstruktur, insbesondere transistor, und verfahren zu seiner herstellung Withdrawn DE3020140A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/042,686 US4289550A (en) 1979-05-25 1979-05-25 Method of forming closely spaced device regions utilizing selective etching and diffusion

Publications (1)

Publication Number Publication Date
DE3020140A1 true DE3020140A1 (de) 1980-12-04

Family

ID=21923236

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19803020140 Withdrawn DE3020140A1 (de) 1979-05-25 1980-05-27 Halbleiterstruktur, insbesondere transistor, und verfahren zu seiner herstellung

Country Status (7)

Country Link
US (1) US4289550A (enExample)
JP (1) JPS55157258A (enExample)
CA (1) CA1144659A (enExample)
DE (1) DE3020140A1 (enExample)
FR (1) FR2457565B1 (enExample)
GB (1) GB2050056B (enExample)
IT (1) IT1128530B (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5827341A (ja) * 1981-08-11 1983-02-18 Fujitsu Ltd 半導体装置の製造方法
US4372033A (en) * 1981-09-08 1983-02-08 Ncr Corporation Method of making coplanar MOS IC structures
US4435898A (en) 1982-03-22 1984-03-13 International Business Machines Corporation Method for making a base etched transistor integrated circuit
JPS58197877A (ja) * 1982-05-14 1983-11-17 Nec Corp 半導体集積回路装置の製造方法
GB8507624D0 (en) * 1985-03-23 1985-05-01 Standard Telephones Cables Ltd Semiconductor devices
US4933295A (en) * 1987-05-08 1990-06-12 Raytheon Company Method of forming a bipolar transistor having closely spaced device regions

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3961356A (en) * 1971-04-03 1976-06-01 U.S. Philips Corporation Integrated circuit with oxidation-junction isolation and channel stop
US4026736A (en) * 1974-01-03 1977-05-31 Motorola, Inc. Integrated semiconductor structure with combined dielectric and PN junction isolation including fabrication method therefor
US4030954A (en) * 1974-09-30 1977-06-21 Hitachi, Ltd. Method of manufacturing a semiconductor integrated circuit device
US4066473A (en) * 1976-07-15 1978-01-03 Fairchild Camera And Instrument Corporation Method of fabricating high-gain transistors

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3083441A (en) * 1959-04-13 1963-04-02 Texas Instruments Inc Method for fabricating transistors
NL170348C (nl) * 1970-07-10 1982-10-18 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een tegen dotering en tegen thermische oxydatie maskerend masker wordt aangebracht, de door de vensters in het masker vrijgelaten delen van het oppervlak worden onderworpen aan een etsbehandeling voor het vormen van verdiepingen en het halfgeleiderlichaam met het masker wordt onderworpen aan een thermische oxydatiebehandeling voor het vormen van een oxydepatroon dat de verdiepingen althans ten dele opvult.
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
NL173110C (nl) * 1971-03-17 1983-12-01 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een uit ten minste twee deellagen van verschillend materiaal samengestelde maskeringslaag wordt aangebracht.
JPS51128268A (en) * 1975-04-30 1976-11-09 Sony Corp Semiconductor unit
DE2605641C3 (de) * 1976-02-12 1979-12-20 Siemens Ag, 1000 Berlin Und 8000 Muenchen Hochfrequenztransistor und Verfahren zu seiner Herstellung
US4115797A (en) * 1976-10-04 1978-09-19 Fairchild Camera And Instrument Corporation Integrated injection logic with heavily doped injector base self-aligned with injector emitter and collector
CA1090006A (en) * 1976-12-27 1980-11-18 Wolfgang M. Feist Semiconductor structures and methods for manufacturing such structures
US4168999A (en) * 1978-12-26 1979-09-25 Fairchild Camera And Instrument Corporation Method for forming oxide isolated integrated injection logic semiconductor structures having minimal encroachment utilizing special masking techniques

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3961356A (en) * 1971-04-03 1976-06-01 U.S. Philips Corporation Integrated circuit with oxidation-junction isolation and channel stop
US4026736A (en) * 1974-01-03 1977-05-31 Motorola, Inc. Integrated semiconductor structure with combined dielectric and PN junction isolation including fabrication method therefor
US4030954A (en) * 1974-09-30 1977-06-21 Hitachi, Ltd. Method of manufacturing a semiconductor integrated circuit device
US4066473A (en) * 1976-07-15 1978-01-03 Fairchild Camera And Instrument Corporation Method of fabricating high-gain transistors

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Siemens Forsch. u. Entwickl.-Ber,, Bd. 5, 1976, Nr. 6, S. 353-359 *

Also Published As

Publication number Publication date
FR2457565A1 (fr) 1980-12-19
GB2050056B (en) 1984-02-01
JPS55157258A (en) 1980-12-06
CA1144659A (en) 1983-04-12
GB2050056A (en) 1980-12-31
JPH0243336B2 (enExample) 1990-09-28
FR2457565B1 (fr) 1985-11-15
IT1128530B (it) 1986-05-28
IT8048498A0 (it) 1980-04-23
US4289550A (en) 1981-09-15

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8130 Withdrawal