IT8048498A0 - Perfezionamento nelle strutture a semiconduttore ad esempio per transistori e procedimento per la loro fabbricazione - Google Patents
Perfezionamento nelle strutture a semiconduttore ad esempio per transistori e procedimento per la loro fabbricazioneInfo
- Publication number
- IT8048498A0 IT8048498A0 IT8048498A IT4849880A IT8048498A0 IT 8048498 A0 IT8048498 A0 IT 8048498A0 IT 8048498 A IT8048498 A IT 8048498A IT 4849880 A IT4849880 A IT 4849880A IT 8048498 A0 IT8048498 A0 IT 8048498A0
- Authority
- IT
- Italy
- Prior art keywords
- transistors
- improvement
- procedure
- manufacturing
- semiconductor structures
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
- H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
- H01L29/7375—Vertical transistors having an emitter comprising one or more non-monocrystalline elements of group IV, e.g. amorphous silicon, alloys comprising group IV elements
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/051—Etching
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/106—Masks, special
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/168—V-Grooves
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Bipolar Transistors (AREA)
- Weting (AREA)
- Bipolar Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/042,686 US4289550A (en) | 1979-05-25 | 1979-05-25 | Method of forming closely spaced device regions utilizing selective etching and diffusion |
Publications (2)
Publication Number | Publication Date |
---|---|
IT8048498A0 true IT8048498A0 (it) | 1980-04-23 |
IT1128530B IT1128530B (it) | 1986-05-28 |
Family
ID=21923236
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT48498/80A IT1128530B (it) | 1979-05-25 | 1980-04-23 | Perfezionamento nelle strutture a semiconduttore ad esempio per transistori e procedimento per la loro fabbricazione |
Country Status (7)
Country | Link |
---|---|
US (1) | US4289550A (it) |
JP (1) | JPS55157258A (it) |
CA (1) | CA1144659A (it) |
DE (1) | DE3020140A1 (it) |
FR (1) | FR2457565B1 (it) |
GB (1) | GB2050056B (it) |
IT (1) | IT1128530B (it) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5827341A (ja) * | 1981-08-11 | 1983-02-18 | Fujitsu Ltd | 半導体装置の製造方法 |
US4372033A (en) * | 1981-09-08 | 1983-02-08 | Ncr Corporation | Method of making coplanar MOS IC structures |
US4435898A (en) | 1982-03-22 | 1984-03-13 | International Business Machines Corporation | Method for making a base etched transistor integrated circuit |
JPS58197877A (ja) * | 1982-05-14 | 1983-11-17 | Nec Corp | 半導体集積回路装置の製造方法 |
GB8507624D0 (en) * | 1985-03-23 | 1985-05-01 | Standard Telephones Cables Ltd | Semiconductor devices |
US4933295A (en) * | 1987-05-08 | 1990-06-12 | Raytheon Company | Method of forming a bipolar transistor having closely spaced device regions |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3083441A (en) * | 1959-04-13 | 1963-04-02 | Texas Instruments Inc | Method for fabricating transistors |
NL170348C (nl) * | 1970-07-10 | 1982-10-18 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een tegen dotering en tegen thermische oxydatie maskerend masker wordt aangebracht, de door de vensters in het masker vrijgelaten delen van het oppervlak worden onderworpen aan een etsbehandeling voor het vormen van verdiepingen en het halfgeleiderlichaam met het masker wordt onderworpen aan een thermische oxydatiebehandeling voor het vormen van een oxydepatroon dat de verdiepingen althans ten dele opvult. |
US3648125A (en) * | 1971-02-02 | 1972-03-07 | Fairchild Camera Instr Co | Method of fabricating integrated circuits with oxidized isolation and the resulting structure |
NL173110C (nl) * | 1971-03-17 | 1983-12-01 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een uit ten minste twee deellagen van verschillend materiaal samengestelde maskeringslaag wordt aangebracht. |
NL170901C (nl) * | 1971-04-03 | 1983-01-03 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting. |
US4026736A (en) * | 1974-01-03 | 1977-05-31 | Motorola, Inc. | Integrated semiconductor structure with combined dielectric and PN junction isolation including fabrication method therefor |
JPS5138983A (it) * | 1974-09-30 | 1976-03-31 | Hitachi Ltd | |
JPS51128268A (en) * | 1975-04-30 | 1976-11-09 | Sony Corp | Semiconductor unit |
DE2605641C3 (de) * | 1976-02-12 | 1979-12-20 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Hochfrequenztransistor und Verfahren zu seiner Herstellung |
US4066473A (en) * | 1976-07-15 | 1978-01-03 | Fairchild Camera And Instrument Corporation | Method of fabricating high-gain transistors |
US4115797A (en) * | 1976-10-04 | 1978-09-19 | Fairchild Camera And Instrument Corporation | Integrated injection logic with heavily doped injector base self-aligned with injector emitter and collector |
CA1090006A (en) * | 1976-12-27 | 1980-11-18 | Wolfgang M. Feist | Semiconductor structures and methods for manufacturing such structures |
US4168999A (en) * | 1978-12-26 | 1979-09-25 | Fairchild Camera And Instrument Corporation | Method for forming oxide isolated integrated injection logic semiconductor structures having minimal encroachment utilizing special masking techniques |
-
1979
- 1979-05-25 US US06/042,686 patent/US4289550A/en not_active Expired - Lifetime
-
1980
- 1980-04-14 CA CA000349821A patent/CA1144659A/en not_active Expired
- 1980-04-23 IT IT48498/80A patent/IT1128530B/it active
- 1980-05-07 GB GB8015124A patent/GB2050056B/en not_active Expired
- 1980-05-26 JP JP6999880A patent/JPS55157258A/ja active Granted
- 1980-05-27 DE DE19803020140 patent/DE3020140A1/de not_active Withdrawn
- 1980-05-27 FR FR8011687A patent/FR2457565B1/fr not_active Expired
Also Published As
Publication number | Publication date |
---|---|
US4289550A (en) | 1981-09-15 |
GB2050056B (en) | 1984-02-01 |
GB2050056A (en) | 1980-12-31 |
DE3020140A1 (de) | 1980-12-04 |
FR2457565B1 (fr) | 1985-11-15 |
CA1144659A (en) | 1983-04-12 |
JPH0243336B2 (it) | 1990-09-28 |
IT1128530B (it) | 1986-05-28 |
JPS55157258A (en) | 1980-12-06 |
FR2457565A1 (fr) | 1980-12-19 |
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