FR2457565B1 - Composant semi-conducteur et son procede de fabrication - Google Patents

Composant semi-conducteur et son procede de fabrication

Info

Publication number
FR2457565B1
FR2457565B1 FR8011687A FR8011687A FR2457565B1 FR 2457565 B1 FR2457565 B1 FR 2457565B1 FR 8011687 A FR8011687 A FR 8011687A FR 8011687 A FR8011687 A FR 8011687A FR 2457565 B1 FR2457565 B1 FR 2457565B1
Authority
FR
France
Prior art keywords
manufacturing
semiconductor component
semiconductor
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8011687A
Other languages
English (en)
Other versions
FR2457565A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Raytheon Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raytheon Co filed Critical Raytheon Co
Publication of FR2457565A1 publication Critical patent/FR2457565A1/fr
Application granted granted Critical
Publication of FR2457565B1 publication Critical patent/FR2457565B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H01L29/7375—Vertical transistors having an emitter comprising one or more non-monocrystalline elements of group IV, e.g. amorphous silicon, alloys comprising group IV elements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/168—V-Grooves

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Weting (AREA)
  • Bipolar Integrated Circuits (AREA)
FR8011687A 1979-05-25 1980-05-27 Composant semi-conducteur et son procede de fabrication Expired FR2457565B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/042,686 US4289550A (en) 1979-05-25 1979-05-25 Method of forming closely spaced device regions utilizing selective etching and diffusion

Publications (2)

Publication Number Publication Date
FR2457565A1 FR2457565A1 (fr) 1980-12-19
FR2457565B1 true FR2457565B1 (fr) 1985-11-15

Family

ID=21923236

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8011687A Expired FR2457565B1 (fr) 1979-05-25 1980-05-27 Composant semi-conducteur et son procede de fabrication

Country Status (7)

Country Link
US (1) US4289550A (fr)
JP (1) JPS55157258A (fr)
CA (1) CA1144659A (fr)
DE (1) DE3020140A1 (fr)
FR (1) FR2457565B1 (fr)
GB (1) GB2050056B (fr)
IT (1) IT1128530B (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5827341A (ja) * 1981-08-11 1983-02-18 Fujitsu Ltd 半導体装置の製造方法
US4372033A (en) * 1981-09-08 1983-02-08 Ncr Corporation Method of making coplanar MOS IC structures
US4435898A (en) 1982-03-22 1984-03-13 International Business Machines Corporation Method for making a base etched transistor integrated circuit
JPS58197877A (ja) * 1982-05-14 1983-11-17 Nec Corp 半導体集積回路装置の製造方法
GB8507624D0 (en) * 1985-03-23 1985-05-01 Standard Telephones Cables Ltd Semiconductor devices
US4933295A (en) * 1987-05-08 1990-06-12 Raytheon Company Method of forming a bipolar transistor having closely spaced device regions

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3083441A (en) * 1959-04-13 1963-04-02 Texas Instruments Inc Method for fabricating transistors
NL170348C (nl) * 1970-07-10 1982-10-18 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een tegen dotering en tegen thermische oxydatie maskerend masker wordt aangebracht, de door de vensters in het masker vrijgelaten delen van het oppervlak worden onderworpen aan een etsbehandeling voor het vormen van verdiepingen en het halfgeleiderlichaam met het masker wordt onderworpen aan een thermische oxydatiebehandeling voor het vormen van een oxydepatroon dat de verdiepingen althans ten dele opvult.
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
NL173110C (nl) * 1971-03-17 1983-12-01 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een uit ten minste twee deellagen van verschillend materiaal samengestelde maskeringslaag wordt aangebracht.
NL170901C (nl) * 1971-04-03 1983-01-03 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
US4026736A (en) * 1974-01-03 1977-05-31 Motorola, Inc. Integrated semiconductor structure with combined dielectric and PN junction isolation including fabrication method therefor
JPS5138983A (fr) * 1974-09-30 1976-03-31 Hitachi Ltd
JPS51128268A (en) * 1975-04-30 1976-11-09 Sony Corp Semiconductor unit
DE2605641C3 (de) * 1976-02-12 1979-12-20 Siemens Ag, 1000 Berlin Und 8000 Muenchen Hochfrequenztransistor und Verfahren zu seiner Herstellung
US4066473A (en) * 1976-07-15 1978-01-03 Fairchild Camera And Instrument Corporation Method of fabricating high-gain transistors
US4115797A (en) * 1976-10-04 1978-09-19 Fairchild Camera And Instrument Corporation Integrated injection logic with heavily doped injector base self-aligned with injector emitter and collector
CA1090006A (fr) * 1976-12-27 1980-11-18 Wolfgang M. Feist Structures a semiconducteur et mode de fabrication
US4168999A (en) * 1978-12-26 1979-09-25 Fairchild Camera And Instrument Corporation Method for forming oxide isolated integrated injection logic semiconductor structures having minimal encroachment utilizing special masking techniques

Also Published As

Publication number Publication date
FR2457565A1 (fr) 1980-12-19
IT1128530B (it) 1986-05-28
CA1144659A (fr) 1983-04-12
GB2050056B (en) 1984-02-01
GB2050056A (en) 1980-12-31
DE3020140A1 (de) 1980-12-04
JPH0243336B2 (fr) 1990-09-28
JPS55157258A (en) 1980-12-06
US4289550A (en) 1981-09-15
IT8048498A0 (it) 1980-04-23

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Legal Events

Date Code Title Description
ST Notification of lapse