DE3881799T2 - Verfahren zur Herstellung von CMOS-Bauelementen. - Google Patents

Verfahren zur Herstellung von CMOS-Bauelementen.

Info

Publication number
DE3881799T2
DE3881799T2 DE88402217T DE3881799T DE3881799T2 DE 3881799 T2 DE3881799 T2 DE 3881799T2 DE 88402217 T DE88402217 T DE 88402217T DE 3881799 T DE3881799 T DE 3881799T DE 3881799 T2 DE3881799 T2 DE 3881799T2
Authority
DE
Germany
Prior art keywords
production
cmos components
cmos
components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88402217T
Other languages
English (en)
Other versions
DE3881799D1 (de
Inventor
Fu-Tai Liou
Yu-Pin Han
Frank Randolph Bryant
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Application granted granted Critical
Publication of DE3881799D1 publication Critical patent/DE3881799D1/de
Publication of DE3881799T2 publication Critical patent/DE3881799T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE88402217T 1987-09-18 1988-09-02 Verfahren zur Herstellung von CMOS-Bauelementen. Expired - Fee Related DE3881799T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/099,144 US4771014A (en) 1987-09-18 1987-09-18 Process for manufacturing LDD CMOS devices

Publications (2)

Publication Number Publication Date
DE3881799D1 DE3881799D1 (de) 1993-07-22
DE3881799T2 true DE3881799T2 (de) 1993-10-07

Family

ID=22273059

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88402217T Expired - Fee Related DE3881799T2 (de) 1987-09-18 1988-09-02 Verfahren zur Herstellung von CMOS-Bauelementen.

Country Status (5)

Country Link
US (1) US4771014A (de)
EP (1) EP0308295B1 (de)
JP (1) JP2663402B2 (de)
KR (1) KR0130549B1 (de)
DE (1) DE3881799T2 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4889825A (en) * 1986-03-04 1989-12-26 Motorola, Inc. High/low doping profile for twin well process
US4908327A (en) * 1988-05-02 1990-03-13 Texas Instruments, Incorporated Counter-doped transistor
US4949136A (en) * 1988-06-09 1990-08-14 University Of Connecticut Submicron lightly doped field effect transistors
IT1225614B (it) * 1988-08-04 1990-11-22 Sgs Thomson Microelectronics Processo per la fabbricazione di dispositivi integrati cmos con lunghezze di gate ridotte e drain leggermente drogato
US5015595A (en) * 1988-09-09 1991-05-14 Advanced Micro Devices, Inc. Method of making a high performance MOS device having both P- and N-LDD regions using single photoresist mask
NL8802219A (nl) * 1988-09-09 1990-04-02 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumlichaam waarin door ionenimplantaties halfgeleidergebieden worden gevormd.
JPH02168666A (ja) * 1988-09-29 1990-06-28 Mitsubishi Electric Corp 相補型半導体装置とその製造方法
US5030582A (en) * 1988-10-14 1991-07-09 Matsushita Electric Industrial Co., Ltd. Method of fabricating a CMOS semiconductor device
US5273914A (en) * 1988-10-14 1993-12-28 Matsushita Electric Industrial Co., Ltd. Method of fabricating a CMOS semiconductor devices
US4876213A (en) * 1988-10-31 1989-10-24 Motorola, Inc. Salicided source/drain structure
EP0405293B1 (de) * 1989-06-27 1996-08-21 National Semiconductor Corporation Silicid-Übereinstimmendes CMOS-Verfahren mit einer differenzierten Oxid-Implantierungsmaske
US5234167A (en) * 1989-11-16 1993-08-10 Afa Products, Inc. One-piece foamer nozzle
US5021354A (en) * 1989-12-04 1991-06-04 Motorola, Inc. Process for manufacturing a semiconductor device
JPH04252032A (ja) * 1990-05-24 1992-09-08 Micron Technol Inc Ｎウエルスチーム酸化工程を省略し、ブランケットｐウエル打ち込み工程によりシリコン基板上にｎウエルおよびｐウエルを形成させる方法
US5262664A (en) * 1990-06-30 1993-11-16 Goldstar Electron Co., Ltd. Process for formation of LDD transistor, and structure thereof
KR100274555B1 (ko) * 1991-06-26 2000-12-15 윌리엄 비. 켐플러 절연 게이트 전계 효과 트랜지스터 구조물 및 이의 제조 방법
US5894158A (en) * 1991-09-30 1999-04-13 Stmicroelectronics, Inc. Having halo regions integrated circuit device structure
KR940004711Y1 (ko) * 1992-07-06 1994-07-20 조길완 흘러내림 방지 수단을 구비한 바지
US5395773A (en) * 1994-03-31 1995-03-07 Vlsi Technology, Inc. MOSFET with gate-penetrating halo implant
US5492847A (en) * 1994-08-01 1996-02-20 National Semiconductor Corporation Counter-implantation method of manufacturing a semiconductor device with self-aligned anti-punchthrough pockets
US5413945A (en) * 1994-08-12 1995-05-09 United Micro Electronics Corporation Blanket N-LDD implantation for sub-micron MOS device manufacturing
US5405791A (en) * 1994-10-04 1995-04-11 Micron Semiconductor, Inc. Process for fabricating ULSI CMOS circuits using a single polysilicon gate layer and disposable spacers
US5595918A (en) * 1995-03-23 1997-01-21 International Rectifier Corporation Process for manufacture of P channel MOS-gated device
US6004854A (en) 1995-07-17 1999-12-21 Micron Technology, Inc. Method of forming CMOS integrated circuitry
US5534449A (en) * 1995-07-17 1996-07-09 Micron Technology, Inc. Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry
KR0172793B1 (ko) * 1995-08-07 1999-02-01 김주용 반도체소자의 제조방법
US5654213A (en) * 1995-10-03 1997-08-05 Integrated Device Technology, Inc. Method for fabricating a CMOS device
US5686324A (en) * 1996-03-28 1997-11-11 Mosel Vitelic, Inc. Process for forming LDD CMOS using large-tilt-angle ion implantation
US6025232A (en) 1997-11-12 2000-02-15 Micron Technology, Inc. Methods of forming field effect transistors and related field effect transistor constructions
US6252278B1 (en) * 1998-05-18 2001-06-26 Monolithic Power Systems, Inc. Self-aligned lateral DMOS with spacer drift region
US6171914B1 (en) 1999-06-14 2001-01-09 Taiwan Semiconductor Manufacturing Company Synchronized implant process to simplify NLDD/PLDD stage and N+/P+stage into one implant
US20030209847A1 (en) * 2002-05-10 2003-11-13 Allison Claudia Leigh Handling device comprising multiple immobilization segments

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6029229B2 (ja) * 1976-12-21 1985-07-09 日本電気株式会社 半導体集積回路装置
US4590663A (en) * 1982-02-01 1986-05-27 Texas Instruments Incorporated High voltage CMOS technology with N-channel source/drain extensions
JPS5923562A (ja) * 1982-07-30 1984-02-07 Hitachi Ltd 絶縁ゲ−ト型電界効果半導体装置及びその製造方法
JPS5932163A (ja) * 1982-08-18 1984-02-21 Nec Corp Ｃｍｏｓ集積回路
JPS5952849A (ja) * 1982-09-20 1984-03-27 Fujitsu Ltd 半導体装置の製造方法
US4480375A (en) * 1982-12-09 1984-11-06 International Business Machines Corporation Simple process for making complementary transistors
DE3340560A1 (de) * 1983-11-09 1985-05-15 Siemens AG, 1000 Berlin und 8000 München Verfahren zum gleichzeitigen herstellen von schnellen kurzkanal- und spannungsfesten mos-transistoren in vlsi-schaltungen
JPH0693494B2 (ja) * 1984-03-16 1994-11-16 株式会社日立製作所 半導体集積回路装置の製造方法
US4599789A (en) * 1984-06-15 1986-07-15 Harris Corporation Process of making twin well VLSI CMOS
US4577391A (en) * 1984-07-27 1986-03-25 Monolithic Memories, Inc. Method of manufacturing CMOS devices
US4642878A (en) * 1984-08-28 1987-02-17 Kabushiki Kaisha Toshiba Method of making MOS device by sequentially depositing an oxidizable layer and a masking second layer over gated device regions

Also Published As

Publication number Publication date
US4771014A (en) 1988-09-13
JP2663402B2 (ja) 1997-10-15
EP0308295B1 (de) 1993-06-16
JPH01101662A (ja) 1989-04-19
DE3881799D1 (de) 1993-07-22
KR890005894A (ko) 1989-05-17
KR0130549B1 (ko) 1998-04-06
EP0308295A1 (de) 1989-03-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee