DE69014707D1 - Verfahren zur Herstellung von CMOS-Feldeffekt-Transistoren. - Google Patents

Verfahren zur Herstellung von CMOS-Feldeffekt-Transistoren.

Info

Publication number
DE69014707D1
DE69014707D1 DE69014707T DE69014707T DE69014707D1 DE 69014707 D1 DE69014707 D1 DE 69014707D1 DE 69014707 T DE69014707 T DE 69014707T DE 69014707 T DE69014707 T DE 69014707T DE 69014707 D1 DE69014707 D1 DE 69014707D1
Authority
DE
Germany
Prior art keywords
production
field effect
effect transistors
cmos field
cmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69014707T
Other languages
English (en)
Other versions
DE69014707T2 (de
Inventor
Samuel C Gioia
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MagnaChip Semiconductor Ltd
NCR International Inc
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of DE69014707D1 publication Critical patent/DE69014707D1/de
Publication of DE69014707T2 publication Critical patent/DE69014707T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE69014707T 1989-05-01 1990-04-27 Verfahren zur Herstellung von CMOS-Feldeffekt-Transistoren. Expired - Lifetime DE69014707T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/345,875 US4874713A (en) 1989-05-01 1989-05-01 Method of making asymmetrically optimized CMOS field effect transistors

Publications (2)

Publication Number Publication Date
DE69014707D1 true DE69014707D1 (de) 1995-01-19
DE69014707T2 DE69014707T2 (de) 1995-07-27

Family

ID=23356881

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69014707T Expired - Lifetime DE69014707T2 (de) 1989-05-01 1990-04-27 Verfahren zur Herstellung von CMOS-Feldeffekt-Transistoren.

Country Status (4)

Country Link
US (1) US4874713A (de)
EP (1) EP0396357B1 (de)
JP (1) JP2942998B2 (de)
DE (1) DE69014707T2 (de)

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Publication number Priority date Publication date Assignee Title
US5006477A (en) * 1988-11-25 1991-04-09 Hughes Aircraft Company Method of making a latch up free, high voltage, CMOS bulk process for sub-half micron devices
US5079180A (en) * 1988-12-22 1992-01-07 Texas Instruments Incorporated Method of fabricating a raised source/drain transistor
US5286998A (en) * 1989-05-31 1994-02-15 Fujitsu Limited Semiconductor device having two transistors forming a memory cell and a peripheral circuit, wherein the impurity region of the first transistor is not subjected to an etching atmosphere
US5070029A (en) * 1989-10-30 1991-12-03 Motorola, Inc. Semiconductor process using selective deposition
US5296401A (en) * 1990-01-11 1994-03-22 Mitsubishi Denki Kabushiki Kaisha MIS device having p channel MOS device and n channel MOS device with LDD structure and manufacturing method thereof
IT1239707B (it) * 1990-03-15 1993-11-15 St Microelectrics Srl Processo per la realizzazione di una cella di memoria rom a bassa capacita' di drain
US6078079A (en) * 1990-04-03 2000-06-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same
KR950000141B1 (ko) * 1990-04-03 1995-01-10 미쓰비시 뎅끼 가부시끼가이샤 반도체 장치 및 그 제조방법
US5262344A (en) * 1990-04-27 1993-11-16 Digital Equipment Corporation N-channel clamp for ESD protection in self-aligned silicided CMOS process
US5045486A (en) * 1990-06-26 1991-09-03 At&T Bell Laboratories Transistor fabrication method
KR960012587B1 (ko) * 1991-10-01 1996-09-23 니뽄 덴끼 가부시끼가이샤 비대칭적으로 얇게 도핑된 드레인-금속 산화물 반도체 전계효과 트랜지스터(ldd-mosfet) 제조 방법
EP0575688B1 (de) * 1992-06-26 1998-05-27 STMicroelectronics S.r.l. Programmierung von LDD-ROM-Zellen
US5342798A (en) * 1993-11-23 1994-08-30 Vlsi Technology, Inc. Method for selective salicidation of source/drain regions of a transistor
US5960319A (en) 1995-10-04 1999-09-28 Sharp Kabushiki Kaisha Fabrication method for a semiconductor device
US6720627B1 (en) * 1995-10-04 2004-04-13 Sharp Kabushiki Kaisha Semiconductor device having junction depths for reducing short channel effect
KR0161885B1 (ko) * 1995-12-26 1999-02-01 문정환 반도체 소자와 그의 제조방법
US6037254A (en) * 1996-10-31 2000-03-14 Texas Instruments Incorporated Method of making a surface protective layer for improved silicide formation
JPH1168103A (ja) * 1997-08-22 1999-03-09 Mitsubishi Electric Corp 半導体装置の製造方法
TW359886B (en) * 1997-09-02 1999-06-01 United Microelectronics Corp Electrostatic discharge protection device and production process therefor
US6001721A (en) * 1998-02-19 1999-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide and salicide on the same chip
US6710424B2 (en) 2001-09-21 2004-03-23 Airip RF chipset architecture
JP4483179B2 (ja) * 2003-03-03 2010-06-16 株式会社デンソー 半導体装置の製造方法
US20060267130A1 (en) * 2003-06-26 2006-11-30 Rj Mears, Llc Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween
US9000525B2 (en) * 2010-05-19 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for alignment marks

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3686080A (en) * 1971-07-21 1972-08-22 Rca Corp Method of fabrication of semiconductor devices
US3747200A (en) * 1972-03-31 1973-07-24 Motorola Inc Integrated circuit fabrication method
JPS567304B2 (de) * 1972-08-28 1981-02-17
US4267012A (en) * 1979-04-30 1981-05-12 Fairchild Camera & Instrument Corp. Process for patterning metal connections on a semiconductor structure by using a tungsten-titanium etch resistant layer
US4622735A (en) * 1980-12-12 1986-11-18 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device utilizing self-aligned silicide regions
US4441247A (en) * 1981-06-29 1984-04-10 Intel Corporation Method of making MOS device by forming self-aligned polysilicon and tungsten composite gate
JPS5950567A (ja) * 1982-09-16 1984-03-23 Hitachi Ltd 電界効果トランジスタの製造方法
US4503601A (en) * 1983-04-18 1985-03-12 Ncr Corporation Oxide trench structure for polysilicon gates and interconnects
JPH0695563B2 (ja) * 1985-02-01 1994-11-24 株式会社日立製作所 半導体装置
US4648175A (en) * 1985-06-12 1987-03-10 Ncr Corporation Use of selectively deposited tungsten for contact formation and shunting metallization
US4722909A (en) * 1985-09-26 1988-02-02 Motorola, Inc. Removable sidewall spacer for lightly doped drain formation using two mask levels
US4703551A (en) * 1986-01-24 1987-11-03 Ncr Corporation Process for forming LDD MOS/CMOS structures
US4711701A (en) * 1986-09-16 1987-12-08 Texas Instruments Incorporated Self-aligned transistor method
EP0292042B1 (de) * 1987-05-14 1992-08-26 Koninklijke Philips Electronics N.V. Verfahren zur Halbleiterherstellung, wobei unter Verwendung einer Hilfsoxidation die Tunnelausbildung bei der Wolframabscheidung reduziert wird

Also Published As

Publication number Publication date
DE69014707T2 (de) 1995-07-27
EP0396357A1 (de) 1990-11-07
JPH02303157A (ja) 1990-12-17
US4874713A (en) 1989-10-17
EP0396357B1 (de) 1994-12-07
JP2942998B2 (ja) 1999-08-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL IN

8327 Change in the person/name/address of the patent owner

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DELAWAR

8327 Change in the person/name/address of the patent owner

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DELAWAR

8328 Change in the person/name/address of the agent

Free format text: V. BEZOLD & SOZIEN, 80799 MUENCHEN

8327 Change in the person/name/address of the patent owner

Owner name: HYNIX SEMICONDUCTOR INC., ICHON, KYONGGI, KR

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DEL, US

8327 Change in the person/name/address of the patent owner

Owner name: MAGNACHIP SEMICONDUCTOR, LTD., CHEONGJU, KR

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DEL, US