DE112014003019B4 - Prozess für die Herstellung einer Verbundstruktur - Google Patents

Prozess für die Herstellung einer Verbundstruktur Download PDF

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Publication number
DE112014003019B4
DE112014003019B4 DE112014003019.8T DE112014003019T DE112014003019B4 DE 112014003019 B4 DE112014003019 B4 DE 112014003019B4 DE 112014003019 T DE112014003019 T DE 112014003019T DE 112014003019 B4 DE112014003019 B4 DE 112014003019B4
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Germany
Prior art keywords
phase
implantation
dose
working layer
layer
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DE112014003019.8T
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German (de)
English (en)
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DE112014003019T5 (de
Inventor
Nadia Ben Mohamed
Eric Maze
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Soitec SA
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Soitec SA
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Publication of DE112014003019T5 publication Critical patent/DE112014003019T5/de
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00349—Creating layers of material on a substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00349—Creating layers of material on a substrate
    • B81C1/00373—Selective deposition, e.g. printing or microcontact printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Element Separation (AREA)
  • Physical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)
  • Medicinal Preparation (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Thin Film Transistor (AREA)
DE112014003019.8T 2013-06-28 2014-06-17 Prozess für die Herstellung einer Verbundstruktur Active DE112014003019B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR1301528A FR3007891B1 (fr) 2013-06-28 2013-06-28 Procede de fabrication d'une structure composite
FR1301528 2013-06-28
PCT/FR2014/051487 WO2014207346A1 (fr) 2013-06-28 2014-06-17 Procede de fabrication d'une structure composite

Publications (2)

Publication Number Publication Date
DE112014003019T5 DE112014003019T5 (de) 2016-03-17
DE112014003019B4 true DE112014003019B4 (de) 2025-06-05

Family

ID=49474468

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112014003019.8T Active DE112014003019B4 (de) 2013-06-28 2014-06-17 Prozess für die Herstellung einer Verbundstruktur

Country Status (7)

Country Link
US (1) US9887124B2 (https=)
JP (1) JP6470275B2 (https=)
CN (1) CN105358474B (https=)
DE (1) DE112014003019B4 (https=)
FR (1) FR3007891B1 (https=)
SG (1) SG11201510631VA (https=)
WO (1) WO2014207346A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6747386B2 (ja) * 2017-06-23 2020-08-26 信越半導体株式会社 Ｓｏｉウェーハの製造方法
FR3116151A1 (fr) * 2020-11-10 2022-05-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de formation d’une structure de piegeage d’un substrat utile
FR3134229B1 (fr) * 2022-04-01 2024-03-08 Commissariat Energie Atomique Procede de transfert d’une couche mince sur un substrat support

Citations (3)

* Cited by examiner, † Cited by third party
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US20050148163A1 (en) * 2003-12-19 2005-07-07 Nguyet-Phuong Nguyen Method of catastrophic transfer of a thin film after co-implantation
EP1705704A1 (en) * 2004-01-08 2006-09-27 SUMCO Corporation Process for producing soi wafer
JP2010161134A (ja) * 2009-01-07 2010-07-22 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法

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JP3031904B2 (ja) * 1998-02-18 2000-04-10 キヤノン株式会社 複合部材とその分離方法、及びそれを利用した半導体基体の製造方法
MY118019A (en) * 1998-02-18 2004-08-30 Canon Kk Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof
FR2797714B1 (fr) * 1999-08-20 2001-10-26 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
FR2809867B1 (fr) * 2000-05-30 2003-10-24 Commissariat Energie Atomique Substrat fragilise et procede de fabrication d'un tel substrat
FR2816445B1 (fr) * 2000-11-06 2003-07-25 Commissariat Energie Atomique Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible
FR2817394B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
FR2894990B1 (fr) * 2005-12-21 2008-02-22 Soitec Silicon On Insulator Procede de fabrication de substrats, notamment pour l'optique,l'electronique ou l'optoelectronique et substrat obtenu selon ledit procede
FR2823599B1 (fr) * 2001-04-13 2004-12-17 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
FR2827423B1 (fr) * 2001-07-16 2005-05-20 Soitec Silicon On Insulator Procede d'amelioration d'etat de surface
US6884696B2 (en) * 2001-07-17 2005-04-26 Shin-Etsu Handotai Co., Ltd. Method for producing bonding wafer
FR2835095B1 (fr) * 2002-01-22 2005-03-18 Procede de preparation d'ensembles a semi-conducteurs separables, notamment pour former des substrats pour l'electronique, l'optoelectrique et l'optique
KR100511656B1 (ko) * 2002-08-10 2005-09-07 주식회사 실트론 나노 에스오아이 웨이퍼의 제조방법 및 그에 따라 제조된나노 에스오아이 웨이퍼
US6911375B2 (en) * 2003-06-02 2005-06-28 International Business Machines Corporation Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
FR2857983B1 (fr) * 2003-07-24 2005-09-02 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
US7179719B2 (en) * 2004-09-28 2007-02-20 Sharp Laboratories Of America, Inc. System and method for hydrogen exfoliation
FR2877491B1 (fr) * 2004-10-29 2007-01-19 Soitec Silicon On Insulator Structure composite a forte dissipation thermique
US8138061B2 (en) * 2005-01-07 2012-03-20 International Business Machines Corporation Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide
JP2006216826A (ja) * 2005-02-04 2006-08-17 Sumco Corp Ｓｏｉウェーハの製造方法
FR2890489B1 (fr) * 2005-09-08 2008-03-07 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure de type semi-conducteur sur isolant
JP2007242972A (ja) * 2006-03-09 2007-09-20 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハの製造方法
JP2008028070A (ja) 2006-07-20 2008-02-07 Sumco Corp 貼り合わせウェーハの製造方法
US20080070340A1 (en) * 2006-09-14 2008-03-20 Nicholas Francis Borrelli Image sensor using thin-film SOI
FR2910179B1 (fr) * 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
FR2911430B1 (fr) * 2007-01-15 2009-04-17 Soitec Silicon On Insulator "procede de fabrication d'un substrat hybride"
FR2912259B1 (fr) * 2007-02-01 2009-06-05 Soitec Silicon On Insulator Procede de fabrication d'un substrat du type "silicium sur isolant".
FR2913528B1 (fr) * 2007-03-06 2009-07-03 Soitec Silicon On Insulator Procede de fabrication d'un substrat comportant une couche d'oxyde enterree pour la realisation de composants electroniques ou analogues.
US7767542B2 (en) * 2007-04-20 2010-08-03 Semiconductor Energy Laboratory Co., Ltd Manufacturing method of SOI substrate
US7619283B2 (en) * 2007-04-20 2009-11-17 Corning Incorporated Methods of fabricating glass-based substrates and apparatus employing same
US7763502B2 (en) * 2007-06-22 2010-07-27 Semiconductor Energy Laboratory Co., Ltd Semiconductor substrate, method for manufacturing semiconductor substrate, semiconductor device, and electronic device
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JP5478199B2 (ja) * 2008-11-13 2014-04-23 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP5607399B2 (ja) * 2009-03-24 2014-10-15 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
CN102986020A (zh) * 2010-06-30 2013-03-20 康宁股份有限公司 对绝缘体基材上的硅进行精整的方法
US8487280B2 (en) * 2010-10-21 2013-07-16 Varian Semiconductor Equipment Associates, Inc. Modulating implantation for improved workpiece splitting
JP5802436B2 (ja) * 2011-05-30 2015-10-28 信越半導体株式会社 貼り合わせウェーハの製造方法
JP5587257B2 (ja) * 2011-07-06 2014-09-10 信越半導体株式会社 イオン注入機の基板保持具の劣化判定方法
CN102386123B (zh) 2011-07-29 2013-11-13 上海新傲科技股份有限公司 制备具有均匀厚度器件层的衬底的方法
CN102347219A (zh) * 2011-09-23 2012-02-08 中国科学院微电子研究所 形成复合功能材料结构的方法
JP5670303B2 (ja) * 2011-12-08 2015-02-18 信越半導体株式会社 イオン注入機の基板保持具の劣化判定方法
JP5927894B2 (ja) 2011-12-15 2016-06-01 信越半導体株式会社 Ｓｏｉウェーハの製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050148163A1 (en) * 2003-12-19 2005-07-07 Nguyet-Phuong Nguyen Method of catastrophic transfer of a thin film after co-implantation
EP1705704A1 (en) * 2004-01-08 2006-09-27 SUMCO Corporation Process for producing soi wafer
JP2010161134A (ja) * 2009-01-07 2010-07-22 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法

Also Published As

Publication number Publication date
FR3007891A1 (fr) 2015-01-02
CN105358474B (zh) 2018-02-13
SG11201510631VA (en) 2016-01-28
US9887124B2 (en) 2018-02-06
FR3007891B1 (fr) 2016-11-25
DE112014003019T5 (de) 2016-03-17
JP2016526796A (ja) 2016-09-05
CN105358474A (zh) 2016-02-24
US20160372361A1 (en) 2016-12-22
JP6470275B2 (ja) 2019-02-13
WO2014207346A1 (fr) 2014-12-31

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