SG11201510631VA - Process For The Manufacture Of A Composite Structure - Google Patents
Process For The Manufacture Of A Composite StructureInfo
- Publication number
- SG11201510631VA SG11201510631VA SG11201510631VA SG11201510631VA SG11201510631VA SG 11201510631V A SG11201510631V A SG 11201510631VA SG 11201510631V A SG11201510631V A SG 11201510631VA SG 11201510631V A SG11201510631V A SG 11201510631VA SG 11201510631V A SG11201510631V A SG 11201510631VA
- Authority
- SG
- Singapore
- Prior art keywords
- manufacture
- composite structure
- composite
- Prior art date
Links
- 239000002131 composite material Substances 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
- Medicinal Preparation (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Physical Vapour Deposition (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1301528A FR3007891B1 (en) | 2013-06-28 | 2013-06-28 | METHOD FOR MANUFACTURING A COMPOSITE STRUCTURE |
PCT/FR2014/051487 WO2014207346A1 (en) | 2013-06-28 | 2014-06-17 | Method for producing a composite structure |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11201510631VA true SG11201510631VA (en) | 2016-01-28 |
Family
ID=49474468
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201510631VA SG11201510631VA (en) | 2013-06-28 | 2014-06-17 | Process For The Manufacture Of A Composite Structure |
Country Status (7)
Country | Link |
---|---|
US (1) | US9887124B2 (en) |
JP (1) | JP6470275B2 (en) |
CN (1) | CN105358474B (en) |
DE (1) | DE112014003019T5 (en) |
FR (1) | FR3007891B1 (en) |
SG (1) | SG11201510631VA (en) |
WO (1) | WO2014207346A1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6747386B2 (en) * | 2017-06-23 | 2020-08-26 | 信越半導体株式会社 | Method for manufacturing SOI wafer |
FR3116151A1 (en) * | 2020-11-10 | 2022-05-13 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | METHOD FOR FORMING A USEFUL SUBSTRATE TRAPPING STRUCTURE |
Family Cites Families (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW437078B (en) * | 1998-02-18 | 2001-05-28 | Canon Kk | Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof |
JP3031904B2 (en) * | 1998-02-18 | 2000-04-10 | キヤノン株式会社 | Composite member, method of separating the same, and method of manufacturing semiconductor substrate using the same |
FR2797714B1 (en) * | 1999-08-20 | 2001-10-26 | Soitec Silicon On Insulator | PROCESS FOR PROCESSING SUBSTRATES FOR MICROELECTRONICS AND SUBSTRATES OBTAINED BY THIS PROCESS |
FR2809867B1 (en) * | 2000-05-30 | 2003-10-24 | Commissariat Energie Atomique | FRAGILE SUBSTRATE AND METHOD FOR MANUFACTURING SUCH SUBSTRATE |
FR2816445B1 (en) * | 2000-11-06 | 2003-07-25 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING A STACKED STRUCTURE COMPRISING A THIN LAYER ADHERING TO A TARGET SUBSTRATE |
FR2817394B1 (en) * | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | METHOD FOR MANUFACTURING A SUBSTRATE, IN PARTICULAR FOR OPTICS, ELECTRONICS OR OPTOELECTRONICS AND SUBSTRATE OBTAINED THEREBY |
FR2894990B1 (en) * | 2005-12-21 | 2008-02-22 | Soitec Silicon On Insulator | PROCESS FOR PRODUCING SUBSTRATES, IN PARTICULAR FOR OPTICS, ELECTRONICS OR OPTOELECTRONICS AND SUBSTRATE OBTAINED BY SAID PROCESS |
FR2823599B1 (en) * | 2001-04-13 | 2004-12-17 | Commissariat Energie Atomique | DEMOMTABLE SUBSTRATE WITH CONTROLLED MECHANICAL HOLDING AND METHOD OF MAKING |
FR2827423B1 (en) * | 2001-07-16 | 2005-05-20 | Soitec Silicon On Insulator | METHOD OF IMPROVING SURFACE CONDITION |
KR100874724B1 (en) * | 2001-07-17 | 2008-12-19 | 신에쯔 한도타이 가부시키가이샤 | Manufacturing method of bonded wafer |
FR2835095B1 (en) * | 2002-01-22 | 2005-03-18 | PROCESS FOR PREPARING SEPARABLE SEMICONDUCTOR ASSEMBLIES, IN PARTICULAR FOR FORMING SUBSTRATES FOR ELECTRONICS, OPTOELECTRIC, AND OPTICS | |
KR100511656B1 (en) * | 2002-08-10 | 2005-09-07 | 주식회사 실트론 | Method of fabricating nano SOI wafer and nano SOI wafer fabricated by the same |
US6911375B2 (en) * | 2003-06-02 | 2005-06-28 | International Business Machines Corporation | Method of fabricating silicon devices on sapphire with wafer bonding at low temperature |
FR2857983B1 (en) * | 2003-07-24 | 2005-09-02 | Soitec Silicon On Insulator | PROCESS FOR PRODUCING AN EPITAXIC LAYER |
US7772087B2 (en) * | 2003-12-19 | 2010-08-10 | Commissariat A L'energie Atomique | Method of catastrophic transfer of a thin film after co-implantation |
JP4285244B2 (en) * | 2004-01-08 | 2009-06-24 | 株式会社Sumco | Manufacturing method of SOI wafer |
US7179719B2 (en) * | 2004-09-28 | 2007-02-20 | Sharp Laboratories Of America, Inc. | System and method for hydrogen exfoliation |
FR2877491B1 (en) * | 2004-10-29 | 2007-01-19 | Soitec Silicon On Insulator | COMPOSITE STRUCTURE WITH HIGH THERMAL DISSIPATION |
US8138061B2 (en) * | 2005-01-07 | 2012-03-20 | International Business Machines Corporation | Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide |
JP2006216826A (en) * | 2005-02-04 | 2006-08-17 | Sumco Corp | Manufacturing method of soi wafer |
FR2890489B1 (en) * | 2005-09-08 | 2008-03-07 | Soitec Silicon On Insulator | METHOD FOR MANUFACTURING A SEMICONDUCTOR TYPE HETEROSTRUCTURE ON INSULATION |
JP2007242972A (en) * | 2006-03-09 | 2007-09-20 | Shin Etsu Handotai Co Ltd | Manufacturing method for soi wafer |
JP2008028070A (en) * | 2006-07-20 | 2008-02-07 | Sumco Corp | Method for manufacturing laminated wafer |
US20080070340A1 (en) * | 2006-09-14 | 2008-03-20 | Nicholas Francis Borrelli | Image sensor using thin-film SOI |
FR2910179B1 (en) * | 2006-12-19 | 2009-03-13 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING THIN LAYERS OF GaN BY IMPLANTATION AND RECYCLING OF A STARTING SUBSTRATE |
FR2911430B1 (en) * | 2007-01-15 | 2009-04-17 | Soitec Silicon On Insulator | "METHOD OF MANUFACTURING A HYBRID SUBSTRATE" |
FR2912259B1 (en) * | 2007-02-01 | 2009-06-05 | Soitec Silicon On Insulator | PROCESS FOR PRODUCING A SUBSTRATE OF THE "SILICON ON INSULATION" TYPE |
FR2913528B1 (en) * | 2007-03-06 | 2009-07-03 | Soitec Silicon On Insulator | PROCESS FOR PRODUCING A SUBSTRATE HAVING A BONE OXIDE LAYER FOR PRODUCING ELECTRONIC OR SIMILAR COMPONENTS |
US7619283B2 (en) * | 2007-04-20 | 2009-11-17 | Corning Incorporated | Methods of fabricating glass-based substrates and apparatus employing same |
US7767542B2 (en) * | 2007-04-20 | 2010-08-03 | Semiconductor Energy Laboratory Co., Ltd | Manufacturing method of SOI substrate |
US7763502B2 (en) * | 2007-06-22 | 2010-07-27 | Semiconductor Energy Laboratory Co., Ltd | Semiconductor substrate, method for manufacturing semiconductor substrate, semiconductor device, and electronic device |
JP5386856B2 (en) * | 2008-06-03 | 2014-01-15 | 株式会社Sumco | Manufacturing method of bonded wafer |
JP5478199B2 (en) * | 2008-11-13 | 2014-04-23 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
JP5607399B2 (en) * | 2009-03-24 | 2014-10-15 | 株式会社半導体エネルギー研究所 | Method for manufacturing SOI substrate |
US20130089968A1 (en) * | 2010-06-30 | 2013-04-11 | Alex Usenko | Method for finishing silicon on insulator substrates |
US8487280B2 (en) * | 2010-10-21 | 2013-07-16 | Varian Semiconductor Equipment Associates, Inc. | Modulating implantation for improved workpiece splitting |
JP5802436B2 (en) * | 2011-05-30 | 2015-10-28 | 信越半導体株式会社 | Manufacturing method of bonded wafer |
JP5587257B2 (en) * | 2011-07-06 | 2014-09-10 | 信越半導体株式会社 | Deterioration judgment method for substrate holder of ion implanter |
CN102386123B (en) * | 2011-07-29 | 2013-11-13 | 上海新傲科技股份有限公司 | Method for preparing substrate with uniform-thickness device layer |
CN102347219A (en) * | 2011-09-23 | 2012-02-08 | 中国科学院微电子研究所 | Method for forming composite functional material structure |
JP5670303B2 (en) * | 2011-12-08 | 2015-02-18 | 信越半導体株式会社 | Deterioration judgment method for substrate holder of ion implanter |
JP5927894B2 (en) * | 2011-12-15 | 2016-06-01 | 信越半導体株式会社 | Manufacturing method of SOI wafer |
-
2013
- 2013-06-28 FR FR1301528A patent/FR3007891B1/en active Active
-
2014
- 2014-06-17 DE DE112014003019.8T patent/DE112014003019T5/en active Pending
- 2014-06-17 US US14/900,257 patent/US9887124B2/en active Active
- 2014-06-17 SG SG11201510631VA patent/SG11201510631VA/en unknown
- 2014-06-17 JP JP2016522698A patent/JP6470275B2/en active Active
- 2014-06-17 CN CN201480036456.1A patent/CN105358474B/en active Active
- 2014-06-17 WO PCT/FR2014/051487 patent/WO2014207346A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2014207346A1 (en) | 2014-12-31 |
DE112014003019T5 (en) | 2016-03-17 |
US9887124B2 (en) | 2018-02-06 |
CN105358474A (en) | 2016-02-24 |
CN105358474B (en) | 2018-02-13 |
US20160372361A1 (en) | 2016-12-22 |
FR3007891A1 (en) | 2015-01-02 |
JP6470275B2 (en) | 2019-02-13 |
JP2016526796A (en) | 2016-09-05 |
FR3007891B1 (en) | 2016-11-25 |
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