SG11201507963QA - Process for manufacturing a composite structure - Google Patents

Process for manufacturing a composite structure

Info

Publication number
SG11201507963QA
SG11201507963QA SG11201507963QA SG11201507963QA SG11201507963QA SG 11201507963Q A SG11201507963Q A SG 11201507963QA SG 11201507963Q A SG11201507963Q A SG 11201507963QA SG 11201507963Q A SG11201507963Q A SG 11201507963QA SG 11201507963Q A SG11201507963Q A SG 11201507963QA
Authority
SG
Singapore
Prior art keywords
manufacturing
composite structure
composite
Prior art date
Application number
SG11201507963QA
Inventor
Sébastien Kerdiles
Guillaume Chabanne
François Boedt
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11201507963QA publication Critical patent/SG11201507963QA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/62—Manufacture or treatment of semiconductor devices or of parts thereof the devices having no potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Micromachines (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
SG11201507963QA 2013-03-29 2014-03-21 Process for manufacturing a composite structure SG11201507963QA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1300738A FR3003997B1 (en) 2013-03-29 2013-03-29 METHOD FOR MANUFACTURING A COMPOSITE STRUCTURE
PCT/FR2014/050666 WO2014154978A1 (en) 2013-03-29 2014-03-21 Process for manufacturing a composite structure

Publications (1)

Publication Number Publication Date
SG11201507963QA true SG11201507963QA (en) 2015-10-29

Family

ID=48856695

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201507963QA SG11201507963QA (en) 2013-03-29 2014-03-21 Process for manufacturing a composite structure

Country Status (9)

Country Link
US (1) US9799549B2 (en)
EP (1) EP2979296A1 (en)
JP (1) JP6306684B2 (en)
KR (1) KR20150140313A (en)
CN (1) CN105074895A (en)
FR (1) FR3003997B1 (en)
RU (1) RU2645895C2 (en)
SG (1) SG11201507963QA (en)
WO (1) WO2014154978A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3326818C2 (en) * 1983-07-26 1986-11-06 Rudolf 8729 Zeil Weigmann Pair of crutches for the standing and walking disabled with a seat
US20180175008A1 (en) * 2015-01-09 2018-06-21 Silicon Genesis Corporation Three dimensional integrated circuit

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003224247A (en) 2002-01-29 2003-08-08 Shin Etsu Handotai Co Ltd Soi wafer and its manufacturing method
FR2852143B1 (en) * 2003-03-04 2005-10-14 Soitec Silicon On Insulator PROCESS FOR THE PREVENTIVE TREATMENT OF THE CROWN OF A MULTILAYER SLICE
JP4854917B2 (en) * 2003-03-18 2012-01-18 信越半導体株式会社 SOI wafer and manufacturing method thereof
JP4730581B2 (en) * 2004-06-17 2011-07-20 信越半導体株式会社 Manufacturing method of bonded wafer
JP2006173354A (en) * 2004-12-15 2006-06-29 Canon Inc Manufacturing method of soi substrate
US7781309B2 (en) * 2005-12-22 2010-08-24 Sumco Corporation Method for manufacturing direct bonded SOI wafer and direct bonded SOI wafer manufactured by the method
CN101669193B (en) * 2007-04-27 2012-02-15 株式会社半导体能源研究所 Soi substrate and manufacturing method of the same, and semiconductor device
US7875532B2 (en) * 2007-06-15 2011-01-25 Semiconductor Energy Laboratory Co., Ltd. Substrate for manufacturing semiconductor device and manufacturing method thereof
JP5498670B2 (en) * 2007-07-13 2014-05-21 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor substrate
TWI493609B (en) * 2007-10-23 2015-07-21 Semiconductor Energy Lab Method for manufacturing semiconductor substrate, display panel, and display device
US8357974B2 (en) * 2010-06-30 2013-01-22 Corning Incorporated Semiconductor on glass substrate with stiffening layer and process of making the same
FR2967295B1 (en) * 2010-11-05 2013-01-11 Soitec Silicon On Insulator PROCESS FOR PROCESSING A MULTILAYER STRUCTURE
RU2469433C1 (en) * 2011-07-13 2012-12-10 Юрий Георгиевич Шретер Method for laser separation of epitaxial film or layer of epitaxial film from growth substrate of epitaxial semiconductor structure (versions)

Also Published As

Publication number Publication date
FR3003997B1 (en) 2015-03-20
FR3003997A1 (en) 2014-10-03
EP2979296A1 (en) 2016-02-03
US9799549B2 (en) 2017-10-24
JP2016519431A (en) 2016-06-30
JP6306684B2 (en) 2018-04-04
CN105074895A (en) 2015-11-18
WO2014154978A1 (en) 2014-10-02
KR20150140313A (en) 2015-12-15
US20160042989A1 (en) 2016-02-11
RU2645895C2 (en) 2018-02-28
RU2015141124A (en) 2017-05-04

Similar Documents

Publication Publication Date Title
ZA201603220B (en) Processes for producing effects layers
GB2520596B (en) Manufacturing method
GB201310854D0 (en) Photoactive layer production process
IL243207B (en) Process for manufacturing 4 -propargylated amino-benzoxazinones
GB2516274B (en) Prepreg for manufacturing composite materials
PL3007844T3 (en) Method for manufacturing a titanium-aluminium alloy part
HK1216098A1 (en) Vortioxetine manufacturing process
IL240748A0 (en) A process for the production of adenvirus
PL3036276T3 (en) Method for producing a composite plastic component
DK3533325T3 (en) Process for forming a coverbraided ribline
SG11201505242UA (en) Method for making a covering
IL241287A0 (en) Processes for producing sovaprevir
HK1207406A1 (en) Process for manufacturing a composite material
GB2516978B (en) Process for manufacturing a release liner
PT3017079T (en) Process for the production tixsi1-xn layers
PL3022787T3 (en) Method for producing a composite semifinished product
SG11201507963QA (en) Process for manufacturing a composite structure
HK1222392A1 (en) Process for preparing a compound
SG11201510631VA (en) Process For The Manufacture Of A Composite Structure
EP2949643A4 (en) Manufacturing process for memantine
GB201322303D0 (en) Production process
GB201303604D0 (en) Manufacturing process
PL2983923T3 (en) Method for manufacturing panels
GB201307620D0 (en) A method of manufacturing a structure
GB201318245D0 (en) Process for constructing a database