DE102014103186B4 - Halbleitervorrichtung und Halbleiterpackage - Google Patents
Halbleitervorrichtung und Halbleiterpackage Download PDFInfo
- Publication number
- DE102014103186B4 DE102014103186B4 DE102014103186.5A DE102014103186A DE102014103186B4 DE 102014103186 B4 DE102014103186 B4 DE 102014103186B4 DE 102014103186 A DE102014103186 A DE 102014103186A DE 102014103186 B4 DE102014103186 B4 DE 102014103186B4
- Authority
- DE
- Germany
- Prior art keywords
- memory
- chip system
- output
- soc
- wide input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Memory System (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2013-0027658 | 2013-03-15 | ||
| KR1020130027658A KR102029682B1 (ko) | 2013-03-15 | 2013-03-15 | 반도체 장치 및 반도체 패키지 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE102014103186A1 DE102014103186A1 (de) | 2014-09-18 |
| DE102014103186B4 true DE102014103186B4 (de) | 2021-05-27 |
Family
ID=50792497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE102014103186.5A Active DE102014103186B4 (de) | 2013-03-15 | 2014-03-11 | Halbleitervorrichtung und Halbleiterpackage |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US9275688B2 (cg-RX-API-DMAC7.html) |
| JP (1) | JP2014182794A (cg-RX-API-DMAC7.html) |
| KR (1) | KR102029682B1 (cg-RX-API-DMAC7.html) |
| CN (1) | CN104051410B (cg-RX-API-DMAC7.html) |
| DE (1) | DE102014103186B4 (cg-RX-API-DMAC7.html) |
| IN (1) | IN2014DE00712A (cg-RX-API-DMAC7.html) |
| NL (1) | NL2012389B1 (cg-RX-API-DMAC7.html) |
| TW (1) | TWI606569B (cg-RX-API-DMAC7.html) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9324397B1 (en) * | 2015-01-16 | 2016-04-26 | Qualcomm Incorporated | Common die for supporting different external memory types with minimal packaging complexity |
| TWI561960B (en) * | 2015-11-05 | 2016-12-11 | Sunplus Technology Co Ltd | Clock providing system |
| KR102413441B1 (ko) | 2015-11-12 | 2022-06-28 | 삼성전자주식회사 | 반도체 패키지 |
| KR102468698B1 (ko) * | 2015-12-23 | 2022-11-22 | 에스케이하이닉스 주식회사 | 메모리 장치 |
| DE102016011750A1 (de) * | 2016-09-29 | 2018-03-29 | Ceramtec-Etec Gmbh | Datenträger aus Keramik |
| US11514996B2 (en) * | 2017-07-30 | 2022-11-29 | Neuroblade Ltd. | Memory-based processors |
| KR20190087893A (ko) * | 2018-01-17 | 2019-07-25 | 삼성전자주식회사 | 클럭을 공유하는 반도체 패키지 및 전자 시스템 |
| KR102836932B1 (ko) * | 2018-09-06 | 2025-07-22 | 뉴로블레이드, 리미티드. | 메모리 기반 프로세서 |
| WO2020240239A1 (en) * | 2019-05-31 | 2020-12-03 | Micron Technology, Inc. | Memory component for a system-on-chip device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080001305A1 (en) * | 2006-06-30 | 2008-01-03 | Fujitsu Limited | Semiconductor device and manufacturing method of same |
Family Cites Families (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5223454A (en) * | 1988-01-29 | 1993-06-29 | Hitachi, Ltd. | Method of manufacturing semiconductor integrated circuit device |
| US6809421B1 (en) * | 1996-12-02 | 2004-10-26 | Kabushiki Kaisha Toshiba | Multichip semiconductor device, chip therefor and method of formation thereof |
| US6724084B1 (en) * | 1999-02-08 | 2004-04-20 | Rohm Co., Ltd. | Semiconductor chip and production thereof, and semiconductor device having semiconductor chip bonded to solid device |
| US7173877B2 (en) * | 2004-09-30 | 2007-02-06 | Infineon Technologies Ag | Memory system with two clock lines and a memory device |
| EP1830363A4 (en) * | 2004-12-24 | 2008-10-08 | Spansion Llc | SYNCHRONIZATION TYPE STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME |
| US8059443B2 (en) | 2007-10-23 | 2011-11-15 | Hewlett-Packard Development Company, L.P. | Three-dimensional memory module architectures |
| US20100140750A1 (en) * | 2008-12-10 | 2010-06-10 | Qualcomm Incorporated | Parallel Plane Memory and Processor Coupling in a 3-D Micro-Architectural System |
| US20100174858A1 (en) | 2009-01-05 | 2010-07-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Extra high bandwidth memory die stack |
| US8207754B2 (en) | 2009-02-24 | 2012-06-26 | Stmicroelectronics International N.V. | Architecture for efficient usage of IO |
| US8174876B2 (en) * | 2009-06-19 | 2012-05-08 | Hynix Semiconductor Inc. | Fusion memory device embodied with phase change memory devices having different resistance distributions and data processing system using the same |
| US8227904B2 (en) | 2009-06-24 | 2012-07-24 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
| US8698321B2 (en) | 2009-10-07 | 2014-04-15 | Qualcomm Incorporated | Vertically stackable dies having chip identifier structures |
| US8612809B2 (en) | 2009-12-31 | 2013-12-17 | Intel Corporation | Systems, methods, and apparatuses for stacked memory |
| US8796863B2 (en) | 2010-02-09 | 2014-08-05 | Samsung Electronics Co., Ltd. | Semiconductor memory devices and semiconductor packages |
| KR20110099384A (ko) * | 2010-03-02 | 2011-09-08 | 삼성전자주식회사 | 와이드 입출력 반도체 메모리 장치 및 이를 포함하는 반도체 패키지 |
| US9123552B2 (en) * | 2010-03-30 | 2015-09-01 | Micron Technology, Inc. | Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same |
| KR101728067B1 (ko) | 2010-09-03 | 2017-04-18 | 삼성전자 주식회사 | 반도체 메모리 장치 |
| KR20120068216A (ko) | 2010-12-17 | 2012-06-27 | 에스케이하이닉스 주식회사 | 반도체 집적회로 |
| US8399961B2 (en) * | 2010-12-21 | 2013-03-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tuning the efficiency in the transmission of radio-frequency signals using micro-bumps |
| KR20120079397A (ko) * | 2011-01-04 | 2012-07-12 | 삼성전자주식회사 | 적층형 반도체 장치 및 이의 제조 방법 |
| US8564111B2 (en) * | 2011-01-27 | 2013-10-22 | Siano Mobile Silicon Ltd. | Stacked digital/RF system-on-chip with integral isolation layer |
| KR20120098096A (ko) | 2011-02-28 | 2012-09-05 | 에스케이하이닉스 주식회사 | 반도체 집적회로 |
| JP5286382B2 (ja) * | 2011-04-11 | 2013-09-11 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
| CN102891114B (zh) * | 2012-10-24 | 2015-01-28 | 上海新储集成电路有限公司 | 一种上下堆叠的片上系统芯片的制作方法 |
-
2013
- 2013-03-15 KR KR1020130027658A patent/KR102029682B1/ko not_active Expired - Fee Related
-
2014
- 2014-02-17 JP JP2014027928A patent/JP2014182794A/ja active Pending
- 2014-03-05 TW TW103107328A patent/TWI606569B/zh active
- 2014-03-10 NL NL2012389A patent/NL2012389B1/en active
- 2014-03-11 DE DE102014103186.5A patent/DE102014103186B4/de active Active
- 2014-03-12 CN CN201410089978.XA patent/CN104051410B/zh active Active
- 2014-03-12 IN IN712DE2014 patent/IN2014DE00712A/en unknown
- 2014-03-14 US US14/211,033 patent/US9275688B2/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080001305A1 (en) * | 2006-06-30 | 2008-01-03 | Fujitsu Limited | Semiconductor device and manufacturing method of same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104051410B (zh) | 2018-05-01 |
| JP2014182794A (ja) | 2014-09-29 |
| TWI606569B (zh) | 2017-11-21 |
| KR20140112944A (ko) | 2014-09-24 |
| KR102029682B1 (ko) | 2019-10-08 |
| IN2014DE00712A (cg-RX-API-DMAC7.html) | 2015-06-19 |
| TW201436165A (zh) | 2014-09-16 |
| US20140268979A1 (en) | 2014-09-18 |
| DE102014103186A1 (de) | 2014-09-18 |
| NL2012389B1 (en) | 2016-07-15 |
| CN104051410A (zh) | 2014-09-17 |
| US9275688B2 (en) | 2016-03-01 |
| NL2012389A (en) | 2014-09-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE102014103186B4 (de) | Halbleitervorrichtung und Halbleiterpackage | |
| DE112011105909B4 (de) | Speichergerät mit Speicherchiplagenschichten, Speicherchiplagenelement mit Kopplungsstrukturen und System umfassend Speicherstapel, Prozessor und Systemelement | |
| DE112011105905B4 (de) | Speichergerät mit gestapeltem Speicher, der Veränderlichkeit bei Zusammenschaltungen von Geräten erlaubt | |
| DE102015116760B4 (de) | Elektrodenkonfigurationen zum erhöhen der elektrothermischen isolation von phasenwechselspeicher-elementen und zugehörige techniken | |
| DE19639247B4 (de) | Halbleiteranordnung mit einem Verdrahtungssubstrat | |
| DE102011052959B4 (de) | Halbleiterspeichervorrichtung | |
| DE102008030205B4 (de) | Speichermatrix auf mehr als einem Die | |
| DE102020103364A1 (de) | Substrat-Patch-Rekonstitutionsoptionen | |
| DE102011087272A1 (de) | Halbleiterherstellungs- und -prüfverfahren, Prüfvorrichtung und Prüfsystem | |
| DE112013003173T5 (de) | Paketsubstrate mit mehreren Mikroplättchen | |
| DE102020133243A1 (de) | Skalierbare und interoperable phy-freie die-zu-die-ea-lösung | |
| DE112017001160B4 (de) | Elektronische Komponenten mit dreidimensionalen Kondensatoren in einem Metallisierungsstapel | |
| DE102014116417A1 (de) | Ein Paket integrierter Schaltungen mit eingebetteter Brücke | |
| DE112015006942T5 (de) | Beidseitige Metallisierung mit einer durch das Silizium verteilten Stromversorgung | |
| DE112008002459T5 (de) | Integrierte-Schaltkreis-Bausteine mit hoch-dichten bumpless bild-up layers und einem Substrat mit dichtevermindertem Kern oder einem kernlosen Substrat | |
| DE112015006975T5 (de) | Mikroelektronische Packung mit drahtloser Zwischenverbindung | |
| DE102020108217A1 (de) | Die-zu-Die-Verbindungsstruktur für modularisierte integrierte Schaltungsvorrichtungen | |
| DE102013202355B4 (de) | Halbleiterchip, verfahren zur herstellung eines halbleiterchips, bauelement und verfahren zur herstellung eines bauelements | |
| DE112019000902T5 (de) | Gehäuse für skalierbare phased-array-antennen | |
| DE112015007236B4 (de) | Vorrichtungen mit Hybridtechnologie-3D-Die-Stapeln und Herstellungsverfahren dafür | |
| DE102018112868B4 (de) | Monolitischer Siliziumbrückenstapel, umfassend einen hybriden Basisband-Prozessorchip, der Prozessoren und einen Speicher trägt und Verfahren zur Bildung eines monolithischen Chipstapels | |
| DE102014109520A1 (de) | Paketbaugruppen-konfigurationen für mehrfach-dies und dazugehörige techniken | |
| DE202017106568U1 (de) | Integriertes DRAM mit niedrigem I/O-Spannungshub | |
| DE112012002370T5 (de) | Mikroelektronisches Substrat für alternierende Package-Funktionalität | |
| DE102018129910A1 (de) | Konzept für einen gepufferten umgedrehten Spannungsfolger und für einen Spannungsregler mit niedrigem Dropout |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R083 | Amendment of/additions to inventor(s) | ||
| R012 | Request for examination validly filed | ||
| R016 | Response to examination communication | ||
| R018 | Grant decision by examination section/examining division | ||
| R020 | Patent grant now final | ||
| R079 | Amendment of ipc main class |
Free format text: PREVIOUS MAIN CLASS: H01L0025065000 Ipc: H10D0080300000 |