CN1812100A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN1812100A
CN1812100A CNA2005101296333A CN200510129633A CN1812100A CN 1812100 A CN1812100 A CN 1812100A CN A2005101296333 A CNA2005101296333 A CN A2005101296333A CN 200510129633 A CN200510129633 A CN 200510129633A CN 1812100 A CN1812100 A CN 1812100A
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salient point
semiconductor
qualified
semiconductor element
unit
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CN100433331C (zh
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油谷直毅
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

具有良好的特性且能提高信赖度，还可以使用SiC晶片。在SiC芯片(9)上形成多个肖特基势垒二极管的单元(10)，各单元(10)具有独立的外部输出电极(4)。形成在SiC芯片(9)上的单元(10)中，只在合格的单元的外部输出电极(4)上形成凸点(11)(直径为数十～数百μm)，没有耐压或漏电电流多的不合格的单元的外部输出电极(4)上不形成凸点。由于不合格的单元上不形成凸点，所以肖特基势垒侧电极(3)依次通过外部输出电极(4)、凸点(11)、布线基板(12)的布线层(13)、外部导线(13a)与外部并联连接，只并联连接合格的单元(10)的外部输出电极(4)。

Description

半导体器件及其制造方法
技术领域
本发明涉及设置了多个半导体元件单元、选择性地连接了合格的半导体元件单元的半导体器件及其制造方法。
背景技术
与使用硅的半导体器件相比，使用了SiC的半导体器件在高电压、大电流、高温运转方面具有优越性，所以人们致力于开发功率半导体器件方面的应用。但是，与硅晶片相比，难以制成缺陷较少的SiC晶片，难以得到需要大面积半导体元件的大电流容量的半导体器件。
因此，在SiC晶片内，在能够保证一定成品率的面积上，形成多个例如肖特基二极管等半导体元件单元(以下，简称为单元)，以由上述多个单元形成1个SiC芯片的方式进行切割。上述SiC芯片中设置了绝缘层，具有到达上述单元中肖特基势垒电极的开口，上述多个单元中的不合格的单元的肖特基势垒电极由涂抹的绝缘物绝缘，隔着上述绝缘层设置的金属层成为上述单元的外部输出电极及布线层，只并联连接合格的单元的肖特基势垒电极，即使在缺陷很多的SiC晶片中，也努力以高成品率得到大容量的半导体器件(如参照专利文献1)。
[专利文献1]
特开2004-111759号公报(第1页)
但是，并联连接上述SiC芯片中合格的单元的布线层，如果不形成数十μm以上的厚膜，电阻损失就会很大。另外，由于上述布线层还形成在单元间分离部的绝缘层上，所以为了保证高度耐压，必须形成数十μm以上的厚的绝缘层。
但是，由于SiC芯片上设置了上述厚膜的绝缘层和布线层，所以机械的和热的应力变大，上述SiC晶片的变形变大，难以制造半导体器件，而且半导体器件的信赖度降低。
一般在使用了硅晶片的半导体器件的制造中，从微细化方面考虑，已将制造装置优化，使其适于进行数μm以下的成膜和加工，所以难以像上述那样增加布线层和绝缘膜的厚度。
发明内容
本发明是为了解决上述问题而实施的，目的在于得到具有良好的特性、提高了信赖度的半导体器件，其目的还在于得到能够以高成品率容易得到上述半导体器件的半导体器件制造方法。
涉及本发明的第1半导体器件具有：形成在半导体芯片上的多个半导体元件单元；互相独立地形成在每个该半导体元件单元上的外部输出电极；在合格和不合格的半导体元件单元中、选择性地形成在合格的半导体元件单元的上述外部输出电极上的凸点；设置了与该凸点电连接的布线层的布线基板。
由于本发明的第1半导体器件具有：形成在半导体芯片上的多个半导体元件单元；互相独立地形成在每个该半导体元件单元上的外部输出电极；在合格和不合格的半导体元件单元中、选择性地形成在合格的半导体元件单元的上述外部输出电极上的凸点；设置了与该凸点电连接的布线层的布线基板。所以具有良好的特性，而且提高了信赖度。另外，由于使用了SiC晶片，所以具有良好的特性，而且提高了信赖度。
附图说明
[图1]是本发明实施方式1的半导体器件的剖面图。
[图2]是涉及本发明实施方式1的半导体器件的、SiC芯片的平面图和剖面图。
[图3]是涉及本发明实施方式1的半导体器件的、布线基板部件的平面图。
[图4]是表示涉及本发明实施方式2的半导体器件制造方法中、凸点形成工序的说明图。
[图5]是用于说明本发明实施方式2的半导体器件制造方法中、与布线层连接工序的立体图。
[图6]是涉及本发明实施方式3的半导体器件的制造方法的凸点形成工序说明图。
[图7]是涉及本发明实施方式4的半导体器件的制造方法的凸点形成工序说明图。
[图8]是涉及本发明实施方式5的半导体器件中、SiC芯片的平面图及与之连接的布线基板部件的平面图。
[图9]是用于说明涉及本发明实施方式5的半导体器件中、SiC芯片和布线基板部件的安装结构的立体图。
[图10]表示涉及本发明实施方式6的半导体器件中、形成在SiC芯片上的半导体元件单元上的凸点的设置状态的平面图。
[图11]是表示涉及本发明实施方式7的半导体器件中、形成在SiC芯片上的半导体元件单元上的凸点的设置状态的平面图。
[图12]是以往的半导体器件的剖面图。
具体实施方式
实施方式1
图1为本发明实施方式1的半导体器件的剖面图，在作为半导体芯片的SiC芯片9上，形成多个作为半导体元件单元的肖特基势垒二极管的单元10，各单元10具有独立的外部输出电极4。
形成在SiC芯片9上的单元10中只在合格的单元的外部输出电极4上形成例如由熔融金属(指Sn-Pb、Sn-Ag、Sn-Cu、Sn-Bi、Sn-Ag-Cu、Sn-Ag-Bi、Sn-Ag-Bi-Cu、Au-Sn等)构成的直径为数十～数百μm的凸点11，耐压不足或漏电电流很大的不合格的单元的外部输出电极4上不形成凸点。而且，由于不合格的单元上不形成凸点，所以肖特基势垒侧电极3依次通过外部输出电极4、凸点11、布线基板12的布线层13、外部导线13a与外部并联连接，只与合格的单元10的外部输出电极4并联连接。
布线基板12与SiC芯片9的间隙由填充树脂19填充，SiC芯片9由熔融金属糊剂构成的焊接材料18固定在封装基板16上。SiC芯片9的背面电极6的最表面为Au膜，以便与上述熔融金属融合，在封装基板16的布线层17上涂抹上述焊接材料18，并在上面安装SiC芯片9，加热到上述熔融金属的融化温度后冷却，于是上述熔融金属糊剂凝固，SiC芯片9被固定到封装基板16上，同时背面电极6与封装基板16的布线层17电连接。布线层17与外部导线17a连接，外部导线17a成为合格的单元10的肖特基势垒二极管元件的共同半导体侧电极的输出。
另外，图12为作为比较的以往的半导体器件的剖面图。即，芯片内分为多个单元10，芯片上设置了具有开口的绝缘层55，其开口到达上述单元10的肖特基势垒电极52、53。上述多个单元中，在不合格的单元的肖特基势垒电极52上涂抹绝缘物51绝缘后，隔着上述绝缘层55设置金属层54，作为单元10的外部输出电极及布线层，利用上述布线层只与合格的单元的肖特基势垒电极53并联连接。而且，上述金属层54还形成在单元10间的分离部的绝缘层55上。
涉及图1所示的本实施方式的半导体器件的SiC芯片9由以下方式得到。
即，在n+型SiC晶片1a上生长n型SiC外延层2作为半导体晶片，然后形成数百nm的Ti或Ni等金属膜并进行加工，形成多个肖特基势垒电极3，在上述SiC晶片1a上形成多个单元10。例如通过在上述肖特基势垒电极3上形成1μm左右的Al膜并加工，形成外部输出电极4。为了与凸点的熔融金属容易融合而在外部输出电极的最表面涂抹Au膜时，还形成Cr-Ni-Au等膜。
接着，形成例如数μm左右的聚亚胺膜，作为一部分外部输出电极4开口后的保护膜5，n+型SiC晶片1a的背面例如形成镍和金膜，作为背面电极6。
然后，上述外部输出电极4作为单元10的金属侧输出电极，背面电极6作为半导体侧输出电极，按下述方式判断SiC晶片内的单元10是否合格，只在合格的单元的外部输出电极4上形成凸点，得到SiC晶片部件，并分割加工，作为具有多个单元10的SiC芯片9。
使用图2说明为了得到规定成品率的SiC晶片而设置单元的方法。图2(a)为涉及本实施方式的半导体器件SiC芯片9的平面图，图2(b)为图2(a)中的A-A′线的剖面图，为了简化，表示设置了4×4个单元10的例子。
制造如具有100A电流容量的半导体器件时，由于对于SiC芯片9的肖特基势垒电极3的面积，电流容量为3A/mm2左右，所以必需约6mm见方的面积的肖特基势垒电极。例如，SiC晶片的缺陷密度小于等于10个/cm2时，上述面积中只能得到小于等于5％的成品率，难以实现量产化。因此，本实施方式中，将各单元10的肖特基势垒电极3的面积设定为能够得到足够成品率的大小。例如，缺陷密度为10个/cm2左右时，将单元10的肖特基势垒电极3的面积设定为1mm见方，能够得到大于等于80％的成品率，将多个该单元10设置在SiC芯片9上时，能够以大于等于80％的确率得到合格的单元。
因此，如图2(a)所示，设置4×4个单元10的情况下，当成品率为80％时，会有3个左右的不合格的单元。涉及本实施方式的SiC芯片9中，只在合格的单元的外部输出电极4上形成由熔融金属构成、直径为数十～数百μm大小的凸点11，图2中没有凸点11的单元为不合格的单元。
图3为涉及本实施方式的半导体器件的、由设置了布线层的布线基板构成的布线基板部件的平面图，与形成图2所示的形成了凸点11的SiC芯片9连接，成为半导体器件。
图3(a)表示，在如陶瓷或树脂构成的布线基板12表面，至少与SiC晶片9中形成凸点11的区域对应地形成布线层13的情况，上述布线层13与外部导线13a连接。由于布线层13与外部输出电极4通过凸点11电连接，所以只并联连接了形成凸点11的合格的单元的电极。
另外，由于单元10的排列间隔在1mm以上，所以使用了硅晶片的半导体器件的制造，在安装到硅芯片的布线基板上的工序中，使用了优化的制造装置，以便形成宽数百μm～数mm、厚数十～数百μm的图案，因此，使用上述制造装置和形成技术，能够容易制成涉及本实施方式的布线基板12的布线层13的图案，布线层13的膜厚也能够容易地形成为数十～数百μm的厚度，能够实现电阻小的布线。
而且，本实施方式中的单元10为肖特基势垒二极管，由于SiC芯片9表面的输出只有一种，所以布线层13如图3(b)所示，可以是形成在布线基板12的整个表面的单一图案，能够简化布线基板12的制造工序。
如上所述，本实施方式的半导体器件中，由于使用SiC晶片作为半导体晶片，所以在高电压、大电流、高温动作方面具有优势，可以作为功率半导体器件。
另外，本实施方式的半导体器件，能够通过连接SiC芯片9与图3所示的布线基板部件得到，如上所述，将设置在SiC晶片上的单元设定为能够确保规定成品率的面积，只在合格的单元的电极上形成凸点11，使用该凸点11，将上述合格的单元的外部电极并联连接在设置在与SiC芯片9不同的布线基板12上的布线层13上，所以能够以高成品率得到良好的特性的半导体器件。而且，由于由凸点11连接，SiC芯片9中产生的热不仅会扩散到封装侧，而且会扩散布线基板侧，所以能够在高温和高电流下运转。
另外，如图12所示，由于布线层54和绝缘膜层51直接形成在SiC芯片上，所以能够防止由于由膜厚导致的应力而引起的SiC晶片的变形和膜应力的发生，所以能够提高半导体器件的信赖度，由于不需要上述成膜工序，所以制造工序简便，成本降低。另外，由于通过凸点11与布线基板12连接，能够同时与外部导线连接，所以安装工序变简便，成本降低。
布线层13过于接近SiC芯片9时，例如会在单元10间分离部上放电或者影响分离耐压，但由凸点11连接，布线层13与SiC芯片9只相隔凸点11大小的距离(大小为凸点11的直径，为数十～数百μm)，所以与使用图12所示的以往的半导体器件相比，容易实现很高的耐压性。另外，在上述以往的半导体器件中，通过在单元间分离部的绝缘层55上形成金属层54，能够防止单元10的耐压降低。
图12所示的以往的半导体器件中，绝缘层55使用由CVD(Chemical Vapor Deposition)法形成的、厚度为1μm左右的PSG(Phosphosilicate Glass)膜等的氧化膜，但是由于PSG膜的绝缘破坏耐压为2～6MV/cm左右，无法实现耐压为200～600V、额定电压为Kv台的半导体器件。要制造5Kv耐压的半导体器件，绝缘层必须有8～25μm的厚度，难以成膜。
另外，本实施方式中，例如凸点11为100μm时，布线层13和SiC芯片9相隔100μm，所以保护膜5和填充树脂19的绝缘破坏耐压低估为1MV/cm左右也能够确保10kV的耐压，本实施方式的半导体器件能够具有以往的10～100倍的额定电压。
一般来说，功率半导体器件的布线层的电阻必须充分小于ON电阻，最好小于等于5mΩ。图12所示的以往的半导体器件中的金属层，由于使用了硅晶片的半导体器件的制造装置被优化，适于形成数μm以下的膜，所以通常使用数μm以下的厚度的铝系布线材料。即使使用布线的长宽比为10∶1、厚度为对利用硅晶片的半导体器件的制造装置来说有些厚的3μm厚的铝布线时，铝布线的电阻为3μΩcm左右，所以布线电阻为100mΩ，要想使电阻小于等于5mΩ，则需要60μm的厚膜，所以难以成膜。
但是，在本实施方式中，布线基板12的布线层13形成在与SiC芯片9不同的布线基板12上，所以能够使用将硅芯片安装到布线基板上的制造工序。因此，本实施方式的半导体器件的制造中，可以使用适于形成宽数百μm～数mm、厚数十～数百μm的图案被优化的装置，而且布线层中能够使用铜。铜布线比铝布线电阻低，为1.8μΩcm左右，所以布线的长宽比为10∶1时，要想获得5mΩ以下的电阻需要36μm厚度的铜布线，但如上所述，能够容易实现该厚度，而且还容易实现大于等于数百μm的布线层厚度。这时，可以将布线电阻设置为0.5mΩ以下，即使布线的长宽比为100∶1，电阻也小于等于5mΩ，所以能够并联连接更多的单元。如上所述，由于本实施方式的半导体器件使用布线电阻低的铜布线，能够得到足够厚度的布线，所以电流容量可以是以往的20～200倍。
实施方式2
图4为表示本发明实施方式2的半导体器件的制造方法中、在作为半导体晶片的SiC晶片1a上形成凸点的工序的说明图。将判断形成在SiC晶片1a上的单元10是否合格的晶片测试(以下简称为晶片测试)的数据输送到滴焊装置的控制器21那种，在滴焊装置中，选择性地只在合格的单元的外部输出电极4上形成熔融金属构成的凸点11。
即，使用晶片测试器20进行晶片测试，用SiC晶片1a的背面电极6与晶片测试器20的载物台(未图示)连接，用探针等与各单元10的外部输出电极4电连接后，检测单元10是否合格[图4(a)]。
接着，使用使熔融金属下滴的装置(以下称为“滴焊装置”)形成凸点11，滴焊装置与油墨喷射印刷装置动作一样，只是将熔融金属的液滴代替油墨滴在晶片规定位置上，根据晶片测试器20的晶片测试数据，由滴焊装置形成凸点11。
即，在设置在上述滴焊装置头部22中的熔融金属槽上的压电元件上，根据上述晶片测试数据施加来自控制器21的脉冲，头部22的喷嘴23将熔融金属的液滴滴在合格的单元10的外部输出电极4上。上述液滴的直径由脉冲信号和喷嘴直径决定，能够形成数十～数百μm的颗粒，通过与头部22相隔数mm设置SiC晶片1a、滴下上述熔融金属的颗粒，在SiC晶片1a上形成熔融金属的凸点。
即，与油墨喷射印刷机印刷一样，由控制器21将头部22移动到SiC晶片1a的凸点形成位置上，在压电元件上施加脉冲，滴下上述液滴，就能在所期望的位置上形成凸点11[图4(b)]。这时，由于形成凸点的外部输出电极形成薄的Au膜等易与熔融金属融合，所以外部输出电极为Al时，有时会形成如Cr-Ni-Au等的膜。凸点11的形状由SiC晶片1a的温度决定，如在室温下，熔融金属的液滴与SiC晶片1a接触后立刻凝固，形成球状和半球状的凸点。另外，升高SiC晶片1a的温度，接近熔融金属的融化温度时，上述金属能够扩散到单元的整个外部输出电极上。由于能够在同一个位置上滴下多个熔融金属的液滴，所以对外部输出电极的面积滴下足量的熔融金属颗粒就能够形成扩散到整个外部输出电极的丘状凸点。
如本实施方式所示，使用晶片测试数据，使用能够在合格的单元的电极上形成凸点的滴焊装置等装置时，就不需要凸点材料的成膜和加工，所以工序简化，能够削减成本。
如上所述，通过只在合格的单元的外部输出电极4上形成凸点，得到SiC晶片部件，并分割为具有多个单元10的SiC芯片9，如图5所示，在SiC芯片9上的凸点11上放置设置在布线基板12上的布线层13后加热冷却，融化凸点11，与布线层13连接。图5为用于说明本实施方式的半导体器件的制造方法中的、布线层的连接工序的立体图。
而且，如图1所示，填充树脂19用于固定SiC芯片9，提高凸点接合部的信赖度，但也可以在凸点11接合后注入到SiC芯片9与布线基板12间，或者在接合前涂抹在芯片上。
另外，将SiC芯片9固定在封装基板16上时，为了防止加热温度过高或者时间过长时凸点11融化，凸点11使用熔点比焊接材料18的金属高的金属。
另外，可以使背面电极6与封装基板16的布线层17连接的熔融金属的焊接材料18不完全凝固，暂时固定，将布线基板12放在SiC芯片9上加热后使凸点11与布线层13连接时，使背面的熔融金属糊剂的焊接材料18凝固。另外，可以将保护膜5的外部输出电极4开口部的大小设置为最终的凸点的大小，即使熔融金属熔化，也会受到开口部的限制。例如，设置直径为100μm的开口，放上直径为80μm左右的熔融金属的颗粒后，背面的熔融金属糊剂的焊接材料18凝固时，外部输出电极4上的熔融金属颗粒也融化，在开口部形成半球状的凸点。另外，SiC芯片9的固定可以使用导电性的焊接材料(如在树脂粘着剂中混入银填充料等导电性填充料的导电性粘着剂)。
实施方式3
本发明实施方式3的半导体器件的制造方法，除了用球焊机代替滴焊装置形成凸点以外，其他与实施方式2的半导体器件制造方法一样，图6说明涉及本实施方式的半导体器件制造方法的凸点形成工序。
例如，用金的球焊机形成金凸点34的工序中，根据晶片测试器20的晶片测试数据，利用控制器31进行控制，用毛细管33将金丝32只压在合格的单元的外部输出电极4上并使之接合，之后切断电线32形成金凸点34。
这时，将SiC晶片1a加热到如100℃左右，除了毛细管加压，有时还施加超声波。
由此，根据晶片测试数据选择性地只在合格的单元上形成凸点，由于不需要凸点材料的成膜和加工，所以工序简化，能够降低成品。
实施方式4
本发明实施方式4的半导体器件的制造方法，除了使用照相制版技术代替滴焊装置在SiC晶片的合格的单元电极上选择性地形成凸点外，其他与实施方式2的半导体器件制造方法一样，图7说明涉及实施方式4的半导体器件制造方法的凸点形成工序。
涉及本实施方式的半导体器件制造方法的凸点形成工序中，可以将滴焊装置中具有熔融金属槽的头部换成曝光头部42。曝光头部42可以照射直径为数十～数百μm的点光，其结构是例如由光纤将光从卤素灯等紫外线灯光源导入到曝光头部42，在光纤出口处设置快门43，能够控制曝光的ON/OFF。
在上述晶片测试后的SiC晶片1a上涂抹光刻胶等的光敏性树脂44，根据晶片测试数据，当曝光头部42在合格的单元的外部输出电极4上时，由控制器41依次输出快门43的ON信号，使合格的单元上的光敏性树脂44感光，得到感光部47[图7(a)]。
使用正型光刻胶作为光敏性树脂44时，显影后感光部47开口，在只有合格的单元的外部输出电极4开口的光敏性树脂44上，利用蒸镀等方法形成熔融金属膜45[图7(b)]。然后用有机溶剂等除去光敏性树脂44，能够只在合格的单元的外部输出电极4上形成凸点46[图7(c)]。
在照像制版技术中，使用掩模使光敏性光刻胶曝光显影，将掩模图案转印到上述光刻胶上时，对应晶片测试结果制成掩模，但由于每个晶片的合格的单元的分布不同，所以要按照每个晶片制造掩模，不实用。使用电子束等的直接描画装置，容易根据晶片测试结果改变每个晶片的曝光图案，但由于造价高，运转成本增大。
但是，在本实施方式中，由于必需的凸点直径为数十～数百μm，所以不需要上述使用了掩模的照相制版技术和直接描画装置那样的析像度，如本实施方式，通过改造滴焊装置，能够形成凸点，所以设备投资少。
实施方式5
本发明实施方式5的半导体器件除了半导体元件单元10不是作为SiC肖特基势垒二极管的功率元件而是SiC纵型MOSFET半导体元件以外，其他与实施方式1一样。
图8(a)为涉及本发明的实施方式5的半导体器件的SiC芯片9的平面图，表示与实施方式1一样的、设置了4×4个SiC纵型MOSFET半导体元件的单元10的例子。即，纵型MOSFET时，SiC芯片9表面侧具有栅电极的外部输出电极7和源电极的外部输出电极8，漏极电极从SiC芯片9的背面电极输出。只在合格的单元的栅电极的外部输出电极7和源电极的外部输出电极8上形成凸点11，图8(a)中没有凸点11的单元为不合格的单元。
图8(b)为与图8(a)的SiC芯片9连接的布线基板部件的平面图，在如陶瓷或树脂构成的布线基板12表面，与SiC芯片9的源电极的外部输出电极8上的凸点11的排列间隔对应，形成梳齿状的布线层14，布线层14与外部导线14a连接，而且与SiC芯片9的栅电极的外部输出电极7上的凸点11的排列间隔对应，形成梳齿状布线层15。
布线层15与外部导线15a连接，布线层15的排列间隔与单元的排列间隔一样，大于等于1mm，所以一般在使用了硅晶片的半导体器件的制造中，向硅芯片的布线基板的安装工序中，使用适于形成宽数百μm～数mm、厚数十～数百μm的图案的被优化的装置，所以在上述制造装置和形成技术中，容易形成数十～数百μm厚的布线层14、15，而且，外部导线14a、15a也能够一体地形成。通过将布线基板12重叠在SiC芯片9上，使布线层14、15与凸点11电连接，分别使外部导线14a、15a和单元10的源电极与栅电极电连接。
图9为用于说明涉及本实施方式的半导体器件的、SiC芯片9与布线基板部件的安装结构的立体图，将SiC芯片9固定在封装基板16的表面，同时形成与背面电极电连接的布线层17。布线层17与外部导线17a连接。单元的漏极电极依次通过芯片9的背面电极、封装基板16的布线层17、外部导线17a与外部连接，源电极依次通过凸点11、布线基板12的布线层14、外部导线14a与外部连接，栅电极依次通过凸点11、布线板13的布线层15、外部导线15a与外部连接。由于不合格的单元上不形成凸点11，所以只有合格的单元的源电极与栅电极并联连接。
本实施方式的半导体器件，能够得到与实施方式1的半导体器件同样的效果，特别是，由于使用电阻低的铜布线形成足够厚度的布线层14、15，所以容易降低布线电阻，电流容量能够是以往的20～200倍，而且还可以得到下述效果。
即，涉及本实施方式的SiC纵型MOSFET半导体元件，如图8和图9所示，由于源电极的外部输出电极7与栅电极的外部输出电极8分开并联连接，所以需要与源电极的外部输出电极7和栅电极的外部输出电极8对应地分离设置的布线层14、15，由于长度比布线层的宽度长，所以如上所述，降低布线电阻的效果更加显著。
实施方式6
本发明实施方式6的半导体器件除了凸点的设置状态为图10所示的状态以外，其他与实施方式1或实施方式5一样。图10为表示涉及本发明实施方式6的半导体器件地、形成在SiC芯片9上的单元上的凸点的设置状态的平面图。
图10(a)表示单元10与肖特基势垒二极管元件一样，表面上具有一种外部输出电极4的情况，图10(b)表示单元10与SiC纵型MOSFET半导体元件一样，表面上具有两种外部输出电极7、8的情况，上述实施方式1～5中，各单元的外部输出电极上各设置了1个凸点，与之相对，本实施方式设置了多个凸点。在外部输出电极4上形成多个凸点11，通过由多个凸点连接，能够降低连接电阻，缓和凸点连接部的应力。另外，如图10(b)所示，SiC纵型MOSFET半导体元件中，与不流通电流的栅电极的外部输出电极7的凸点数量相比，增加流通电流的源电极的外部输出电极的凸点数量，也能够降低连接电阻。
实施方式7
本发明实施方式7的半导体器件除了凸点的设置状态为图11所示的状态以外，其他与实施方式1或实施方式5一样。图11为表示涉及本发明实施方式6的半导体器件的、形成在SiC芯片9上的单元上的凸点的设置状态的平面图。
图11(a)表示单元10与肖特基势垒二极管元件一样，表面上具有一种外部输出电极4的情况，图11(b)表示单元10与SiC纵型MOSFET半导体元件一样，表面上具有两种外部输出电极7、8的情况，在上述实施方式1～6中，只在合格的单元的外部输出电极上形成凸点，与之相对，本实施方式中在SiC芯片中外部输出电极4以外的区域也形成虚设的凸点11a，其不以连接单元的外部输出电极和布线层为目的。这时，虚设凸点11a能够使在SiC芯片上产生的热量高效地扩散到布线基板侧，而且通过虚设凸点11a的排列，还能够缓和连接用凸点11的应力。
由于虚设凸点11a不与单元的外部输出电极电连接，所以只要与布线层14、15连接就可以。另外，可以在面对布线基板上的虚设凸点11a的位置上，设置与布线层14、15电分离的电极焊盘，与虚设凸点11a连接。
另外，在上述中，在单元间设置虚设凸点，但也可以设置在单元阵列的外侧(芯片的周边部)。

Claims (8)

1.一种半导体器件，具有：
形成在半导体芯片上的多个半导体元件单元；
互相独立地形成在每个该半导体元件单元上的外部输出电极；
在合格和不合格的半导体元件单元中、选择性地形成在合格的半导体元件单元的上述外部输出电极上的凸点；以及
设置有与该凸点电连接的布线层的布线基板。
2.根据权利要求1所述的半导体器件，其特征在于：半导体元件单元为使用了SiC晶片的肖特基二极管或者使用了SiC晶片的MOSFET半导体元件。
3.根据权利要求1或2所述的半导体器件，其特征在于：具有用于使半导体芯片的外部输出电极之外的区域与布线基板接合的凸点。
4.一种半导体器件的制造方法，包括：
在半导体晶片上形成多个半导体元件单元的工序；
判断上述半导体元件单元是否合格的工序；
在合格和不合格的半导体元件单元中，选择性地在合格的半导体元件单元的外部输出电极上形成凸点，以得到半导体晶片部件的工序；
分割加工上述半导体晶片部件，以得到具有多个半导体元件单元的半导体芯片的工序；以及
使设置在布线基板上的布线层与上述凸点电连接的工序。
5.根据权利要求4所述的半导体器件的制造方法，其特征在于：半导体元件单元为使用了SiC晶片的肖特基二极管或者使用了SiC晶片的MOSFET半导体元件。
6.根据权利要求4或5所述的半导体器件的制造方法，其特征在于，形成凸点的工序如下：根据判断合格和不合格的半导体元件单元的测试结果，在合格的半导体元件单元的外部输出电极上选择性地滴下熔融金属，形成凸点。
7.根据权利要求4或5所述的半导体器件的制造方法，其特征在于，形成凸点的工序如下：
根据判断合格和不合格的半导体元件单元的测试结果，用突点焊机选择性地在合格的半导体元件单元的外部输出电极上形成凸点。
8.根据权利要求4或5所述的半导体器件的制造方法，其特征在于，形成凸点的工序如下：
根据判断合格和不合格的半导体元件单元的测试结果，在设置在半导体晶片上的光敏性树脂层中，选择性地依次使上述光敏性树脂层曝光，以便在合格的半导体元件单元的外部输出电极上形成开口，在上述开口上形成凸点，从而在合格的半导体元件单元的外部输出电极上选择性地形成凸点。
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US7880763B2 (en) 2011-02-01
CN100433331C (zh) 2008-11-12
US20060131745A1 (en) 2006-06-22
US20090004761A1 (en) 2009-01-01
DE102005059224A1 (de) 2006-06-29
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US8178972B2 (en) 2012-05-15
JP2006173250A (ja) 2006-06-29

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