CN1779986A - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
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- CN1779986A CN1779986A CNA2005101163172A CN200510116317A CN1779986A CN 1779986 A CN1779986 A CN 1779986A CN A2005101163172 A CNA2005101163172 A CN A2005101163172A CN 200510116317 A CN200510116317 A CN 200510116317A CN 1779986 A CN1779986 A CN 1779986A
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- China
- Prior art keywords
- region
- metal
- channel region
- transistor
- lateral junction
- Prior art date
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- Granted
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Abstract
本发明涉及半导体器件。它包括半导体岛、第一和第二杂质区、沟道区、栅电极、物质添加区。其中,晶体生长由物质添加区一直延伸至第一和第二杂质区的部分才终止。它还包括至少一种导线。半导体岛包含绝缘表面上形成的结晶硅,含0.01-5原子%的氢。杂质区可以是一对n-型或P-型杂质区。沟道区没有晶粒间界。
Description
本申请是分案申请,原申请的申请日为1994年2月15日,申请号为99118536.6,发明名称为“半导体器件”。
本发明涉及一种用于薄膜器件,例如薄膜绝缘栅型场效应晶体管(薄膜晶体管或TFT)的晶态半导体薄膜器件。
通常,采用使由等离子CVD方法或热CVD方法形成的非晶硅薄膜在如电炉设备中,在高于600℃温度下结晶化来制造用于像薄膜绝缘栅型场效应晶体管(TFT)薄膜器件的晶态半导体薄膜。
然而,这种常规方法存在许多问题。最大的问题是极难获得好的产品。这是因为所获得的晶态硅膜是多晶的,并且晶粒间界的控制也存在困难,且其可靠性和产量亦不高,这是由于其分散(dispersion)特性所造成的。这就是说,由于用常规热处理获得的硅晶体,完全是在无定向的情况下生长的,因此要控制晶体生长的方向几乎是不可能的。
因此,本发明的目的是提供一种控制晶体生长的方法,以解决上述存在的问题。
按照本发明,控制晶体生长,且获得具有高可靠性和高产量的TFT是通过在非晶态或实质上可以说是非晶态的不规则的晶态(例如部分为晶性,部分为非晶性的混合态)中的硅薄膜上形成栅电极,用栅电极作掩模,在硅薄膜内形成掺杂区域,形成至少包括镍、铁、钴、铂或钯中一种的区域,以便他们粘着在掺杂区域部分上,并且使该整体进行退火,以便从包括镍的区域开始使它结晶化。
特别是,本发明允许实际上消除在源和漏与有源层之间的晶粒间界,并且通过在有源层结晶化(沟道形成区域)的同时推进源和漏的结晶化来获得好的特性。
以一个作为晶核或作为籽晶的结晶岛薄膜为中心固相外延生长,硅薄膜晶体的方法已作为现有技术的方法提出(例如,日本专利公开NO.1-214110,等)。然而,即使存在晶核抑制晶体从其它位置生长是困难的。即,因为用于晶体生长的热处理(退火,下同)温度是适合于晶核充分产生的温度,所以晶体经常是从不企望的位置开始生长。
本发明的发明人发现镍、钴、铁、铂和钯是容易与硅结合的,并且以他们为中心生长晶体,发明人注意到镍容易形成硅化镍(NiSiX,0.4≤x≤2.5),且硅化镍的晶格常数与硅晶体的晶格常数接近,于是发明了以硅化镍为中心生长硅晶体的方法。实际上,该晶体生长温度能比常规方法降低20℃到150℃。因为在该温度下,在纯硅薄膜中不产生晶核,故晶体不会从不企望的位置生长,假定晶体的生长是采用与常规方法相同的机理从晶核开始,并且在晶核不会自然生长的温度(最好低于580℃)下温度越高,晶化进行的速度越快,采用铁(Fe),钴(Co),铂(Pt)和钯(Pd)也有同样的效果。
按照本发明,将一包含镍,铁,钴,铂或钯或它们的硅化物,醋酸盐,硝酸盐和其它有机酸盐单一物质的薄膜或类似物粘结到薄膜晶体管的掺杂区域并且该晶体硅区域从作为起始点薄膜扩展开来。另外,氧化物作为包含上述材料的材料是不可取的,因为氧化物是一种稳定的化合物,并且从这里不会产生很可能变成晶核的硅化物。
因此从特定位置扩展的晶体硅具有与良好的连续结晶性单晶体相近的结构。用具有少量氢浓度的非晶硅膜作为结晶化的起始材料,能获得更好的结果。然而,因为进行结晶化时释放出氢,在获得的硅薄膜中的氢浓度和作为起始材料的非晶硅膜的氢浓度之间看不出有明显的关系。在本发明的晶体硅中,氢浓度一般大于1×1015原子·厘米-3(atoms·cm-3)0.01原子%和小于5原子%。
当像镍、铁、钴或铂或钯中的一种重金属材料用到本发明中时,这些材料本身不适合于作为半导体材料的硅,假如这些元素含量过多,则必须将他们除去。发明人从进行的研究的一个结果中发现在400-650℃下,在氯化氢,各种氯化甲烷(CH3Cl等),各种氯化乙烷(C2H3Cl3等)和各种氯化乙烯(C2HCl3等)的气氛中进行热处理,能够完全除去镍。还发现本发明的硅膜中,镍、铁、钴、铂或钯的浓度最好选择在1×1015cm-3到1原子%,或镍、铁、钴、铂和钯的最小浓度最好选择在1×1015cm-3到1×1019cm-3,采用SIMS测量值。在浓度低于该范围时,结晶化进行得不充分,反之,当浓度超过该范围时,其特性和可靠性则下降。
可以采用各种物理和化学方法来形成镍、铁、钴、铂或钯膜。例如,它们是需要真空设备的那些方法,像真空沉积方法,溅射方法和CVD方法,以及可以在大气中完成的一些方法,像旋转涂覆法,浸渍法(涂布法(application method)),刮刀法,丝网印刷法和喷射热分解法。
虽然旋转涂覆法和浸渍法不需要特殊设备,但他们生产的薄膜具有均匀的薄膜厚度和精确控制的浓度。作为用于这些方法中的溶液,不论是镍、铁、钴、铂或钯的醋酸盐,硝酸盐或各种羧酸盐或其它有机酸盐溶解或分散在水、各种乙醇(低和商品位)和石油(饱和的碳氢化合物或不饱和的碳氢化合物)中都可以采用。
然而,在此情况下,含在这些盐中的氧和碳有可能扩散到硅膜中,从而降低半导体的特性。但是,通过热平衡方法和差示热分析提出的研究结果证明他们在低于450℃温度下,被分解成适当的材料的氧化物或单质,并且在此后,它们并不扩散到硅膜中。当醋酸盐和硝酸盐这类低级物质在还原气氛如氮的气氛中被加热时,它们在低于400℃下分解,并且变成单金属体。同样,当它们在氧气中被加热时,一开始就产生氧化物,并且在较高温度下,放出氧后变成金属单质。
上述方法和本发明达到的其它目的将从说明书,权利要求书和附图中变的更明显。
图1(A)-1(C)是表示本发明一个实施例工艺剖面图(指的是第一实施例);
图2(A)-2(D)是表示本发明一个实施例工艺剖面图(指的是第二实施例);
图3(A)-3(D)是表示本发明一个实施例工艺的剖面图(指的是第三实施例);
图4(A)-4(D)是表示本发明的一个实施例的工艺剖面图(指的是第四实施例);
图5是表示在晶体硅中镍浓度的曲线图(指第四实施例)。
参照本发明的附图,对最佳实施例进行说明。
[第一实施例]
用等离子CVD方法,在基片(Corning 7059)10上形成2000埃(angstroms)厚度的底材氧化硅薄膜11,接着用等离子CVD或真空CVD方法制成厚度为200-3000埃或最好为500-1500埃的非晶硅膜。通过在350℃到450℃下热处理0.1-2小时,使之脱氢,使氢在薄膜中的浓度降低到低于5原子%,很容易使非晶硅膜结晶化。然后被构图以形成岛形硅区域12。接着用RF等离子CVD,ECR等离子CVD或溅射方法形成厚度为500-1500埃起栅绝缘薄膜作用的氧化硅膜13。当采用等离子体CVD法时,用TEOS(四乙氧硅烷)和氧作为原始气体能获得合适的结果。然后,用溅散方法淀积含1%硅的钽膜(厚度为5000埃),并且构图以形成栅布线和电极14。钛,硅,铬或铝可作为栅电极材料。
于是,将基片浸泡在3%酒石酸的乙酸乙二醇溶液中并放置在有电流流通的铂阴极和钽丝阳极之间进行阳极氧化,所施加的电流是这样的,即其电压以2v/min提升,当达到220V时,电流变为恒定值。当降到低于10微安/米2时,电流截止。结果,形成一个厚度为2000埃的阳极氧化物15(氧化钽)。当用钛、铝或硅作为栅电极时,同样能获得作为阳极氧化物的氧化钛、氧化铝或氧化硅(图1(A))。
接着,通过等离子掺杂方法引入杂质。至于掺杂气体,对N型TFT采用磷化氢(PH3),对P型TFT采用乙硼烷(B2H6)。图中所示为N型TFT。对磷化氢的加速电压为80KeV,而对乙硼烷为65KeV。由此形成掺杂区16A和16B。此时,由图看出这些掺杂区和栅电极是不重合的。随后在掺杂区上氧化硅膜13上建立孔,以形成硅化镍(或镍)膜17A和17B,以使他们通过孔粘结到半导体区12,然后在550℃的氮气中进行四小时的热处理,以使掺杂区16和其它半导体区结晶化(图1(B))。
最后,在采用与制造常规TFT的方法同样方式沉积厚度为5000埃的氧化硅薄膜作为层间绝缘层18,同时形成穿通层间绝缘层的接触孔,以便在源区和漏区域上形成布线和电极19A和19B。铝、钛、氮化钛或由他们组成的多层膜适合作为布线和电极材料。在本实施例(图1(C))中,采用了氮化钛(厚1000埃)和铝(厚5000埃)的多层薄膜。
通过上述工艺制成TFT(图为N沟道型)。所获得的TFT的场效应迁移率(mobility)在N沟道型中是40-60cm2/Vs,在P沟道型中是30-50cm2/Vs。另外,甚至在栅和漏之间施加48小时的17至25V的电压,仍能获得几乎不变的阈值电压,场效应迁移率和亚阈值特性以及高可靠性。这是由于源、漏和沟道形成区域(在栅电极下的半导体区域)同时被结晶化,并且它们的结晶化方向是相同的。
[第二实施例]
用等离子体CVD方法在基片(Corning 7059)20上形成厚度为2000埃的底材氧化硅膜21。接着用等离子体CVD或真空CVD方法制成厚度为200至3000埃或最佳为500至1500埃的非晶硅膜。通过在350℃至450℃热处理0.1-2小时,使之脱氢降低氢在薄膜中的浓度,使之低于5原子%,能容易的形成非晶硅膜。然后,构图以形成岛形硅区域23。随后用RF等离子CVD,ECR等离子CVD或溅射方法形成厚度为500至1500埃,作为栅绝缘膜的氧化硅膜24。当采用等离子CVD方法时,使用TEOS(四乙氧硅烷)和氧作为原始气体能获得满意的结果。接着用LPCVD方法沉积含1%-5%磷的多晶硅膜(厚度为5000埃),并构图以形成栅布线和电极25A和25B(图2(A))。
在这之后,用离子掺杂方法使杂质向该处扩散,以形成N型掺杂区26A和P型杂质区26B。此时,磷(掺杂气体为磷化氢PH3)能被用作N型杂质,用60-110KV或例如80KV加速电压使整个表面掺杂,此后在40-80KV例如65KV的加速电压下,硼(掺杂气是乙硼烷B2H6)能作为P型掺杂的杂质,例如,用光刻胶覆盖N沟道型TFT区域。
接着,在杂质区上的氧化硅薄膜24中开一些孔,以形成厚度为200-1000埃或例如300埃的硅化镍(或镍)薄膜27A和27B,从而使他们通过孔粘结到杂质区26。然后,在550℃的氮气中进行四小时热处理,以使杂质区26和其它半导体区结晶化。此时,晶体的生长从岛形半导体区域两端部同时推进,并围绕其中央完成。因此,在沟道形成区域不产生颗粒间界,而且对TFT(图2(B))的特性也没有不利的影响。
另外,硅化镍膜27C可设于岛形半导体区域的中央,如图2(C)所示。在这种情况下,结晶化是从中心推进的(图2(C))。
最后,采用与制造常规TFT方法相同的措施,沉积厚度为5000埃的氧化硅膜作为层间绝缘体28,并通过层间绝缘体建立接触孔,以形成源区和漏区域上的布线和电极29A,29B和29C。铝、钛、氮化钛或它们的多层膜作为布线和电极材料是合适的。在这种情况下,采用的是氮化钛(1000埃厚)和铝(5000埃厚)的多层膜。
用上述工艺制成CMOS型TFT。然后用如此制成的CMOS电路来制造一个移位寄存器,以研究它的工作特性。结果,当漏电压是15V时,最大工作频率为11MHz,当漏电压是17V时,最大工作频率为18MHz。
[第三实施例]
本实施例涉及一种方案,以此方案,在实施第一实施例的工艺-加热促进结晶化之后,再用激光束辐照,使之退火,来进一步改进半导体区的结晶度。
其制造工艺说明如下,参考图3。用等离子体CVD方法在基片30(Corning 7059)上形成厚度为2000埃的底材氧化硅膜31。进一步,用等离子体CVD或真空CVD方法制造厚度为200-3000埃或最好为500-1500埃的非晶硅膜。通过在350-450℃下热处理0.1-2小时脱氢使薄膜中氢浓度降到低于5原子%,能容易的使非晶硅膜结晶化。然后构图以形成岛形硅区域32。随后用RF等离子CVD,ECR等离子DVC或溅射方法形成厚度为500-1500埃的氧化硅膜33,它起栅绝缘膜的作用。当采用等离子体CVD方法时,用TEOS(四乙氧硅烷)和氧作为原始气体能获得满意的结果。
之后,用溅射方法沉积含有1%硅的钽膜(厚5000埃),并构图以形成栅布线和电极34。钛,硅,铬或铝可作为栅电极的材料。
然后,将基片浸泡在3%酒石酸的1,2-亚乙基二醇溶液中,并且设置铂作为阴极,钽丝作为阳极在两电极之间通以电流进行阳极氧化。这样施加电流,使电压以2V/min上升,当达到220V时,电流恒定。当电流降低到10微安/米2时,电流截止。结果,形成厚度为2000埃的阳极氧化物(氧化钽)。同样,当钛,铝或硅被用作为栅电极(图3(A))时,能获得作为阳极氧化物的氧化钛,氧化铝或氧化硅。
接着,用等离子掺杂方法将杂质引入,作为掺杂气体,对N型TFT采用磷化氢(PH3),对P型TFT采用乙硼烷(B2H6)。图中表示的是N型TFT。所用的加速电压对磷化氢是80KeV,对乙硼烷是65KeV。从而形成杂质区域36A和36B。此时,如图所见,杂质区域和栅电极是不重合的。进一步,在杂质区域上的氧化硅薄膜33中建立孔,以使形成的硅化镍(或镍)膜37A和37B通过这些孔粘结到半导体区域32。然后在550℃氮气中进行四个小时的热处理,以使杂质区36A和36B以及其它半导体区域(图3(B))结晶化。
接着,用一个KrF准分子激光器照射在其上以促进结晶化,(激光器波长:248nm,脉宽:20nsec),此处用200-400mJ/cm2能量密度或例如250mJ/cm2能量密度进行两次激光束照射。进一步,此时,在激光束照射的同时,使基片加热到300℃,以增加激光束照射的效果。基片的加热温度可在200℃到450℃之间。
XeCl(波长:308nm),ArF(波长:193nm)或类似的都可用作激光束。用强光代替激光束照射也是可能的。用红外光束在短时间内照射实现RTA(快速热退火)特别有效,因为它允许硅膜有选择地进行加热。
由此能获得结晶度好的硅膜,这样处理的结果,用热退火结晶化的区域成为具有改良结晶度的硅膜。根据透射型(transmission type)电子显微镜所进行的观察,在本发明的结晶化方法之后,在激光照射区域看到相同方向的较大晶体。
最后,以与制造常规TFT方法相同的手段,沉积厚度为5000埃的氧化硅膜作为层间绝缘体38,并通过层间绝缘体建立接触孔,以便在源区和漏区域上形成布线和电极39A及39B。铝、钛、氮化钛或它们的多层膜适合作为布线和电极材料。在本实施例中,采用氮化钛(厚1000埃)和铝(厚5000埃)的多层膜。用上述工艺(图3(C))制成TFT(图为N一沟道型)。
[第四实施例]
本实施例是用含有加速结晶化的催化元素的溶液将催化元素引入非晶硅膜的一种方法。
参考图4,以说明其制造工艺。首先,用等离子CVD方法,在10cm见方的基片(Corning 7059)40上,形成厚度为2000埃的底材氧化硅薄膜41。用等离子CVD或真空CVD方法制造厚度为200-3000埃,最好选择500-1500埃的非晶硅膜。通过在350-450℃下,热处理0.1-2小时脱氢使该薄膜中氢浓度降到低于5原子%,能容易的使非晶硅膜结晶化。然后构图以形成岛形硅区域42。
然后,用RF等离子CVD,ECR等离子CVD或溅射方法形成厚度为500-1500埃的氧化硅膜43作栅绝缘膜。当采用等离子CVD方法时,使用TEOS(四乙氧硅烷)和氧作为原始气体能获得满意的结果。随后用溅射方法沉积含1%硅的钽膜(厚5000埃),并且构图以形成栅布线和电极44,钛、硅、铬或铝可以用作栅电极材料。
之后,将基片浸泡到3%的酒石酸的1,2-亚乙基二醇溶液中,并且设置铂作为阴极,钽丝作为阳极使两极之间通以电流进行阳极氧化,电流是如此施加的,即电压以2V/min提升当其达到220V时,电流变为恒定值。当电流降到10微安/米2时,电流截止。结果形成厚度为2000埃的阳极氧化物(氧化钽)45。同样,当用钛,铝或硅作为栅电极时,能获得作为阳极氧化物的氧化钛,氧化铝或氧化硅。(图4(A))。
接着,用等离子掺杂方法引入杂质。作为掺杂气体,磷化氢(PH3)用于N型TFT,乙硼硼烷(B2H6)用于P型TFT。图中所示为N型TFT。加速电压对磷化氢为80KeV,对乙硼烷为65KeV。由此产生杂质区域46A和46B。此时,由图(图4(B))中看出,杂质区和栅电极不重合。
进一步,在杂质区上的氧化硅薄膜中建立孔。然后在氧气中,用紫外线束在其上照射5分钟形成一个薄的氧化硅薄膜51。该氧化硅膜51的厚度定为约20-50埃。
形成氧化硅膜是为了改善在后继工序中所用溶液的润湿度。在该情况下,滴入5ml的加了100ppm(比重量)镍的醋酸盐溶液(在基片为10cm见方的情况下)。此时,用旋涂器41以50转/分旋涂10秒钟,从而在该基片整个表面上形成均匀的水薄膜52。随后,在该情况下,使该基片保持5秒钟之后,用旋涂器41,以每分钟2000转的速度进行60秒钟的旋转干燥。顺便提一下当旋涂器以0-150rpm旋转时,它可以置于旋转器上(图4(C))。
另外,虽然图4(C)画出的好像在旋转器41上被安置的基片40上只设置一个TFT,实际上,在基片40上形成大量的TFT。
其后,在550℃热处理四小时,使非晶硅膜42结晶化(在氮气中)。此时,晶体在水平方向从掺入镍的区域(与氧化物薄膜51接触的区域)向未引入镍的区域生长。
为获得第三实施例所说的薄膜,用激光或等强光照射,对改进晶体硅膜的结晶度是有效的。因为在第三实施例中,硅薄膜内的镍浓度相当高,在激光照射下,硅薄膜中形成沉淀在硅薄膜中的镍和大约为0.1-10微米的硅化镍颗粒,因此破坏了该薄膜的结构。然而,因为本实施例允许镍浓度降低到大于第三实施例的范围,因此没有沉淀的硅化镍,并且在激光照射下能防止薄膜变得粗糙。
图5表示,在SIMS中完成结晶化工序之后,在标号50指示的区域中,对镍浓度研究的结果。该区域是由从直接引入镍的区域开始晶体生长被结晶化的区域,它起TFT沟道形成区域的作用。已证明,在直接引入镍的区域中镍的浓度比图5所示浓度分布高一位数。这就是说,已证明,在完成之后,沟道形成区域的镍浓度比TFT的源/漏区域的镍浓度低不止一位数,如图5所示。
图5中所示的镍浓度可通过控制溶液中镍的浓度加以控制。当在本实施例中溶液中镍浓度为100ppm时,发现甚至用10ppm镍浓度也有可能结晶化。在此情况下,图5所示的镍浓度能进一步降低一位数。然而,当溶液中镍浓度被降低时,出现一个问题,即晶体从引入镍区域在水平方向生长的距离变短。
最后,采用与制造常规TFT方法相同的措施,沉积厚度为5000埃的氧化硅膜作为层间绝缘体48,通过此层向绝缘体建立接触孔以形成源区和漏区域上的布线和电极49A和49B。铝、钛,氮化钛或它们的多层膜适合作布线和电极材料。在本情况中,采用了氮化钛(厚1000埃)和铝(5000埃厚)的多层膜。
虽然本实施例中采用了醋酸盐溶液作为含催化元素的溶液,但是采用水溶液,有机溶剂溶液或类似溶液是可行的。此处的催化元素可以被含有,但不作为化合物,只作为分散质。
从极性溶剂的水,酒精、酸和氨中选出的一种溶剂可以作为含催化元素的溶剂使用。
当用镍作催化剂,并使其含在极性溶剂中时,以镍化合物被掺入。作为镍化合物,一般采用从溴化镍、乙酸镍、草酸镍、碳酸镍、氯化镍、碘化镍、氮化镍、硫酸镍、甲酸镍、乙酰丙酮镍、4-环已基丁酸镍,氧化镍和氢氧化镍中选择出的一种化合物。
作为溶剂,可从非极性溶剂的苯、甲苯、二甲苯、四氯化碳、三氯甲烷和乙醚中选出一种使用。
在这种情况中,加入镍作为镍化合物,一般使用的镍化合物是从乙酰丙酮镍和2-乙基已酸镍(nickel 2-ethylhexanodic acid)中选择一种。
将一种表面活性剂加到含催化元素的溶液中,以改善与待涂表面的粘接性和控制它的吸附作用也是有效的。将表面活性剂预先涂到待涂表面上也是可能的。当用单质镍作为催化元素时,必须将其用酸溶解到溶液中。
虽然上面已经说明采用镍催化元素完全溶解到溶液中的情况,但采用这样的乳剂材料是可能的,该乳剂中的由单质镍或镍化合物构成的粉末均匀的分散在分散介质中,镍没有完全溶解。像这样一种溶液,可使用从Tokyo Ohka kogyo Co.,Ltd获得OCD(Ohka DiffusionSource)。采用OCD溶液涂在要形成膜的表面上,并将它在约200℃下烘烤,就能容易的制成氧化硅膜。另外,因为它允许杂质自由地加入,因此它们能被使用。
上述说明也适合于采用镍以外的材料作为催化元素的情况。
此外,采用非极性溶液,如2-乙基已酸镍(nickel 2-ethylhexanodic acid)的甲苯溶液允许直接将其涂于非晶硅膜表面上。在该情况中,预先涂覆这种材料作为粘合剂用于保护膜是有效的。然而,必须注意,这种溶液不能涂的太多,因为它将减弱催化元素掺入非晶硅中的量。
尽管含在溶液中的催化元素之数量取决于溶液的类型,但对溶液来说一般趋向采用的量为200ppm-1ppm为合适,或优选为50ppm-1ppm(比重量)。该值是在结晶化结束之后,考虑了薄膜中镍浓度和氢氟酸电阻确定的。
如上所述,本发明能控制晶体生长的方向,这在过去是困难的,同时能明显的改善薄膜晶体管的可靠性和产量。另外,因为对本发明所需要的设备、装置和工艺是非常一般的,且大批量生产率也是极好的,所以本发明对工业生产提供了不可估量的利益。因此本发明是在工业上是有益的并是可专利的。
虽然本发明已经参照一些最佳实施例作了具体的说明和描述,但是本领域的技术人员应当理解在不偏离本发明的精神和范围下,前述的和其它改变的结构和细节是能由此做出的。
Claims (13)
1.一种晶体管,它包括:
用半导体材料在基片上形成并包括沟道区的金属推进的横向结晶区;
用半导体材料在金属推进的横向结晶区的侧面形成的多个金属推进的结晶区,其中在所述金属推进的横向结晶区和一个金属推进的结晶区之间的至少一个边界位于沟道区外面。
2.权利要求1的晶体管,其中所述金属推进的横向结晶区包括在沟道区的侧面形成的杂质掺杂区。
3.权利要求1的晶体管,其中所述金属推进的横向结晶区包括源区和漏区。
4.权利要求1的晶体管,其中所述金属推进的横向结晶区包括在沟道区的侧面形成的未掺杂部分。
5.一种晶体管,它包括:
沟道区,
具有与沟道区相邻的第一源部分和与第一源部分相邻的第二源部分的源区,
具有与沟道区相邻的第一漏部分和与第一漏部分相邻的第二漏部分的漏区,
其中所述沟道区与所述第一源部分和第一漏部分的至少一个包含金属推进的横向结晶区。
6.权利要求5的晶体管,其中所述第二源部分包含金属推进的结晶区。
7.权利要求5的晶体管,其中所述第二漏部分包含金属推进的结晶区。
8.权利要求5的晶体管,其中所述源区和漏区掺杂有杂质。
9.权利要求5的晶体管,其中所述沟道区、第一源部分和第一漏部分包含金属推进的横向结晶区,所述第二源区包含金属推进的结晶区,所述第二漏区包含金属推进的结晶区。
10.一种晶体管,它包括:
用半导体材料在基片上形成并包括沟道区的金属推进的横向结晶区;
用半导体材料在金属推进的横向结晶区的侧面形成的多个金属推进的结晶区,其中在金属推进的横向结晶区和一个金属推进的结晶区之间的至少一部分位于沟道区外面。
11.一种晶体管,它包括:
沟道区;
具有与沟道区相邻的源部分的源区;
具有与沟道区相邻的漏部分的漏区;
其中所述沟道区与所述源部分和漏部分的至少一个包含金属推进的横向结晶区。
12.一种晶体管,它包括:
用半导体材料在基片上形成并包括沟道区的金属感应的横向结晶区;和
用半导体材料在金属感应的横向结晶区的侧面形成的多个金属感应的结晶区,其中在金属感应的横向结晶区和一个金属感应的结晶区之间的至少一个边界位于沟道区外面。
13.一种晶体管,它包括:
沟道区,
具有与沟道区相邻的第一源部分和与第一源部分相邻的第二源部分的源区,
具有与沟道区相邻的第一漏部分和与第一漏部分相邻的第二漏部分的漏区,
其中所述沟道区与所述第一源部分和第一漏部分的至少一个包含金属感应的横向结晶区。
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- 1994-02-15 CN CN94103242A patent/CN1053292C/zh not_active Expired - Fee Related
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Cited By (2)
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CN104769718A (zh) * | 2012-11-07 | 2015-07-08 | 高通股份有限公司 | 共享扩散标准单元架构 |
CN104769718B (zh) * | 2012-11-07 | 2019-08-09 | 高通股份有限公司 | 共享扩散标准单元架构 |
Also Published As
Publication number | Publication date |
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JP3662263B2 (ja) | 2005-06-22 |
CN1256510A (zh) | 2000-06-14 |
CN1129961C (zh) | 2003-12-03 |
CN100452423C (zh) | 2009-01-14 |
US5773327A (en) | 1998-06-30 |
CN1218361C (zh) | 2005-09-07 |
CN1098555A (zh) | 1995-02-08 |
CN1256520A (zh) | 2000-06-14 |
JPH06244205A (ja) | 1994-09-02 |
CN1053292C (zh) | 2000-06-07 |
CN1275796A (zh) | 2000-12-06 |
CN1230910C (zh) | 2005-12-07 |
KR100376372B1 (ko) | 2003-03-15 |
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