CN1661812A - 具有隔离结构的高电压ldmos晶体管 - Google Patents

具有隔离结构的高电压ldmos晶体管 Download PDF

Info

Publication number
CN1661812A
CN1661812A CN2004100551833A CN200410055183A CN1661812A CN 1661812 A CN1661812 A CN 1661812A CN 2004100551833 A CN2004100551833 A CN 2004100551833A CN 200410055183 A CN200410055183 A CN 200410055183A CN 1661812 A CN1661812 A CN 1661812A
Authority
CN
China
Prior art keywords
type
region
drain
diffusion region
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2004100551833A
Other languages
English (en)
Other versions
CN100388504C (zh
Inventor
黄志丰
杨大勇
林振宇
简铎欣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Taiwan Corp
Original Assignee
System General Corp Taiwan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by System General Corp Taiwan filed Critical System General Corp Taiwan
Publication of CN1661812A publication Critical patent/CN1661812A/zh
Application granted granted Critical
Publication of CN100388504C publication Critical patent/CN100388504C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873Drain regions
    • H01L29/0878Impurity concentration or distribution
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873Drain regions
    • H01L29/0886Shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816Lateral DMOS transistors, i.e. LDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明为一种具有隔离结构的高电压LDMOS晶体管,包括在一N型井区(N-Well)中的一漏极延伸区(extended drain region)内的一P型区域(P-field)与分开的P型区域群(divided P-fields),该P型区域与分开的P型区域群于N型井区内形成接面场效(junction-field),使得漂移区能够在崩溃发生前先完全空乏,因此晶体管可以有较高的崩溃电压(break down voltage)且N型井区可容许较高的掺杂浓度。较高的掺杂浓度可有效降低LDMOS半导体的导通阻抗(on-resistance),此外,在源极(source)扩散区之下所形成的该N型井区,为源极提供一低阻抗路径,以限制漏极区与源极区之间的晶体管电流。

Description

具有隔离结构的高电压LDMOS晶体管
技术领域
本发明涉及一种半导体装置,特别是关于一横向功率金氧半场效晶体管(lateral power MOSFET)。
背景技术
在电源IC的发展过程中,为了将功率开关以及控制电路整合在一起而开发的单芯片制程,尤其是目前用于制作单石集成电路(monolithic IC)的横向二次扩散金氧半导体(lateral double diffusion MOS,LDMOS)制程,是一主流趋势,LDMOS制程是于半导体基板的表面进行平面扩散(planar diffusion)以便形成横向的主要电流路径,由于横向MOSFET是以典型的IC制程所制造,因此控制电路与横向功率MOSFET可以整合在一个单石电源IC上。
图1所示为一个电源转换器(power converter)的方块图,变压器200为单石电源IC 500的负载,LDMOS晶体管100具有漏极电极10、源极电极20以与门极40(栅极),用以切换变压器200。电阻400用来感测LDMOS晶体管100的切换电流Is,以进行功率控制。控制器300产生一控制信号以驱动LDMOS晶体管100进行功率转换,为了要降低成本,并使切换效能最佳化,控制器300与LDMOS晶体管100放置在同一基板上,LDMOS制程采用表面电场缩减(reduced surfaceelectricfield,RESURF)技术与低厚度磊晶(EPI)或N型井区(N-well)技术,可以达到高电压兼具低导通阻抗的目标。
近来,有许多与高电压LDMOS晶体管制程有关的开发技术被相继提出,尽管目前可以制造出高电压与低导通电阻的LDMOS晶体管,但是制程的复杂度会提高制作成本,同时/或者降低生产合格率,公知的半导体技术还有一个缺点是非隔离的源极结构,未受隔离的晶体管电流可能会在基板中流动,产生噪声干扰控制电路300,此外,LDMOS晶体管100的交换电流Is可能会产生一个地弹反射干扰控制电路300。
发明内容
本发明要解决的技术问题是:提供一种具有隔离结构的高电压LDMOS晶体管,达到高崩溃电压、低导通阻抗与隔离特性的晶体管以符合单石集成电路整合的目标。
为此,本发明提供一种具有隔离结构的高电压LDMOS晶体管,该隔离的高电压横向二次扩散金氧半导体(LDMOS)包括一P型基板(P-substrate),LDMOS晶体管同时包含具有N型导电离子(conductivity type ion)的一第一扩散区(diffusion region)与一第二扩散区,用以在P基板内形成一N型井区(N-well),第一扩散区更包括一漏极延伸区(extended drain region),一具有N+型导电离子的漏极扩散区形成一漏极区,而该漏极区位于漏极延伸区内。一具有P型导电离子的第三扩散区在该漏极延伸区内形成一P型区域(P-field)与一分开的P型区域群(divided P-fields),其中该分开的P型区域群至少含有一个以上的分开的P型区域。一具有N+型导电离子的源极扩散区形成一源极区,一具有P+型导电离于的接点扩散区形成一接点区,一具有P型导电离子的第四扩散区形成一隔离的P型井区以防止崩溃,其中位于该第二扩散区的隔离的P型井区将该源极区与该接点区包围。位于N型井区中的漏极延伸区内的P型区域与分开的P型区域群(divided P-fields)在N型井区产生接面场效,使漂移区(drift region)空乏,因此会产生一个介于源极区与漏极区的传导通道,并穿过N型井区,而分开的P型区域群可降低信道的导通电阻。闸极(polysilicongate electrode)形成于该传导通道之上以控制该传导通道的电流,此外,由第二扩散区形成的N型井区为源极区提供一低阻抗路径,以限制漏极区与源极区之间的晶体管电流。
本发明的特点和优点是:本发明的具有隔离结构的高电压LDMOS晶体管,为一种高电压横向二次扩散金氧半导体(LDMOS)晶体管,包括在一N型井区(N-Well)中的一漏极延伸区(extended drain region)内的一P型区域(P-field)与分开的P型区域群(divided P-fields),该P型区域与分开的P型区域群于N型井区内形成接面场效(junction-field),使得漂移区能够在崩溃发生前先完全空乏,因此晶体管可以有较高的崩溃电压(break down voltage)且N型井区可容许较高的掺杂浓度。较高的掺杂浓度可有效降低LDMOS半导体的导通阻抗(on-resistance),此外,在源极(source)扩散区之下所形成的该N型井区,为源极提供一低阻抗路径,以限制漏极区与源极区之间的晶体管电流。隔离的LDMOS晶体管可以限制电流流动,从而正确地量测通过电阻的交换电流。
附图说明
图1为电源转换器的方块图;
图2为本发明的较佳实施例中一个LDMOS晶体管的剖面图;
图3为图2的LDMOS晶体管的俯视图;以及
图4为根据本发明的较佳实施例,当650V电压加诸于LDMOS晶体管时,所呈现的电场分布。
附图标号说明:
10、漏极电极         12、焊垫               15、漏极金属接点
20、源极电极         22、焊垫               25、源极金属接点
30、N型井区          33、第一扩散区         37、第二扩散区
40、闸极             42、焊垫               50、漏极延伸区
52、漏极区           53、漏极扩散区         55、源极扩散区
56、源极区           57、接点扩散区         58、接点区
60、P型区域          61、分开的P型区域      62、分开的P型区域
65、隔离的P型井区    67、第四扩散区         71、漏极间隙
72、源极间隙            81、薄闸极氧化层         85、绝缘层
86、绝缘层              87、场氧化层             88、场氧化层
90、P型基板             100、LDMOS晶体管         200、变压器
300、控制器             400、电阻                500、电源IC
具体实施方式
本发明的前述技术方案或特征,将依据附图及实施例加以详细说明,惟附图及实施例,旨在具体说明本发明的特征而非在限制或缩限本发明。
图2为一个LDMOS晶体管100的剖面图,LDMOS晶体管100包含P型基板90,LDMOS晶体管100更包含具有N型导电离子的第一扩散区33与具有N型导电离子的第二扩散区37,以在P型基板90内形成N型井区30,而第一扩散区33更包含一漏极延伸区50。由第一扩散区33形成的N型井区30内具有N+型导电离于的漏极扩散区53,其于漏极延伸区50内产生漏极区52。具有P型导电离子的第三扩散区在漏极延伸区50内形成P型区域60以及分开的P型区域61与62,此实施例中其中该分开的P型区域61与62比P型区域60更靠近漏极区52。由第二扩散区37形成的N型井区30内具有N+型导电离子的源极扩散区55,其产生源极区56。由第二扩散区37形成的N型井区30内具有P+型导电离子的接点扩散区57,其产生一接点区58。由第二扩散区37形成的N型井区30内具有P型导电离子的第四扩散区67,其产生一隔离的P型井区65以防止崩溃,其中隔离的P型井区65将源极区56与接点区58围起。P型区域60以及分开的P型区域61与62在N型井区30内形成接面场效,使得漂移区(drift region)空乏。
一传导通道形成于源极区56与漏极区52之间,并穿过N型井区30,分开的P型区域61与62可进一步降低传导通道的导通电阻,一薄闸极氧化层(thin gateoxide)81与一厚场氧化层(thick field oxide)87形成于P型基板90之上,一闸极40位于薄闸极氧化层81与场氧化层87的区域之上,以控制传导通道的电流,一漏极间隙(drain-gap)71形成于漏极扩散区53与场氧化层87之间,用以在漏极扩散区53与场氧化层87之间维持一空间,源极间隙(source-gap)72形成于场氧化层87与隔离的P型井区65之间,用以在场氧化层87与隔离的P型井区65之间维持一空间,漏极间隙71与源极间隙72的适当配置可在实质上有助于提升LDMOS晶体管100的崩溃电压,漏极间隙71更可进一步降低传导通道的导通阻抗。
绝缘层85与86覆盖在闸极40、场氧化层87与场氧化层88之上,绝缘层85与86是采用,例如,二氧化硅(silicon dioxide)等材料构成,漏极金属接点15为一金属电极,用以接触漏极扩散区53,源极金属接点25亦为一金属电极,用以接触源极扩散区55与接点扩散区57。
图3为图2所示LDMOS晶体管100的俯视图,LDMOS晶体管100包含一漏极电极10、源极电极20、以与门极(polysilicon gate electrode)40,还有漏极电极10所用的焊垫(bonding pad)12、源极电极20所用的焊垫22、以与门极40所用的焊垫42。
参照图2与图3,漏极延伸区50与漏极扩散区53形成漏极10,而隔离的P型井区65、源极扩散区55、以及接点扩散区57组成源极电极20,焊垫12连接至漏极金属接点15,焊垫22连接至源极金属接点25,焊垫42连接至闸极40。在P型区域60以及分开的P型区域61与62底下的N型井区30由漏极电极10连接至源极电极20,在分开的P型区域61与62之间的N型井区30可降低传导通道的导通阻抗。
P型区域60以及分开的P型区域61与62位于漏极延伸区50内,在N型井区30内形成一接面场效(junction-field),其中N型井区30、P型区域60以及分开的P型区域61与62使漂移区(drift region)空乏,而漂移区在N型井区30内建立电场,并提升崩溃电压,为了要达到高崩溃电压,漏极延伸区50必须在崩溃发生之前完全空乏,N型井区30、P型区域60以及分开的P型区域61与62能让漏极延伸区50在崩溃到达前被空乏,即使漂移区具有高掺杂浓度(doping density)亦同,如此一来可以让漂移区允许较高的掺杂浓度以达到低阻抗的特性。
图4为当650V电压加诸于LDMOS晶体管100的漏极区52时的电场分布情形。粗虚线分别标出0V、100V、200V、300V、400V、500V、550V、600V、以及650V等电压。
此外,由第二扩散区37形成的N型井区30部分为源极区56提供一低阻抗路径,而限制了在N型井区内漏极区52与源极区56之间的晶体管电流。
本发明的LDMOS晶体管100采用简单的结构来达成高崩溃电压、低导通阻抗与隔离的特性,在成本降低的同时合格率也可获得提升。
虽然本发明已以具体实施例揭示,但其并非用以限定本发明,任何本领域的技术人员,在不脱离本发明的构思和范围的前提下所作出的等同组件的置换,或依本发明专利保护范围所作的等同变化与修饰,皆应仍属本专利涵盖之范畴。

Claims (4)

1.一种具有隔离结构的高电压LDMOS晶体管,其特征在于,包含:
一P型基板;
一第一扩散区与一第二扩散区,其中该第一扩散区与该第二扩散区皆具有N型导电离子,于该P型基板内形成一N型井区,而其中该第一扩散区包含一漏极延伸区;
一具有N+型导电离子的漏极扩散区,用以在该漏极延伸区内形成一漏极区;
一具有P型导电离子的一第三扩散区,包含在该漏极延伸区内形成的一P型区域与分开的P型区域群,且其中该P型区域与分开的P型区域群在该漏极延伸区内产生接面场效;
一具有N+型导电离子的源极扩散区,用以在该第二扩散区所形成的该N型井区内形成一源极区;
一传导通道,形成于该源极区与该漏极区之间;
一闸极,形成于该传导通道之上以控制该传导通道的一电流;
一具有P+型导电离子的接点扩散区,用以在该第二扩散区所形成的该N型井区内形成一接点区;以及
一具有P型导电离子的一第四扩散区,用以在该第二扩散区所形成的该N型井区内形成一隔离的P型井区以防止崩溃,其中该隔离的P型井区将该源极区与该接点区包围起。
2.如权利要求1所述的晶体管,其特征在于,其中由该第二扩散区形成的该N型井区为该源极区提供一低阻抗路径,以限制该漏极区与该源极区之间的一晶体管电流。
3.如权利要求1所述的晶体管,其特征在于,所述晶体管更包含:
一薄闸极氧化层,形成于该传导通道之上;
一厚场氧化层,邻接于该薄闸极氧化层侧面;
一漏极间隙,形成于该漏极扩散区与该厚场氧化层之间,用以在该漏极扩散区与该厚场氧化层之间维持一空间;
一源极间隙,形成于该厚场氧化层与该隔离的P型井区之间,用以在该厚场氧化层与该隔离的P型井区之间维持一空间;
一绝缘层,覆盖于该闸极与该厚场氧化层之上;
一漏极金属接点,具有一第一金属电极以接触该漏极扩散区;以及
一源极金属接点,具有一第二金属电极以接触该源极扩散区与该接点扩散区。
4.如权利要求1所述的晶体管,其特征在于,该P型区域与分开的P型区域群在该N型井区产生接面场效,以使一漂移区空乏。
CNB2004100551833A 2004-02-24 2004-08-12 具有隔离结构的高电压ldmos晶体管 Expired - Fee Related CN100388504C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/786,703 2004-02-24
US10/786,703 US6995428B2 (en) 2004-02-24 2004-02-24 High voltage LDMOS transistor having an isolated structure

Publications (2)

Publication Number Publication Date
CN1661812A true CN1661812A (zh) 2005-08-31
CN100388504C CN100388504C (zh) 2008-05-14

Family

ID=34861815

Family Applications (2)

Application Number Title Priority Date Filing Date
CNA2004800259330A Pending CN1849710A (zh) 2004-02-24 2004-07-02 具有一隔离结构的高电压ldmos晶体管
CNB2004100551833A Expired - Fee Related CN100388504C (zh) 2004-02-24 2004-08-12 具有隔离结构的高电压ldmos晶体管

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CNA2004800259330A Pending CN1849710A (zh) 2004-02-24 2004-07-02 具有一隔离结构的高电压ldmos晶体管

Country Status (4)

Country Link
US (1) US6995428B2 (zh)
CN (2) CN1849710A (zh)
TW (1) TWI235492B (zh)
WO (1) WO2005081321A1 (zh)

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100438032C (zh) * 2006-02-22 2008-11-26 崇贸科技股份有限公司 具有辐射结构和隔离效果的高电压和低导通电阻晶体管
CN100454579C (zh) * 2006-07-03 2009-01-21 崇贸科技股份有限公司 自驱动ldmos晶体管
US7615976B2 (en) 2006-04-19 2009-11-10 System General Corp. Switching circuit of power converter having voltage-clipping device to improve efficiency
CN101075790B (zh) * 2006-05-15 2010-05-12 崇贸科技股份有限公司 具有电压削波装置用以改善效率的功率转换器的切换电路
CN101834207A (zh) * 2010-04-27 2010-09-15 上海北京大学微电子研究院 双扩散金属氧化物半导体场效应管结构及其制造方法
CN101916728A (zh) * 2010-07-20 2010-12-15 中国科学院上海微系统与信息技术研究所 可完全消除衬底辅助耗尽效应的soi超结ldmos结构的制作工艺
CN101916779A (zh) * 2010-07-20 2010-12-15 中国科学院上海微系统与信息技术研究所 可完全消除衬底辅助耗尽效应的soi超结ldmos结构
CN101297407B (zh) * 2005-10-26 2011-05-25 惠普开发有限公司 晶体管器件及其制造方法
CN102130012A (zh) * 2010-12-31 2011-07-20 中国科学院上海微系统与信息技术研究所 Soi超结ldmos器件的ldd、lds及缓冲层一体化制作方法
US8247870B2 (en) 2006-09-26 2012-08-21 O2Micro, Inc. Power MOSFET integration
US8278712B2 (en) 2007-09-25 2012-10-02 O2Micro Inc. Power MOSFET integration
CN102130167B (zh) * 2010-01-20 2012-11-07 上海华虹Nec电子有限公司 Dddmos器件及其制造方法
CN104201207A (zh) * 2014-09-16 2014-12-10 电子科技大学 一种具有自适应偏置场板的高压mos器件
CN101960574B (zh) * 2008-03-17 2015-06-03 飞兆半导体公司 具有经改进架构的ldmos装置
CN105097924A (zh) * 2014-05-22 2015-11-25 上海北京大学微电子研究院 功率器件结构
CN109900965A (zh) * 2017-12-07 2019-06-18 南亚科技股份有限公司 一种mos晶体管的接点电阻的计测方法
CN112448711A (zh) * 2019-08-30 2021-03-05 新唐科技股份有限公司 高电压集成电路及其半导体结构
CN112993021A (zh) * 2019-12-18 2021-06-18 东南大学 横向双扩散金属氧化物半导体场效应管
CN113078217A (zh) * 2020-01-06 2021-07-06 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7498652B2 (en) * 2004-04-26 2009-03-03 Texas Instruments Incorporated Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof
US7141860B2 (en) * 2004-06-23 2006-11-28 Freescale Semiconductor, Inc. LDMOS transistor
US7535057B2 (en) * 2005-05-24 2009-05-19 Robert Kuo-Chang Yang DMOS transistor with a poly-filled deep trench for improved performance
EP1852916A1 (en) * 2006-05-05 2007-11-07 Austriamicrosystems AG High voltage transistor
JP5048273B2 (ja) * 2006-05-10 2012-10-17 オンセミコンダクター・トレーディング・リミテッド 絶縁ゲート型半導体装置
US8080848B2 (en) * 2006-05-11 2011-12-20 Fairchild Semiconductor Corporation High voltage semiconductor device with lateral series capacitive structure
JP4616856B2 (ja) * 2007-03-27 2011-01-19 株式会社日立製作所 半導体装置、及び半導体装置の製造方法
US20080296636A1 (en) * 2007-05-31 2008-12-04 Darwish Mohamed N Devices and integrated circuits including lateral floating capacitively coupled structures
CN103762243B (zh) 2007-09-21 2017-07-28 飞兆半导体公司 功率器件
US8193565B2 (en) 2008-04-18 2012-06-05 Fairchild Semiconductor Corporation Multi-level lateral floating coupled capacitor transistor structures
CN101673763B (zh) * 2008-09-09 2011-06-22 上海华虹Nec电子有限公司 Ldmos晶体管及其制备方法
US8482065B2 (en) * 2008-11-25 2013-07-09 Newport Fab, Llc MOS transistor with a reduced on-resistance and area product
KR101578931B1 (ko) * 2008-12-05 2015-12-21 주식회사 동부하이텍 반도체 소자 및 반도체 소자의 제조 방법
US8174067B2 (en) 2008-12-08 2012-05-08 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
CN102013437B (zh) * 2009-09-07 2014-11-05 苏州捷芯威半导体有限公司 半导体器件及其制造方法
US8624302B2 (en) * 2010-02-05 2014-01-07 Fairchild Semiconductor Corporation Structure and method for post oxidation silicon trench bottom shaping
DE102010014370B4 (de) * 2010-04-09 2021-12-02 X-Fab Semiconductor Foundries Ag LDMOS-Transistor und LDMOS - Bauteil
TWI449159B (zh) * 2011-04-18 2014-08-11 Episil Technologies Inc 功率橫向雙擴散金氧半導體元件
CN103050512A (zh) * 2011-10-13 2013-04-17 上海华虹Nec电子有限公司 非外延的高压绝缘n型ldmos器件结构
US8872278B2 (en) 2011-10-25 2014-10-28 Fairchild Semiconductor Corporation Integrated gate runner and field implant termination for trench devices
CN103123929B (zh) * 2011-11-21 2015-10-14 上海华虹宏力半导体制造有限公司 隔离型高耐压场效应管的版图结构
CN102623509A (zh) * 2012-04-19 2012-08-01 成都芯源系统有限公司 高压开关器件及其制作方法
CN103633083B (zh) * 2012-08-15 2016-06-08 上海华虹宏力半导体制造有限公司 形成超高耐压电阻的版图结构
CN103681777B (zh) * 2012-08-31 2016-11-02 上海华虹宏力半导体制造有限公司 面结型场效应管
US8786021B2 (en) * 2012-09-04 2014-07-22 Macronix International Co., Ltd. Semiconductor structure having an active device and method for manufacturing and manipulating the same
US9059278B2 (en) 2013-08-06 2015-06-16 International Business Machines Corporation High voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) having a deep fully depleted drain drift region
KR101941295B1 (ko) * 2013-08-09 2019-01-23 매그나칩 반도체 유한회사 반도체 소자
US9460926B2 (en) * 2014-06-30 2016-10-04 Alpha And Omega Semiconductor Incorporated Forming JFET and LDMOS transistor in monolithic power integrated circuit using deep diffusion regions
KR102164721B1 (ko) 2014-11-19 2020-10-13 삼성전자 주식회사 반도체 장치
US10784372B2 (en) * 2015-04-03 2020-09-22 Magnachip Semiconductor, Ltd. Semiconductor device with high voltage field effect transistor and junction field effect transistor
KR101975630B1 (ko) * 2015-04-03 2019-08-29 매그나칩 반도체 유한회사 접합 트랜지스터와 고전압 트랜지스터 구조를 포함한 반도체 소자 및 그 제조 방법
KR102389294B1 (ko) * 2015-06-16 2022-04-20 삼성전자주식회사 반도체 장치 및 그 제조 방법
EP3144974B1 (en) * 2015-09-18 2022-01-26 Ampleon Netherlands B.V. Semiconductor device
US10103258B2 (en) 2016-12-29 2018-10-16 Texas Instruments Incorporated Laterally diffused metal oxide semiconductor with gate poly contact within source window
TWI659539B (zh) * 2018-06-28 2019-05-11 立錡科技股份有限公司 高壓元件及其製造方法
CN113871456B (zh) * 2021-10-09 2023-07-04 上海华虹宏力半导体制造有限公司 Ldmos器件及其形成方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW218424B (zh) * 1992-05-21 1994-01-01 Philips Nv
JPH07135307A (ja) * 1993-06-30 1995-05-23 Shindengen Electric Mfg Co Ltd 半導体装置
JPH0974190A (ja) * 1995-09-06 1997-03-18 Denso Corp 半導体装置
JP3142057B2 (ja) * 1997-11-13 2001-03-07 日本電気株式会社 半導体装置とその製造方法、及び駆動装置
JP2000164876A (ja) * 1998-11-27 2000-06-16 Matsushita Electric Works Ltd 半導体装置及びその製造方法
US6211552B1 (en) * 1999-05-27 2001-04-03 Texas Instruments Incorporated Resurf LDMOS device with deep drain region
JP4357127B2 (ja) * 2000-03-03 2009-11-04 株式会社東芝 半導体装置
KR100360416B1 (ko) * 2000-04-12 2002-11-13 페어차일드코리아반도체 주식회사 높은 브레이크다운 전압을 갖는 전력용 반도체소자 및 그제조방법
US6448625B1 (en) * 2001-03-16 2002-09-10 Semiconductor Components Industries Llc High voltage metal oxide device with enhanced well region
US6475870B1 (en) * 2001-07-23 2002-11-05 Taiwan Semiconductor Manufacturing Company P-type LDMOS device with buried layer to solve punch-through problems and process for its manufacture

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101297407B (zh) * 2005-10-26 2011-05-25 惠普开发有限公司 晶体管器件及其制造方法
CN100438032C (zh) * 2006-02-22 2008-11-26 崇贸科技股份有限公司 具有辐射结构和隔离效果的高电压和低导通电阻晶体管
US7615976B2 (en) 2006-04-19 2009-11-10 System General Corp. Switching circuit of power converter having voltage-clipping device to improve efficiency
CN101075790B (zh) * 2006-05-15 2010-05-12 崇贸科技股份有限公司 具有电压削波装置用以改善效率的功率转换器的切换电路
CN100454579C (zh) * 2006-07-03 2009-01-21 崇贸科技股份有限公司 自驱动ldmos晶体管
US8247870B2 (en) 2006-09-26 2012-08-21 O2Micro, Inc. Power MOSFET integration
US8278712B2 (en) 2007-09-25 2012-10-02 O2Micro Inc. Power MOSFET integration
CN101960574B (zh) * 2008-03-17 2015-06-03 飞兆半导体公司 具有经改进架构的ldmos装置
CN102130167B (zh) * 2010-01-20 2012-11-07 上海华虹Nec电子有限公司 Dddmos器件及其制造方法
CN101834207A (zh) * 2010-04-27 2010-09-15 上海北京大学微电子研究院 双扩散金属氧化物半导体场效应管结构及其制造方法
CN101916779A (zh) * 2010-07-20 2010-12-15 中国科学院上海微系统与信息技术研究所 可完全消除衬底辅助耗尽效应的soi超结ldmos结构
CN101916728A (zh) * 2010-07-20 2010-12-15 中国科学院上海微系统与信息技术研究所 可完全消除衬底辅助耗尽效应的soi超结ldmos结构的制作工艺
CN101916779B (zh) * 2010-07-20 2012-10-03 中国科学院上海微系统与信息技术研究所 可完全消除衬底辅助耗尽效应的soi超结ldmos结构
CN102130012B (zh) * 2010-12-31 2012-06-27 中国科学院上海微系统与信息技术研究所 Soi超结ldmos器件的ldd、lds及缓冲层一体化制作方法
CN102130012A (zh) * 2010-12-31 2011-07-20 中国科学院上海微系统与信息技术研究所 Soi超结ldmos器件的ldd、lds及缓冲层一体化制作方法
CN105097924A (zh) * 2014-05-22 2015-11-25 上海北京大学微电子研究院 功率器件结构
CN104201207A (zh) * 2014-09-16 2014-12-10 电子科技大学 一种具有自适应偏置场板的高压mos器件
CN109900965A (zh) * 2017-12-07 2019-06-18 南亚科技股份有限公司 一种mos晶体管的接点电阻的计测方法
CN112448711A (zh) * 2019-08-30 2021-03-05 新唐科技股份有限公司 高电压集成电路及其半导体结构
CN112448711B (zh) * 2019-08-30 2023-09-08 新唐科技股份有限公司 高电压集成电路及其半导体结构
CN112993021A (zh) * 2019-12-18 2021-06-18 东南大学 横向双扩散金属氧化物半导体场效应管
CN113078217A (zh) * 2020-01-06 2021-07-06 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Also Published As

Publication number Publication date
CN100388504C (zh) 2008-05-14
US20050184338A1 (en) 2005-08-25
WO2005081321A1 (en) 2005-09-01
TWI235492B (en) 2005-07-01
US6995428B2 (en) 2006-02-07
TW200529429A (en) 2005-09-01
CN1849710A (zh) 2006-10-18

Similar Documents

Publication Publication Date Title
CN1661812A (zh) 具有隔离结构的高电压ldmos晶体管
CN100334742C (zh) 具有一分开井结构的隔离的高电压ldmos晶体管
US10020369B2 (en) Dual channel trench LDMOS transistors with drain superjunction structure integrated therewith
US8304329B2 (en) Power device structures and methods
US8659076B2 (en) Semiconductor device structures and related processes
US8319278B1 (en) Power device structures and methods using empty space zones
TWI509798B (zh) 用於形成具多通道之屏蔽閘極溝槽場效電晶體(fet)的結構及方法
US8310001B2 (en) MOSFET switch with embedded electrostatic charge
US7265416B2 (en) High breakdown voltage low on-resistance lateral DMOS transistor
JP5687700B2 (ja) スーパージャンクショントレンチパワーmosfetデバイス
JP5746699B2 (ja) スーパージャンクショントレンチパワーmosfetデバイスの製造
US8207577B2 (en) High-voltage transistor structure with reduced gate capacitance
US20070228463A1 (en) Self-aligned complementary ldmos
US10068965B1 (en) Lateral high-voltage device
WO2010014283A1 (en) Lateral devices containing permanent charge
WO2006134810A1 (ja) 半導体デバイス
CN101593773B (zh) 沟槽型功率mos晶体管及利用其的集成电路
KR100290913B1 (ko) 고전압 소자 및 그 제조방법
US20140117441A1 (en) Power device structures and methods
CN112713193B (zh) 一种具有凸型扩展埋氧区的沟槽ldmos晶体管
KR100345305B1 (en) Ldmos type power device with polysilicon field plate structure and method for manufacturing thereof
CN102983162A (zh) 半导体装置及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20080514

Termination date: 20210812