CN101297407B - 晶体管器件及其制造方法 - Google Patents

晶体管器件及其制造方法 Download PDF

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CN101297407B
CN101297407B CN2006800398116A CN200680039811A CN101297407B CN 101297407 B CN101297407 B CN 101297407B CN 2006800398116 A CN2006800398116 A CN 2006800398116A CN 200680039811 A CN200680039811 A CN 200680039811A CN 101297407 B CN101297407 B CN 101297407B
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C·黄
J·A·欣茨曼
D·J·施勒曼
H·廖
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Abstract

本发明提供一种晶体管器件及其制造方法，该晶体管器件包括第一型半导体材料的轻掺杂层(42)以及第二型半导体材料的体区(44)。在体区(44)内形成第一型的源区(46)。源区(46)比轻掺杂层掺杂的更多。在轻掺杂层(42)内形成第一型的漏区(50)，漏区(50)比轻掺杂层(42)掺杂的更多。还提供设置在体区(44)和漏区(50)之间的轻掺杂层(42)的漂移区(54)。另外，提供包围漏区的栅电极。栅电极(34A)部分设置在薄氧化物(36)上且部分设置在厚氧化物(56)上，其中从薄氧化物(36)在厚氧化物(56)上延伸的栅电极(34A)控制漂移区内的电场以增大漏区(50)的雪崩击穿。

Description

晶体管器件及其制造方法
背景技术
横向扩散金属氧化物半导体(LDMOS)晶体管用在各种电路应用中。本领域技术人员知道，典型LDMOS晶体管结构使用多指栅极。但是，对于高压和低驱动电流的电路应用，已知的LDMOS结构至少包括双指栅极。因此，这种晶体管比所需要的大得多，硅和管芯空间被不必要的浪费。
当前LDMOS结构包括至少两个栅极和两个漏极，一共用源极完全由多晶硅栅极包围。这种设计结构上的对称性增大了每单位面积的有效沟道宽度，并且具有减小器件导通电阻的优点。这种结构在同时需要高驱动电流和高压的功率电路应用中很受欢迎。但是，该双栅极设计限制了最小器件尺寸，并且在小的宽/长比适用于需要高压但低驱动电流的应用时不允许设计者使用小的宽/长(W/L)比。此外，当前LDMOS结构会导致增加辅助元件以满足性能需求。因此，辅助元件消耗了更多管芯空间并且给电路性能增加了更多变化性。对于典型的非LDMOS晶体管，栅极宽度和栅极长度对电路设计者来说都是可变的。但是，由于LDMOS结构本身的原因，栅极长度通常由工艺固定。所以，只有栅极宽度对电路设计来说是可变的。
因此，需要具有较小宽度的高压器件。相应地，需要具有较小管芯尺寸的新型器件。期望减小单元尺寸而不降低击穿电压。此外，需要一种高压器件，它消除了对至少一些现有器件所需的辅助元件的需求。还期望提高制造中的生产率。
发明内容
提供一种晶体管器件，其具有第一型半导体材料的轻掺杂层和第二型半导体材料的体区。在体区内形成第一型的源区。源区比轻掺杂层掺杂得更多。在轻掺杂层内形成第一型的漏区，漏区比轻掺杂层掺杂得更多。还提供设置在体区和漏区之间的轻掺杂层的漂移区。此外，提供包围漏区的栅电极。栅电极部分地设置在薄氧化物上方并且部分地设置在厚氧化物上方，其中从薄氧化物在厚氧化物上延伸的栅电极控制漂移区内的电场，以增加漏区的雪崩击穿。
附图说明
阅读下面的详细描述、权利要求和附图后，实施例的特征和发明性的方面将更加显而易见，以下是附图的简单说明：
图1是根据一实施例的示例单指栅极LDMOS晶体管的部分截面图；
图2是示出了图1的实施例的漏区、包围环、栅电极、源区和体区的部分重叠视图。
图3是示出了图1的实施例的紧密包围源区的马蹄形区、源极分接触(source split contact)和漏区的部分重叠视图。
具体实施方式
现在参考附图详细说明示例性实施例。虽然附图示出实施例，但附图不一定按比例绘制，而且某些特征可能经过放大以更好地示出和解释实施例的创新方面。此外，这里所描述的实施例并非意在排除其它实施例，或者将其限制于附图所示及下文详述的具体形式和配置。
参见图1-3，其中示出晶体管20的实施例。晶体管20配置成单指栅极LDMOS晶体管。晶体管20包括漏极接触30、源极分接触32、多晶硅栅电极34A以及多晶硅包围环34B。另外，在第二型(P)的半导体衬底40内配置第一型(N)的轻掺杂阱42。在轻掺杂阱42内配置第二型(P)的体区44。在体区44内形成源区46(N+)和马蹄形区48(P+)。为清楚起见，图2在源区46和马蹄形区48之间具有间隙。但是，实践中源区46和马蹄形区48彼此直接接触。漏区50位于漏极接触30下方，并配置成更重掺杂(N+)的第一型。源极分接触32使源区46和马蹄形区48短路。
多晶硅栅电极34A部分地设置于薄栅氧化物36和使栅电极34A与下层结构绝缘的厚场氧化层56之上。栅电极34A部分地位于场氧化层56之上的部分改变栅电极34A边缘的表面处的电场，因此提供更高的电压能力。此外，栅电极34A设置在作为体区44一部分的导电沟道52上。导电沟道52在栅氧化36之下、体区44的表面处形成。晶体管20的有效栅极长度64，例如沟道长度，通过体区44上方的栅电极34A和源区46(N+)扩散的重叠测量。体区44(P)和源区46(N+)两者都与栅电极34A和包围环34B自对准，这是因为这两个工艺步骤是在栅极界定之后进行的(以下详细说明该步骤)。
为了在不降低高压处理能力的同时减小器件尺寸(即单元尺寸)，将由轻掺杂漏极漂移区54和附属于栅电极34A的场极板构成的高压技术应用到晶体管20。栅电极34A延伸遍布栅氧化层36，形成多晶硅场极板以提高晶体管20的击穿电压能力。
高压漏区50完全由多晶硅栅电极34A和多晶硅包围环34B包围并用作多晶硅引导环(guide ring)(见图1和2)。由于包围环34B的电位被偏置在与高压LDMOS晶体管栅电极34A相同的电位，该电位通常比场阈值低很多，因此可以实现高压漏区50和低压电路区(未示出)之间的有效隔离。从而，当在低压侧应用中晶体管源极与地连接时，不需要额外的多晶硅引导环环绕晶体管20来抑制干扰。
如图1所示，包围环34B的一部分位于阱42上方，并且包围环34B的一部分位于衬底40上方。氧化层60作为绝缘物形成于晶体管20上方，并且可由多个氧化层构成。包围环34B在第一场氧化层56上形成，其用于将高压漏区50与阱42、衬底40和任何附近的低压电路(未示出)隔离。多晶硅栅电极34A和包围环34B还通过第二氧化层57与配置在晶体管20上方的其它电路或互连(未示出)隔离。
在高压侧应用中，可在源区46附近实施部分地包围阱42的引导环62，例如泄漏抑制环。见图1-2。引导环62抑制由于从衬底40至源区46的泄漏电流引起的击穿电压降低。引导环62可形成于氧化层56上，氧化层56可用第一场氧化层56或几个氧化层形成，见下文中的详细说明。
引导环62可使用多晶硅或金属互连层。当使用多晶硅互连时，引导环62形成于第一氧化层56上。当使用金属互连时，引导环62形成于第一场氧化层56和第二氧化层上方或第一、第二和第三氧化层上方(未在图中示出)。引导环62形成为部分地位于阱42上方并且部分地位于衬底40上方。位于阱42和衬底40上方的引导环62的总宽度和面积对于隔离效果尤为重要。引导环62通过金属互连80与体区44和源区46连接(见图2)。如上文所述，对于低压侧应用，多晶硅栅极34A和包围环34B完全包围漏区50。因此，不需要额外的引导环。
晶体管20还包括部分地包围源区46的更重掺杂的第二型(P+)马蹄形区48(见图2和3)。马蹄形区48抑制LDMOS晶体管20内的寄生NPN晶体管。因此，闩锁效应的风险得以降低。马蹄形区48(P+)也用来有效地终止宽度方向上的晶体管沟道，限定出有效栅极宽度66。体区44和源区46通过源极分接触32内部地短路，该源极分接触32部分地形成在马蹄形区48(P+)上方并且部分地形成在源区46(N+)上方。体区44和源区46还通过体接触31由金属互连80内部地连接，金属互连80形成于马蹄形区48(P+)和源极分接触32之上。
晶体管20的栅长64和栅宽66如图1和2所示。对于晶体管20，栅宽66是由马蹄形区48(P+)包围的源区46的距离。参见图3，典型的双栅LDMOS晶体管具有的栅宽为源极宽度距离的两倍。例如，在1μm CMOS工艺中集成的双指栅10V LDMOS晶体管，由于设计规则限制，最小栅宽为23.2μm。借助在适当位置的相同的设计规则(1μm CMOS工艺)，应用图1-3所描绘的晶体管20的实施例可以实现3.2μm的栅宽(40VLDMOS)。对于最小的LDMOS晶体管，栅极宽度的这种减小提供40％的单元尺寸减小和86％的驱动电流减小。本领域技术人员皆知，由于微型化的快速发展，具体的尺度没有相对尺寸重要。40％的尺寸减小可以按比例缩放到兼容的工艺技术。此外，替代工艺的设计规则可能允许单元尺寸更进一步减小。因此，3.2μm的具体尺寸不视为设计标准，且不用来确定可能用图1-3的实施例实施的任何最小尺寸。完全期望制造工艺的发展将容许所述实施例获得比3.2μm小的栅长。
现在转到晶体管20的制造，描述制造LDMOS晶体管20实体的工艺步骤。
首先，通过N型掺杂注入和热推进(thermal drive)工艺在衬底40(P)内形成阱42(N)。然后，在阱42(N)内限定出晶体管有源区。环绕有源区生长厚场氧化层56。之后，在多晶硅淀积前在有源区上形成薄栅氧化物36。
然后，淀积并图案化多晶硅层以形成栅电极34A和包围环34B，并且视需要形成引导环62。体区44用光刻、注入和热推进形成。体区44的深度远大于源区46(见图1)。由于多晶硅栅电极34A对注入的阻挡，体区44与多晶栅自对准。视需要，在形成N+源区和漏区前，可以有轻掺杂漏(LDD)延伸注入/推进和间隔物形成。在限定出源区46(N+)和漏区50(N+)后形成马蹄形区(48)(P+)。
淀积第二氧化层57(或第一介电质薄膜)。在第二氧化层57中刻蚀接触孔(体接触31、源极分接触32和漏极接触30)。在接触区域中形成硅化物层以减小接触电阻。施加第一互连金属层以填充接触孔并容许衬底40上形成的各种器件的互连。如果合适，泄漏抑制环62可与第一互连金属层一起形成。根据集成电路(IC)的需要，可形成更多的介电质层、通路孔和互连金属层。这些方法在所述领域是公知的，因此未在这里详细说明。
虽然已参考前述优选实施例具体展现及描述本发明，但本领域技术人员应理解，实践本发明时，在不脱离如以下权利要求限定的发明精神和范围情形下，可对这里所述发明实施例采用各种替换。意图是以下权利要求限定本发明的范围，并且在这些权利要求及其等价物范围内的方法和系统由它们涵盖。本发明的描述应理解为包括这里描述的要素的所有新颖和非显而易见的组合，并且本申请或后续申请中可以提出对这些要素的任何新颖的和非显而易见的组合的权利要求。前面的实施例是示例性的，没有单个特征或要素对于在本申请或后续申请中可能作为权利要求的所有可能组合都是必需的。当权利要求提到其等价物的“一个”或“第一”要素时，应将这种权利要求理解为包括一个或多个这种要素的组合，既不要求也不排除两个或多个这种要素。

Claims (5)

1.一种晶体管器件，包括：
第一型半导体材料的轻掺杂层(42)；
在所述轻掺杂层(42)内形成的第二型半导体材料的体区(44)；
在所述体区(44)内形成的所述第一型的源区(46)，所述源区(46)比所述轻掺杂层(42)掺杂得更多；
在所述轻掺杂层(42)内形成的所述第一型的漏区(50)，所述漏区(50)比所述轻掺杂层(42)掺杂得更多；
设置在所述体区(44)和所述漏区(50)之间的所述轻掺杂层(42)的漂移区(54)；
部分设置于所述漂移区(54)上方的栅电极(34A)，其中所述栅电极(34A)控制所述漂移区(54)内的电场；
包围环(34B)，部分设置在所述轻掺杂层(42)上方，其中所述栅电极(34A)和所述包围环(34B)完全包围所述漏区(50)，以及
在平面视图中呈马蹄形的所述第二型的区(48)，所述马蹄形区(48)在所述体区(44)内形成，所述马蹄形区(48)比所述体区(44)掺杂得更多，所述马蹄形区(48)部分包围所述源区(46)；
其中所述马蹄形区(48)与所述源区(46)和所述体区(44)电接触，
其中所述马蹄形区(48)和所述源区(46)彼此直接接触。
2.如权利要求1所述的器件，其中所述栅电极(34A)部分设置于薄氧化物(36)上并且部分设置于厚氧化物(56)上，其中从所述薄氧化物(36)上方在所述厚氧化物(56)上延伸的所述栅电极(34A)控制所述漂移区(54)内的电场以增大所述漏区(50)的雪崩击穿。
3.如权利要求1或2所述的器件，还包括部分包围所述源区(46)和所述漏区(50)的泄漏抑制环(62)，所述泄漏抑制环(62)电连接到所述源区(46)。
4.一种在第一型的衬底上制造晶体管器件的方法，包括步骤：
在该衬底内形成第二型的阱(42)；
在所述阱(42)内限定有源区；
形成所述有源区周围的厚场氧化物(56)；
在所述有源区上形成薄栅氧化物(36)；
形成栅电极(34A)和包围环(34B)，所述包围环(34B)部分设置在所述阱(42)上方，其中所述栅电极(34A)和所述包围环(34B)完全包围要形成漏区(50)的区域；
形成体区(44)和源区(46)；以及
形成源区(46)周围的区(48)，所述区(48)在平面视图中呈马蹄形，并且形成为使得所述马蹄形区(48)和所述源区(46)直接彼此接触。
5.如权利要求4所述的方法，其中所述栅电极(34A)部分设置于所述体区(44)和漂移区(54)上方。
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