CN103050512A - 非外延的高压绝缘n型ldmos器件结构 - Google Patents

非外延的高压绝缘n型ldmos器件结构 Download PDF

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CN103050512A
CN103050512A CN2011103105001A CN201110310500A CN103050512A CN 103050512 A CN103050512 A CN 103050512A CN 2011103105001 A CN2011103105001 A CN 2011103105001A CN 201110310500 A CN201110310500 A CN 201110310500A CN 103050512 A CN103050512 A CN 103050512A
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刘剑
段文婷
孙尧
陈瑜
陈华伦
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0886—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开了一种非外延的高压绝缘N型LDMOS器件结构；器件的p型井区域下方注入较浓的深N型井，并且伴随长时间深推井的工艺；在器件漏端扩展区和其他区域，采用较淡的浅N型井，并且伴随短时间深推井工艺。本发明采用两步不同N型井注入在器件不同的位置并且伴随不同的深推井的工艺，以替代传统的深N型井注入及深推井工艺，其工艺简单，容易实现。同时，相比采用埋层+外延的工艺方法，成本大幅下降。

Description

非外延的高压绝缘N型LDMOS器件结构
技术领域
本发明涉及一种集成电路制造技术。
背景技术
高压绝缘N型横向扩散金属氧化物半导体LDMOS器件由于设计灵活，而且比导通电阻(Rdson)低，响应速度快等优点，大量的应用在电源管理芯片设计中。绝缘N型LDMOS器件与普通N型LDMOS器件相比，在其p型井(P-body)区域下会进行深N型井(Deep Nwell，DNW)注入，以作为隔离用途。所以，绝缘N型LDMOS的源端(source，P+)和p型井引出端(bulk)所允许连接的电位可在0电位(ground)和漏端(drain)所加载的电位(一般为Vdd，线路最高电位)之间浮动。而普通N型LDMOS器件其源端(source，P+)和p型井引出端(bulk)只能允许接0电位(与P型衬底电位相一致)。因此，绝缘N型LDMOS器件设计较为灵活，用途广泛。但是，这种深N型井(Deep Nwell，DNW)隔离p型井(P-body)区域的结构给高压绝缘N型LDMOS器件的研发带来很大的困难。在考虑高压器件漏端扩展区(drain drift)满足器件耐压需求的同时，还要保证垂直方向上的PNP(Pbody-DNW-P型衬底)的穿通问题。
图1为传统的高压器件结构剖面图。区域1为证垂直方向上的PNP(Pbody-DNW-P型衬底)结构。区域2为高压器件漏端扩展区(drain drift)用以满足器件耐压需求。现有的工艺基本上是采用深推井(thermal drive-in)的工艺方法，使深N型井(Deep Nwell，DNW)在垂直方向上尽量深，来确保PNP(Pbody-DNW-P型衬底)的穿通。但是，由于深N型井(Deep Nwell，DNW)也涵盖高压器件漏端扩展区(drain drift)，用于满足器件耐压需求。图2。传统的绝缘N型LDMOS电势(electric potential)分布图。左图为垂直方向上的PNP(Pbody-DNW-P型衬底)穿通时电势(electric potential)分布图；右图为LDMOS横向(漏端扩展区)的电势(electric potential)分布图。图中白色虚线为耗尽区边界；白色实线为PN结边界；
图2为传统的绝缘N型LDMOS电势分(electric potential)布图。在确保垂直方向上的PNP(Pbody-DNW-P型衬底)穿通问题的同时，过深的N型井会导致器件漏端扩展区无法全耗尽(fully deplete)，器件的耐压只能依靠延长该区域的横向尺寸来满足。横向尺寸的增加直接会导致比导通电阻(Rdson)大幅增加，器件性能变差。器件的耐压要求越大，比导通电阻(Rdson)劣化越明显。这是目前高压绝缘N型LDMOS器件的设计难点所在。
针对这种情况，现有的专利技术大多采用N型埋层+外延的工艺方法来满足器件在垂直方向上的PNP(Pbody-DNW-P型衬底)的穿通要求；对横向器件漏端扩展区(drain drift)，采用Resurf的方法来进行设计，以期达到器件的耐压与比导通电阻(Rdson)的优化，从而提升器件性能。但是，成本问题又凸显出来。
发明内容
本发明所要解决的技术问题是提供一种，它可以本专利提出了一种新的非外延的高压绝缘N型LDMOS器件结构，用以解决垂直方向上的PNP(Pbody-DNW-P型衬底)穿通问题和横向漏端扩展区(drain drift)的耐压与比导通电阻(Rdson)的优化问题。
为了解决以上技术问题，本发明提供了一种非外延的高压绝缘N型LDMOS器件结构；器件的p型井(Pbody)区域下方注入较浓的深N型井(DeepNwell，DNW)，并且伴随长时间深推井的工艺；在器件漏端扩展区(drain drift)和其他区域，采用较淡的浅N型井(shallow Nwell，SNW)，并且伴随短时间深推井工艺。
本发明的有益效果在于：采用两步不同(多一步光罩)N型井注入在器件不同的位置并且伴随不同的深推井(thermal drive-in)的工艺，以替代传统的深N型井(Deep Nwell，DNW)注入及深推井工艺，其工艺简单，容易实现。同时，相比采用埋层+外延的工艺方法，成本大幅下降。
版图上浅N型井与深N型井保持0um～2um的间隔。
在器件漏端扩展区的浅N型井工艺形成浅的NP(SNW到P衬底)结深，利用P型衬底的作用使器件漏端扩展区全耗尽。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细说明。
图1是传统的绝缘N型LDMOS结构剖面图；
图2是为传统的绝缘N型LDMOS电势分(electric potential)布图。
图3本专利的绝缘N型LDMOS结构剖面图
图4本专利的N型LDMOS电势(electric potential)分布图。
具体实施方式
本专利提出了一种新的非外延的高压绝缘N型LDMOS器件结构，具体结构如图3：
在器件的p型井(Pbody)区域下方注入较浓的深N型井(Deep Nwell，DNW)，并且伴随强的(长时间)深推井(thermal drive-in)的工艺条件，以确保隔离和垂直方向上的PNP(Pbody-DNW-P型衬底)的穿通要求。
在器件漏端扩展区(drain drift)和其他区域，采用较淡的浅N型井(shallow Nwell，SNW)，并且伴随弱的(短时间)深推井(thermal drive-in)工艺条件。版图上，浅N型井与深N型井保持0um～2um的间隔(space)。在器件漏端扩展区的浅N型井工艺会形成浅的NP(SNW到P衬底)结深。
图4是本专利的N型LDMOS电势(electric potential)分布图。左图为垂直方向上的PNP(Pbody-DNW-P型衬底)穿通时电势(electric potential)分布图；右图为LDMOS横向(漏端扩展区)(electric potential)分布图。图中白色虚线为耗尽区边界；白色实线为PN结边界。
图4为本专利的高压器件电势(electric potential)分布图。从左图可以看出，由于深N型井的存在，器件垂直方向上的PNP(Pbody-DNW-P型衬底)穿通得到抑制。从右图可以看出，由于采用较淡的浅N型井参杂工艺和弱的推井(thermal drive-in)条件使NP结深(SNW到P衬底)变浅。这样P型衬底从底部辅助使器件漏端扩展区全耗尽(fully deplete)，从而在小的横向尺寸下保证器件的耐压，优化比导通电阻(Rdson)，使器件的性能得以提升。
本发明并不限于上文讨论的实施方式。以上对具体实施方式的描述旨在于为了描述和说明本发明涉及的技术方案。基于本发明启示的显而易见的变换或替代也应当被认为落入本发明的保护范围。以上的具体实施方式用来揭示本发明的最佳实施方法，以使得本领域的普通技术人员能够应用本发明的多种实施方式以及多种替代方式来达到本发明的目的。

Claims (5)

1.一种非外延的高压绝缘N型LDMOS器件结构；其特征在于，
器件的p型井区域下方注入较浓的深N型井，并且伴随长时间深推井的工艺；
在器件漏端扩展区和其他区域，采用较淡的浅N型井，并且伴随短时间深推井工艺。
2.如权利要求1所述的非外延的高压绝缘N型LDMOS器件结构；其特征在于，版图上浅N型井与深N型井保持0um～2um的间隔。
3.如权利要求1所述的非外延的高压绝缘N型LDMOS器件结构；其特征在于，在器件漏端扩展区的浅N型井工艺形成浅的NP结深，利用P型衬底的作用使器件漏端扩展区全耗尽。
4.如权利要求1所述的非外延的高压绝缘N型LDMOS器件结构；其特征在于，所述长时间深推井的工艺指1200oC，6到10小时的深推井的工艺。
5.如权利要求1所述的非外延的高压绝缘N型LDMOS器件结构；其特征在于，所述短时间深推井的工艺指1150oC，1到3小时深推井的工艺。
CN2011103105001A 2011-10-13 2011-10-13 非外延的高压绝缘n型ldmos器件结构 Pending CN103050512A (zh)

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CN104659100A (zh) * 2015-02-10 2015-05-27 上海华虹宏力半导体制造有限公司 隔离型nldmos器件及其制造方法

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CN104659100A (zh) * 2015-02-10 2015-05-27 上海华虹宏力半导体制造有限公司 隔离型nldmos器件及其制造方法

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