CN101960574B - 具有经改进架构的ldmos装置 - Google Patents

具有经改进架构的ldmos装置 Download PDF

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CN101960574B
CN101960574B CN200980108187.4A CN200980108187A CN101960574B CN 101960574 B CN101960574 B CN 101960574B CN 200980108187 A CN200980108187 A CN 200980108187A CN 101960574 B CN101960574 B CN 101960574B
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蔡军
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Fairchild Semiconductor Corp
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Abstract

一种LDMOS装置包含：第一导电率类型的衬底；所述衬底上的外延层；所述外延层的下部分中的与所述第一导电率类型相反的第二导电率类型的掩埋阱，所述外延层在掩埋层下面为所述第一导电率类型。所述装置进一步包含位于漏极与栅极氧化物上的栅极及源极两者之间的场氧化物且具有在所述外延层中所述掩埋阱上面的所述第二导电率类型的鞍形垂直掺杂梯度，使得所述外延层中所述掩埋阱上面及所述场氧化物的中央部分下面的掺杂剂浓度低于所述场氧化物的最靠近所述漏极及最靠近所述栅极的边缘处的掺杂剂浓度。

Description

具有经改进架构的LDMOS装置
技术领域
本发明涉及高电压、高功率MOSFET及低电压、低功率MOSFET。
背景技术
将高电压、高功率MOSFET及低电压、低功率MOSFET组合在集成电路中通常涉及不能有效地用于形成低功率MOSFET的用于形成高功率MOSFET的处理步骤及不能有效地用于形成高功率MOSFET的用于形成低功率MOSFET的其它处理步骤。因为减小集成电路制造中的处理步骤的数目是恒定的目标，所以高度期望用于两种类型装置之共用架构。
发明内容
本发明在其一个形式中包括：LDMOS装置，其具有第一导电率类型的衬底；所述衬底上的起始外延层；所述起始外延层中的与所述第一导电率类型相反的第二导电率类型的掩埋阱，所述掩埋阱在所述第一导电率类型的所述起始外延层的顶部中；构建于所述起始外延层的顶部上的内嵌外延层，及位于漏极与栅极氧化物上的栅极及源极两者之间的场氧化物；及所述内嵌外延层中所述掩埋阱上面的所述第二导电率类型的鞍形垂直掺杂梯度，使得所述内嵌外延层中所述掩埋阱上面及所述场氧化物的中央部分下面的掺杂剂浓度低于所述场氧化物的最靠近所述漏极及最靠近所述栅极的边缘处的掺杂剂浓度。
本发明在其另一形式中包括LDMOS装置，其包含：第一导电率类型的衬底；所述衬底上的起始外延层；所述起始外延层的顶部区域中的与所述第一导电率类型相反的第二导电率类型的掩埋阱，所述掩埋阱在所述第一导电率类型的所述起始外延层的顶部中；构建于所述起始外延层的顶部上的内嵌外延层；及所述内嵌外延层中所述掩埋阱上面的所述第二导电率类型的垂直掺杂梯度，其在靠近所述掩埋层处及在所述内嵌外延层的顶部处具有比在所述内嵌外延区的中间区中高的掺杂剂浓度；及所述内嵌外延层的上部分中的源极及漏极，所述内嵌外延层上的栅极氧化物及所述栅极氧化物上的栅极电极。
本发明在其又一形式中包括一种技术，其包括高电压LDMOS，其具有第一导电率类型的衬底；所述衬底上的起始外延层；所述起始外延层的顶部区中的与所述第一导电率类型相反的第二导电率类型的掩埋阱，所述起始外延层为所述第一导电率类型；构建于所述起始外延层的顶部上的内嵌外延层；位于漏极与栅极氧化物上的栅极及源极两者之间的场氧化物；及所述内嵌外延层中所述掩埋阱上面的所述第二导电率类型的鞍形垂直掺杂梯度，使得所述外延层中所述掩埋阱上面及所述场氧化物的中央部分下面的掺杂剂浓度低于所述场氧化物的最靠近所述漏极及最靠近所述栅极的边缘处的掺杂剂浓度。所述技术还包含低电压LDMOS，其包括：所述衬底上的起始外延层；所述起始外延层的所述顶部区中的与所述第一导电率类型相反的第二导电率类型的掩埋阱，所述外延层为所述第一导电率类型；构建于所述起始外延层的顶部上的内嵌外延层；及所述内嵌外延层中所述掩埋阱上面的所述第二导电率类型的垂直掺杂梯度，其在靠近所述掩埋层处及在所述外延层的顶部处具有比在所述外延区的中间区中高的掺杂剂浓度；及所述内嵌外延层的上部分中的源极及漏极，所述内嵌外延层中的栅极氧化物及所述栅极氧化物上的栅极电极。
在又一形式中，本发明包含一种形成LDMOS装置的方法。所述方法包括以下步骤：在第一导电率类型的衬底上形成起始外延层，其中在所述起始外延层的顶部区中具有与所述第一导电率类型相反的第二导电率类型的掩埋阱；在所述第一导电率类型起始外延层的顶部上形成第一导电率类型内嵌外延层；在高电压LDMOS装置的作用区域中，于所述内嵌外延层的顶部边缘中形成场氧化物；使第一、第二及第三垂直植入物进入到所述外延层中，所述场氧化物屏蔽所述外延层免受所述第三植入物影响；及形成源极、漏极及栅极氧化物上的栅极，其中所述漏极在所述场氧化物的一个侧上，且所述栅极及源极在所述场氧化物的相对侧上。
在额外形式中，本发明包含一种形成LDMOS的方法。所述方法包括以下步骤：在第一导电率类型的衬底上形成起始外延层，其中在所述外延层的顶部中具有与所述第一导电率类型相反的第二导电率类型的掩埋阱；在第一导电率类型的所述起始外延层的顶部上形成第一导电率类型的内嵌外延层；使第一、第二及第三垂直植入物进入到所述外延层中，所述第一植入物位于所述外延层的靠近所述掩埋层的部分中，所述第二植入物浅于所述第一植入物，且所述第三植入物浅于所述第二植入物，所述第二植入物具有比所述第一及第三植入物低的掺杂剂浓度；及形成源极、漏极及栅极氧化物上的栅极，其中所述漏极在所述场氧化物的一个侧上，且所述栅极及源极在所述场氧化物的相对侧上。
在又额外形式中，本发明包含在第一导电率类型的衬底上形成高电压LDMOS及低电压LDMOS的方法。形成所述高电压LDMOS的方法包括以下步骤：在所述衬底上形成起始外延层，其中在所述起始外延层中具有与所述第一导电率类型相反的第二导电率类型的掩埋阱；在所述第一导电率类型的所述起始外延层的顶部上形成第一导电率类型的内嵌外延层；在所述高电压LDMOS的作用区域中，于所述外延层的顶部边缘中形成场氧化物；使第一、第二及第三垂直植入物进入到所述外延层中，所述场氧化物屏蔽所述外延层免受所述第三植入物影响；及形成源极、漏极及栅极，其每一者是针对两个装置同时形成的，其中所述漏极在所述场氧化物的一个侧上，且所述栅极及源极在所述场氧化物高电压LDMOS的相对侧上。形成低电压LDMOS的方法包括以下步骤：在所述衬底上形成内嵌外延层，其中在所述起始外延层中具有与所述第一导电率类型相反的第二导电率类型及第一掺杂剂浓度的掩埋阱；在第一导电率类型的所述起始外延层的顶部上形成第一导电率类型的内嵌外延层；在所述高电压LDMOS的作用区域中，于所述外延层的顶部边缘中形成场氧化物；使第一、第二及第三垂直植入物进入到所述外延层中，所述场氧化物屏蔽所述外延层免受所述第三植入物影响；及形成源极、漏极及栅极，其每一者是针对两个装置同时形成，其中所述漏极在所述场氧化物的一个侧上，且所述栅极及源极在所述场氧化物高电压LDMOS的相对侧上。
附图说明
通过结合附图阅读以下更详细说明，将更好地了解前文所述及其它特征、特性、优点及本发明大体内容。
图1A及1B是根据本发明实施例的高电压LDMOS及低电压LDMOS的相应示意图；
图1C是根据本发明实施例的形成在同一衬底上的高电压LDMOS及低电压LDMOS的示意图；
图2A及2B是用于图1A及1B中所示的高电压LDMOS及低电压LDMOS的早期过程步骤的相应示意图；
图3A及3B分别是用于图1A及1B中所示高电压LDMOS及低电压LDMOS的迟于图2A及2B中所示的过程步骤的过程步骤的示意图；
图4是用于图1A中所示的高电压LDMOS的迟于图3A及3B中所示的过程步骤的过程步骤的示意图；
图5A及5B分别是用于图1A及1B中所示的高电压LDMOS及低电压LDMOS的迟于图3A、3B及4中所示的过程步骤的过程步骤的示意图；
图6A及6B分别是用于图1A及1B中所示的高电压LDMOS及低电压LDMOS的迟于图5A及5B中所示的过程步骤的过程步骤的示意图；
图7A及7B分别是用于图1A及1B中所示的高电压LDMOS及低电压LDMOS的迟于图6A及6B中所示的过程步骤的过程步骤的示意图；
图8A及8B分别是用于图1A及1B中所示的高电压LDMOS及低电压LDMOS的迟于图7A及7B中所示的过程步骤的过程步骤的示意图；
图9A及9B分别是用于图1A及1B中所示的高电压LDMOS及低电压LDMOS的迟于图8A及8B中所示的过程步骤的过程步骤的示意图；
图10A及10B分别是用于图1A及1B中所示的高电压LDMOS及低电压LDMOS的迟于图9A及9B中所示的过程步骤的过程步骤的示意图；
图11是两个图1A中所示的高功率LDMOS装置或者两个图1B中所示的低功率LDMOS装置的源极区域的界面的示意图；
图12A及12B分别是根据本发明的5伏LDMOS的正向电压与电流特性及反向电压与电流特性的图形表示；
图13A及13B分别是根据本发明的12伏LDMOS的正向电压与电流特性及反向电压与电流特性的图形表示；
图14A及14B分别是根据本发明的20伏LDMOS的正向电压与电流特性及反向电压与电流特性的图形表示；
图15A及15B分别是根据本发明的40伏LDMOS的正向电压与电流特性及反向电压与电流特性的图形表示；
图16A及16B分别是根据本发明的60伏LDMOS的正向电压与电流特性及反向电压与电流特性的图形表示；及
图17A及17B分别是根据本发明的80伏LDMOS的正向电压与电流特性及反向电压与电流特性的图形表示。
应了解，出于清晰的目的且在认为适当时，已在图中重复参考编号以指示对应的特征。此外，在某些情况下，已使图式中各种物体的相对大小发生变形以更清楚地显示本发明。
具体实施方式
现在转向该等图式。图1A及1B是根据本发明的一个实施例的高电压LDMOS 30及根据本发明的另一实施例的低电压LMOS 32的相应示意图。然而，本发明可实施为不同形式而不应视为仅限于本文所阐明的实施例。此外，提供此等实施例旨在使本揭示内容透彻且完整，且向所属领域的技术人员全面传达本发明的范围。
高电压LDMOS 30及低电压LDMOS 32具有第一导电率类型的经高度掺杂衬底34。术语“第一导电率类型”及“第二导电率类型”是指相反的导电率类型，例如N或P型，然而，本文中所描述及图解说明的每一实施例也包含其互补实施例。在本文中所描述的实施例中，所述第一导电率类型是P型，而所述第二导电率类型是N型。因此，经高度掺杂的衬底34将被描述为P+衬底以促进对图1A及1B的说明。外延(epi)层36生长在衬底34上，所述外延层包含起始外延及内嵌外延，且N型掩埋阱38形成在为外延层36的下部分的起始外延的顶部区域中。
内嵌外延构建于起始外延的顶部上形成N型掩埋阱38之后，然后是场氧化物62形成在高电压LDMOS 30的漂移区的顶部上。使三种N型植入物形成于内嵌外延中，所述内嵌外延是高电压LDMOS 30及低电压LDMOS 32中的外延层36的上部分。第一植入物40最靠近掩埋阱38，第二植入物42浅于第一植入物40，且第三植入物44浅于第二植入物42。图1A及1B中所示的作用区域中的每一者位于外延层36的上部分中且包含形成于外延层36的上表面下面的P阱46及形成在P阱46与外延层36的上表面之间的P本体48。P本体48是使用低倾角植入而形成，所述低倾角植入可以为7°，但并不限于低倾角植入。与P本体48的内部曲面邻接的是N+源极间隔件50，其是使用与P本体48相同的掩模通过双重植入形成，一个植入是针对P本体48且另一个植入是针对N+源极间隔件50。体P+52形成在P阱46及P本体48中且可与N+源极间隔件50邻接、与氧化物间隔件72自对准或具有到氧化物间隔件的间隔。源极硅化物54形成在外延层36的上表面中体P+52上方且与体P+52及N+源极间隔件50接触。
N阱56形成在外延层36的另一部分中，所述另一部分可自外延层36的上表面朝下延伸。N+漏极58形成在N阱56中且由漏极硅化物60覆盖顶部。
在高电压LDMOS 30中，场氧化物62形成在外延层36的上表面中P本体48与N阱56之间的区的一部分上面，且可延伸到N阱56的一部分中。阶梯式栅极氧化物64位于外延层36的上表面上源极硅化物54与场氧化物62之间。外延层36的表面上的另一氧化物层66从场氧化物62延伸到漏极硅化物60。栅极68(其包含可为经掺杂多晶硅的栅极电极70)位于阶梯式栅极氧化物64的一部分上。栅极电极70在场氧化物62的一部分的顶部上延伸以形成多晶硅场镀层。与常规LDMOS装置相比，阶梯式栅极氧化物64与栅极电极70的多晶硅场镀层的组合减小表面电场。栅极68包含在N+源极间隔件50上方的第一栅极侧壁氧化物72及在场氧化物62上方的第二栅极侧壁氧化物74。栅极68可具有形成在栅极电极70的顶部表面中的栅极硅化物层76。
在低电压LDMOS 32中，阶梯式栅极氧化物80位于外延层36的上表面上源极硅化物54与漏极硅化物60之间。栅极82(其包含可为经掺杂的多晶硅的栅极电极84)位于阶梯式栅极氧化物80的一部分上。栅极82包含在N+源极间隔件50上方于薄栅极氧化物的顶部上的第一栅极侧壁氧化物86，及在厚栅极氧化物的顶部上的第二栅极侧壁氧化物88。栅极82可具有形成在栅极电极84的顶部表面中的栅极硅化物层90。
图1C是根据本发明的实施例形成在同一衬底34上的高电压LDMOS 30及低电压LDMOS 32的示意图。
图2A及2B分别显示在制造高电压LDMOS 30及低电压LDMOS 32中的一个阶段，其中在衬底34上已生长薄的起始P-外延层92，及在P-外延层92中已形成掩埋阱38。高电压LDMOS 30中的掩埋阱38可具有在0.5x1016cm-3至5.5x1016cm-3范围中的掺杂剂浓度，其中优选的掺杂剂浓度约为2.5x1016cm-3，且低电压LDMOS 32中的掩埋阱38在一个实施例中可具有在5.5x1016cm-3至5X1018cm-3范围中的掺杂剂浓度，其中优选的掺杂剂浓度约为1.0x1017cm-3，且在低电压LDMOS 32的另一实施例中可具有在5x1018cm-3至5x1019cm-3范围中的掺杂剂浓度，其中优选的掺杂剂浓度约为7.0x1018cm-3。
图3A及3B显示在用以完成具有在p-外延层36的下部分中的掩埋阱38的P-外延36的另一外延生长操作之后的高电压LDMOS 30及低电压LDMOS 32。
图4显示在制造高电压LDMOS 30中在场氧化物62已形成于外延层36的上表面中之后的另一阶段。
图5A及5B分别显示在制造高电压LDMOS 30及低电压LDMOS 32中在已形成三种植入物40、42及44之后的又一阶段，所述植入物可为逆行植入物。第一植入物40(其从外延层36的顶部表面延伸到接近掩埋层38的所规定深度)可具有在0.5x1016cm-3至3x1017cm-3范围中的掺杂剂浓度，其中优选的掺杂剂浓度约为1.2x1016cm-3。第二植入物42(其从外延层36的顶部表面延伸到浅于第一植入物40的所规定深度)可具有在1x1015cm-3至1x1017cm-3范围中的掺杂剂浓度，其中优选的掺杂剂浓度约为7.0x1015cm-3。第三植入物44(其从外延层36的顶部表面延伸到浅于第二植入物42的所规定深度)可具有在3x1015cm-3至2x1017cm-3范围中的掺杂剂浓度，其中优选的掺杂剂浓度约为1.0x1016cm-3。
在低电压LDMOS 32中，三种植入物形成直线掺杂剂区。然而，在高电压LDMOS30中，场氧化物吸收所植入离子的一些能量，且掺杂剂层具有鞍形状以使其在场氧化物62下方的区中比在没有被场氧化物62遮蔽的区中浅。因此，第三植入物44在场氧化物62下方没有延伸到外延层36中，且因此，在场氧化物62下方的外延层比低电压LDMOS 32中的外延层36的表面层为经较轻的掺杂N型。高电压LDMOS 30的漂移区是横向区，其在场氧化物62下面且由外延层36中最靠近P本体48的第三植入物44限界且由外延层36中最靠近N阱56的第三植入物44或者在N阱56在场氧化物62下方延伸足够远以将第三植入物44的任何部分包含在场氧化物62的N阱56侧上时由N阱56限界。因此，假设外延层36中的掺杂剂分布适于高电压LDMOS及低电压LDMOS，高电压LDMOS 30在场氧化物62下方具有相比于低电压LDMOS 32的表面层经相对轻掺杂的漂移区，且两个装置30、32中的不同漂移区掺杂分布可在同一过程步骤中构建。
而且，高电压LDMOS 30中的鞍形第一及第二植入物40及42分别和掩埋阱38在本发明的实施例中提供：(a)相比于常规LDMOS装置相对较高的源极对衬底击穿电压(尽管其具有薄的外延层)，(b)由于薄的外延层及p+衬底所致相比于常规LDMOS装置相对较低的寄生NPN电流放大系数，及(c)由于逆行漂移掺杂、分级漏极掺杂及具有以下图式中所示的阶梯本体的N+源极间隔件所致的相比于常规LDMOS装置的改进电流分布，此等优点一起提供相比于常规LDMOS装置大的安全操作区域(SOA)。
图6A及6B显示已形成P阱46及N阱56的高电压LDMOS 30及低电压LDMOS32。
图7A及7B分别显示对高电压LDMOS 30及低电压LDMOS 32添加阶梯式栅极氧化物64、80及栅极电极70、84。图8A及8B显示图7A及7B在已使用低倾角植入形成P本体48及N+源极间隔件50之后的结构。P本体48及N+源极间隔件50两者与栅极电极70、84自对准。P本体植入倾角可以为7°，植入能量可为相对低，约60kev，且植入掺杂剂可以为硼。
因此，在不使温度、湿度及偏压(THB)和高温反向偏压(HTRB)特性因P本体硼植入物到栅极氧化物中的渗透而降级的情况下，P本体48植入可借助精细工艺规范而与薄栅极多晶硅及薄栅极氧化物兼容。低倾角植入减轻栅极及光致抗蚀剂堆叠的遮蔽效应，因此，P本体及N+源极间隔件掩模开口可为极小，从而减小这些装置的源极区域。在构建于阶梯本体(其由P阱46及P本体48构成)中的侧壁氧化物72、86之下的N+源极间隔件50减轻本征NPN基极中的过早穿通及电荷减少。
在图9A及9B中，已形成栅极氧化物侧壁72、74、86及88。图10A及10B分别显示在已形成N+漏极58及体P+区52之后的高功率LDMOS 30及低功率LDMOS32。体P+区52与栅极氧化物侧壁72及86自对准。因此，有效的N+源极仅在氧化物侧壁间隔件86之下。在其中侧壁氧化物可为太窄而不能防止体P+掺杂剂渗透沟道区域的另一实施例(图式中未显示)中，体P+区52可经形成在体P+区52与侧壁氧化物72、86之间具有间隔。N+漏极58、第一、第二及第三植入物40、42、44分别与N阱38形成分级漏极掺杂分布。
图11是两个条带高功率LDMOS装置30或两个条带低功率LDMOS装置32的源极区域96的界面的实例的实例性示意图94。共同自对准体P+52及P阱46有利于最小间距大小，其在一个实施例中基本上等于仅具有N+源极的常规低电压nmos源极区的间距及栅极电极84之间的最小间隔。低电压LDMOS 32的间距大小在一个实施例中可如使用0.35μm过程的0.5μm一样低。另外，高电压LDMOS 30的源极间距在一个实施例中等于常规低电压CMOS装置的源极间距。
图12A及12B是5伏低功率LDMOS 32的实施例的初始硅结果的图形表示，其显示针对多个栅极对源极电压的关于漏极对源极电压的漏极电流密度Ids(mA/mm)(图12A)，及关于反向偏压Vds的漏极电流(Ids)(图12B)。具有图12A及12B中所示的特性的低功率LDMOS 32具有2.34mΩ.mm2的Rdson.A。以下表针对图12A中所示的曲线中的每一者识别对应的栅极对源极电压(Vgs)：
如图12B中所示，反向偏压漏极对源极电流120靠近零直到反向偏压电压达到大约11伏为止。
图13A及13B是12伏低电压LDMOS 32的实施例的初始硅结果的图形表示，其显示针对多个栅极对源极电压的关于Vds的电流密度Ids(mA/mm)(图13A)，及关于反向偏压Vds的漏极电流，Ids(图13B)。具有图13A及13B中所示的特性的低功率LDMOS 32具有11.1mΩmm2的Rdson.A。以下表针对图12A中所示的曲线中的每一者识别对应的Vgs：
如图13B中所示，反向偏压漏极对源极电流132接近零直到反向偏压电压达到大约23伏为止。
图14A及14B是20伏低功率LDMOS 32的实施例的初始硅结果的图形表示，其显示针对多个栅极对源极电压的关于Vds的电流密度Ids(mA/mm)(图14A)，及关于反向偏压Vds的漏极电流，Ids(图14B)。具有图14A及14B中所示的特性的低功率LDMOS 32具有22.2mΩmm2的Rdson.A。以下表针对图14A中所示的曲线中的每一者识别对应的Vgs：
如图14B中所示，反向偏压漏极对源极电流154靠近零直到反向偏压电压达到大约34伏为止。
图15A及15B是40伏高功率LDMOS 30的实施例的初始硅结果的图形表示，其显示针对多个栅极对源极电压的关于Vds的电流密度，Ids(mA/mm)(图15A)，及关于反向偏压Vds的漏极电流，Ids(图15B)。具有图15A及15B中所示的特性的高功率LDMOS 30具有53.4mΩmm2的Rdson.A。以下表针对图15A中所示的曲线中的每一者识别对应的Vgs：
  参考编号   Vgs
  156   1.5V
  158   2.0V
  160   2.5V
  162   3.0V
  164   3.5V
  166   4.0V
  168   4.5V
  170   5.0V
  172   5.5V
如图15B中所示，反向偏压漏极对源极电流174靠近零直到反向偏压电压达到大约55伏为止。
图16A及16B是60伏高功率LDMOS 30的实施例的初始硅结果的图形表示，其显示针对多个栅极对源极电压的关于Vds的电流密度，Ids(mA/mm)(图16A)，及关于反向偏压Vds的漏极电流，Ids(图16B)。具有图16A及16B中所示的特性的高功率LDMOS 30具有97.3mΩmm2的Rdson.A。以下表针对图16A中所示的曲线中的每一者识别对应的Vgs：
  参考编号   Vgs
  176   1.5V
  178   2.0V
  180   2.5V
  182   3.0V
  184   3.5V
  186   4.0V
  188   4.5V
  190   5.0V
  192   5.5V
如图16B中所示，反向偏压漏极对源极电流194靠近零直到反向偏压电压达到大约77伏为止。
图17A及17B是80伏高功率LDMOS 30的实施例的初始硅结果的图形表示，其显示针对多个栅极对源极电压的关于Vds的电流密度，Ids(mA/mm)(图17A)及关于反向偏压Vds的漏极电流，Ids(图17B)。具有图17A及17B中所示的特性的高功率LDMOS 30具有155.6mΩmm2的Rdson.A。以下表针对图17A中所示的曲线中的每一者识别对应的Vgs：
  参考编号   Vgs
  196   1.0V
  198   1.5V
  200   2.0V
  202   2.5V
  204   3.0V
  206   3.5V
  208   4.0V
  210   4.5V
  212   5.0V
  214   5.5V
如图17B中所示，反向偏压漏极对源极电流216靠近零直到反向偏压电压达到大约97伏为止。
尽管已参考特定实施例描述本发明，但所属领域的技术人员将了解可在不背离本发明的范围的前提下做出各种改变且等效物可替代其元件。另外，可在不背离本发明的范围的前提下做出众多修改以使特定情景或材料适应本发明的教示内容。
因此，本文并不打算将本发明限于所揭示作为实施本发明最佳设想模式的特定实施例，而是打算使本发明包含所有属于以上权利要求书的范围及精神内的实施例。

Claims (11)

1.一种LDMOS装置，其包括：
a)第一导电率类型的衬底；
b)所述衬底上的外延层；
c)所述外延层的下部分中的与所述第一导电率类型相反的第二导电率类型的掩埋阱，所述外延层在所述掩埋阱下面为所述第一导电率类型；
d)场氧化物，漏极在所述场氧化物的一侧上且栅极氧化物上的栅极及源极在所述场氧化物的相对侧上；
e)在所述外延层中所述掩埋阱上面的所述第二导电率类型的鞍形垂直掺杂梯度，使得所述外延层中所述掩埋阱上面及所述场氧化物的中央部分下面的掺杂剂浓度低于所述场氧化物的最靠近所述漏极及最靠近所述栅极的边缘处的掺杂剂浓度；及
f)位于源极区中的P阱及位于漏极区中的N阱。
2.如权利要求1所述的装置，其中所述梯度从所述掩埋阱向上到所述场氧化物单调地降低。
3.如权利要求1所述的装置，其中所述栅极氧化物为阶梯式栅极氧化物。
4.如权利要求1所述的装置，其中所述源极为位于所述栅极的侧壁氧化物下方且与所述栅极的边缘自对准的N+源极间隔件。
5.如权利要求4所述的装置，其进一步包含与所述N+源极间隔件接触且与所述栅极的所述边缘自对准的P本体。
6.如权利要求5所述的装置，其进一步包含与所述P本体及所述N+源极间隔件接触且与所述栅极的侧壁氧化物自对准的P+体。
7.一种LDMOS装置，其包括：
a)第一导电率类型的衬底；
b)所述衬底上的外延层；
c)所述外延层的下部分中的与所述第一导电率类型相反的第二导电率类型的掩埋阱，所述外延层在所述掩埋阱下面为所述第一导电率类型；
d)所述外延层中所述掩埋阱上面的所述第二导电率类型的垂直掺杂梯度，所述垂直掺杂梯度在靠近所述掩埋阱处及在所述外延层的顶部处具有比在所述外延层的中间区中高的掺杂剂浓度；
e)所述外延层的上部分中的源极及漏极，所述外延层上的栅极氧化物及所述栅极氧化物上的栅极电极；及
f)位于源极区中的P阱及位于漏极区中的N阱。
8.如权利要求7所述的装置，其中所述栅极氧化物为阶梯式栅极氧化物。
9.如权利要求7所述的装置，其中所述源极为位于所述栅极的侧壁氧化物下方且与所述栅极的边缘自对准的N+源极间隔件。
10.如权利要求9所述的装置，其进一步包含与所述N+源极间隔件接触且与所述栅极的所述边缘自对准的P本体。
11.如权利要求10所述的装置，其进一步包含与所述P本体及所述N+源极间隔件接触且与所述栅极的侧壁氧化物自对准的P+体。
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Patentee before: Ficho Semiconductor Co.