CN1391278A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN1391278A
CN1391278A CN02123018A CN02123018A CN1391278A CN 1391278 A CN1391278 A CN 1391278A CN 02123018 A CN02123018 A CN 02123018A CN 02123018 A CN02123018 A CN 02123018A CN 1391278 A CN1391278 A CN 1391278A
Authority
CN
China
Prior art keywords
mentioned
semiconductor chip
semiconductor
chip
outer electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN02123018A
Other languages
English (en)
Other versions
CN1267993C (zh
Inventor
长尾浩一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nova Semiconductor Ltd
Sony Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of CN1391278A publication Critical patent/CN1391278A/zh
Application granted granted Critical
Publication of CN1267993C publication Critical patent/CN1267993C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85455—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

具备：具有模片底座10及引线11的引线框；具有第1内部电极1及第1外部电极3，安装在模片底座上的第1半导体芯片4；具有第2内部电极6及第2外部电极7，以使表面对置的方式接合到第1半导体芯片上，利用凸点2、5把第2内部电极与第1内部电极连接起来的第2半导体芯片8；把引线与第1、第2电极连接起来的第1、第2金属丝12、13；以及密封树脂14。两个半导体芯片的各端缘在实质平行的状态下偏移，各半导体芯片的端部的一部分从另一方半导体芯片的端缘露出，在其露出了的区域中配置了外部电极。不管两个半导体芯片的外形尺寸的关系如何，都可以有效地电连接半导体芯片与引线框之间。

Description

半导体装置及其制造方法
技术领域
本发明涉及具有以使主面互相对置的方式、把在主面上分别形成了LSI的第1 LSI芯片与第2 LSI芯片接合起来的安装体的半导体装置及其制造方法。
背景技术
为了谋求半导体集成电路装置的低成本化及小型化，提出了通过倒装接合方式把2个LSI芯片互相接合起来形成了安装体的COC(芯片上的芯片)型半导体装置。在各LSI芯片上，形成了例如具有不同功能的LSI或利用不同工艺形成了的LSI。下面，参照图8，说明这样的半导体装置。
在图8所示的半导体装置中，安装着第1 LSI芯片101及第2 LSI芯片104。在第1 LSI芯片101中的形成了LSI(未图示)的主面上，形成了内部电极102及外部电极103。在第2 LSI芯片104中的形成了LSI(未图示)的主面上，形成了凸点105。在把内部电极102与凸点105连接起来的状态下，通过倒装接合方式把第1 LSI芯片101与第2 LSI芯片104接合起来。在第1 LSI芯片101与第2 LSI芯片104之间，填充了绝缘性树脂106。利用焊锡把第1 LSI芯片101固定在引线框的模片底座107上。利用由金属丝构成的接合焊丝109把第1LSI芯片101的外部电极103与引线框的内部引线108导电性地连接起来。利用密封树脂110把第1 LSI芯片101、第2 LSI芯片104、模片底座107、内部引线108及接合焊丝109密封起来。
上述半导体装置按下述方式来制造。首先，在周缘部上形成了外部电极103的第1 LSI芯片101上的中央部上涂布绝缘性树脂106。其次，把第2 LSI芯片104按压在第1 LSI芯片101上，在把内部电极102与凸点105连接起来的状态下，把第1 LSI芯片101与第2 LSI芯片104接合起来。
其次，利用接合焊丝109，连接第1 LSI芯片101的外部电极103与引线框的内部引线108。其次，利用密封树脂110，密封第1 LSI芯片101、第2 LSI芯片104、模片底座107、内部引线108及接合焊丝109。最后，成形从密封树脂110伸出的引线框的外部引线111，由此完成了半导体装置。
可是，在上述半导体装置的结构中，第2 LSI芯片104的外形变大，当它变成比配置在下侧的第1 LSI芯片101的外形大时，对于将其安装到引线框上以构成半导体装置来说，产生了结构上的制约。特别是，利用接合焊丝109连接第1 LSI芯片101的外部电极103与引线框的内部引线108变得困难。
例如，在作为上侧的第2 LSI芯片104使用了存储器芯片的情况下，伴随着将来存储器芯片的容量增加，存储器芯片的外形增大。另一方面，在作为下侧的第1 LSI芯片101使用了逻辑芯片的情况下，由于工艺的微细化，逻辑芯片的外形减小。因而，存储器芯片的外形变成比逻辑芯片的外形大。此时，上述问题在高密度半导体安装技术中成为重要的障碍。
与此不同，在特开平10-256472号公报中公开了图9所示那样的结构的半导体装置。第2 LSI芯片104a具有与下侧的第1 LSI芯片101a同一的外形。在互相旋转了45°的状态下，把两个芯片接合起来。因而，剖开后的两个芯片的角部112、113不重叠地露出来了。通过分别在该角部112、113上设置外部电极(未图示)，尽管第2 LSI芯片104的外形增大，还是可以布线。
可是，在利用了这样的角部112、113的布线中，可以使用的外部电极的个数极为有限，进行能够满意的导电性的连接是困难的。这是因为，通过芯片相互旋转而露出的面积较小。此外，如果考虑到两个芯片间填充的绝缘性树脂从端部溢出而形成所谓凸起的情况，则可以利用的露出面积的余量会更小。
发明内容
本发明之目的在于，解决上述现有的课题，提供即使是上侧的半导体芯片的外形尺寸比下侧的半导体芯片大的COC结构，也可以有效地连接半导体芯片与引线框之间的半导体装置及其制造方法。
本发明的半导体装置，具备：引线框，具有模片底座部及设置在上述模片底座部附近的引线部；第1半导体芯片，在表面上具有第1内部电极及第1外部电极，将其安装在上述模片底座部上；第2半导体芯片，在表面上具有第2内部电极及第2外部电极，以使表面对置的方式将其接合到上述第1半导体芯片上，利用凸点把上述第2内部电极与上述第1内部电极连接起来；第1及第2金属丝，分别把上述引线部与上述第1及上述第2外部电极连接起来；以及密封树脂，把上述引线部、上述第1及第2半导体芯片以及上述第1及第2金属丝密封起来。以使其各端缘在实质平行的状态下相互偏移的方式把上述第1及第2半导体芯片迭合，上述第1及第2半导体芯片的端部的一部分超出另一方半导体芯片的端缘，在其超出了的区域中分别配置了上述第1及第2外部电极。
按照该结构，由于各外部电极不重叠地露出，故可用金属丝无障碍地连接引线框的引线部与各外部电极，所谓各端缘实质平行的状态，包含在COC封装工序中的对准精度范围内，各端缘相互保持角度的情况。具体而言，若在±1度以下，则即使各端缘相成角度也会得到实用上的充分效果。
此外，可以把半导体装置作成下述结构，上述第1半导体芯片的相对置的一对端部超出上述第2半导体芯片的端缘，上述第2半导体芯片的相对置的一对端部超出上述第1半导体芯片的端缘。按照该结构，可以简便地层叠大多为长方形芯片的存储器元件与系统LSI等。再有，由于存储器件大多具有把电极连接端集中于2个边上的结构，故可容易地使用现有的存储器元件。
或者，可以把半导体装置作成下述结构，上述第1半导体芯片的一个端部超出上述第2半导体芯片的端缘，上述第2半导体芯片的3个端部超出上述第1半导体芯片的端缘。按照该结构，为了把第2半导体芯片与第1半导体芯片的电路径作成最短，可以部分地通过凸点进行导电性的连接。
或者，可以把半导体装置作成下述结构，把上述第1半导体芯片的与上述第2半导体芯片在大致对角线方向上偏移后配置，上述第1半导体芯片的相邻的2个端部及上述第2半导体芯片的相邻的2个端部超出了。按照该结构，可以简便地层叠正方形的芯片。
在上述半导体装置的结构中，在上述第1半导体芯片与上述第2半导体芯片的间隙中填充绝缘性树脂，上述绝缘性树脂的端部从上述第1半导体芯片或上述第2半导体芯片的端部突出而形成凸起，上述第1及第2外部电极位于上述凸起端部的外侧是较为理想的。由此，可以有效地使用第1及第2外部电极的面积。
为此，可以把半导体装置作成下述的结构，当假定在上述第1半导体芯片/上述第2半导体芯片超出了的部分中的、上述第1半导体芯片/上述第2半导体芯片的厚度与上述绝缘性树脂的厚度相加后的厚度为t，从上述第2半导体芯片/上述第1半导体芯片的端缘到上述第1外部电极/第2外部电极的内侧端缘的距离为L时，满足t＜L的条件。
在实用上，半导体装置的上述第2半导体芯片/上述第1半导体芯片的端部超出了上述第1半导体芯片/上述第2半导体芯片的端缘的长度为0.3mm以上到2.0mm以下，是较为理想的。
可以把半导体装置作成下述结构，上述第1半导体芯片是逻辑芯片或模拟芯片，上述第2半导体芯片是其外形面积比上述第1半导体芯片大的存储器芯片。此时，也可以把半导体装置作成下述结构，上述第2半导体芯片的至少1个边比上述第1半导体芯片的边更长。
本发明的半导体装置的制造方法是，把在表面上具有第1内部电极及第1外部电极的第1半导体芯片、与在表面上具有第2内部电极及第2外部电极的第2半导体芯片迭合而接合起来，作成半导体安装体，把上述半导体安装体安装到引线框上来制造半导体装置的方法。该制造方法具备：以使双方的表面对置并使其各端缘在实质平行的状态下相互偏移的方式把上述第1及第2半导体芯片迭合，上述第1及第2半导体芯片的端部的一部分超出另一方半导体芯片的端缘，作为上述第1及第2外部电极分别位于其超出了的区域中的状态、利用凸点连接上述第1内部电极与上述第2内部电极，形成上述半导体安装体的工序；使用具有模片底座部及设置在上述模片底座部附近的引线部的上述引线框，使上述第1半导体芯片与上述模片底座部的表面适当连接，来安装上述半导体安装体进行粘着的工序；用第1及第2金属丝，分别连接上述第1及第2外部电极与上述引线部的工序；以及用密封树脂，密封上述引线框的引线部的一部分、上述半导体安装体、第1金属丝及第2金属丝的工序。
按照该制造方法，可以高效率地用金属丝连接各半导体芯片的外部电极与引线部。
附图说明
图1A为示出构成本发明之一实施形态中的半导体装置的半导体安装体的平面图。
图1B为图1A的A-A1剖面图。
图2为示出使用该半导体安装体而构成了的半导体装置的剖面图。
图3A～D为示出本发明之一实施形态中的半导体装置的制造方法的工序的剖面图。
图4A～C为接着图3D，示出工序的剖面图。
图5A～C为接着图4C，示出工序的剖面图。
图6A～C为示意性地示出构成本发明的实施形态中的半导体装置的芯片的配置例的平面图。
图7A为示出本发明之另一实施形态中的半导体装置的剖面图。
图7B为示意性地示出构成图7A的半导体装置的芯片的配置的平面图。
图8为示出现有例的半导体装置的剖面图。
图9为示意性地示出构成现有例的半导体装置的芯片的配置的平面图。
优选实施例的描述
(实施形态1)
下面，参照附图，说明实施形态1中的半导体装置。
首先，参照图1，说明装入本实施形态的半导体装置中的半导体安装体。图1A为示出本实施形态的半导体安装体的芯片状态的示意性的平面图，图1B为沿着图1A的A-A1线的剖面图。
如图1B所示，本实施形态的半导体安装体具有由第1半导体芯片4、及以表面一侧相对置的方式与第1半导体芯片4的表面接合起来的第2半导体芯片8构成的COC型的结构。第1半导体芯片4具有：在表面上形成的第1内部电极1；在该第1内部电极1上形成的第1凸点2；以及在周边部上形成、与第1内部电极1连接起来的第1外部电极3。第2半导体芯片8具有：在表面上形成的第2内部电极6；在第2内部电极6上形成的第2凸点5；以及在周边部上形成、与第2内部电极6连接起来的第2外部电极7。通过第1凸点2与第2凸点5的接合，把第1半导体芯片4的第1内部电极1与第2半导体芯片8的第2内部电极6导电性地连接起来。在第1半导体芯片4与第2半导体芯片8的间隙中，作为底层填料填充了绝缘性树脂9。
如图1A所示，在使第2半导体芯片8的长边对第1半导体芯片4的长边正交的状态下，形成了该半导体安装体的COC结构。因而，第1半导体芯片4的长方向上的两个端部超出了第2半导体芯片8的侧缘，第2半导体芯片8的长方向上的两个端部超出了第1半导体芯片4的侧缘。由此，第1半导体芯片4的第1外部电极3及第2半导体芯片8的第2外部电极7分别露出。因而，成为在把半导体安装体安装到引线框上时，可用金属丝无障碍地连接第1外部电极3及第2外部电极7与引线部的状态。
使各半导体芯片4、8的端部超出的长度，如图1B所示，必须考虑到在两个芯片间填充的树脂9从端部溢出所形成的凸起。即，必须设定芯片4的端部超出长度，以使第1外部电极3位于凸起的端部9a的外侧。对于第2外部电极7，也是同样的。
虽然图1B中未图示，但通常已知，凸起的端部9a从半导体芯片8突出的长度以与t相当的长度为上限，t为半导体芯片8的厚度与树脂9的厚度相加后的厚度。因而，当假定从半导体芯片8的端缘到第1外部电极3的内侧端源的距离为L时，如果满足t＜L的条件，就能够使第1外部电极3可靠地位于凸起的端部9a的外侧。
具体地说，为了得到在实用上能够满意的效果，假定从另一方半导体芯片的缘突出的长度为0.3mm以上～2.0mm以下是较为理想的。即，如果是0.3mm以上，就可以使外部电极的连接端在超出了的部分中露出。此外，如果超过2.0mm，则把半导体芯片收存到半导体装置内的效率变低，是不实用的。
第2半导体芯片8的第2外部电极7，作为用再布线从第2内部电极6引伸到芯片周边部的外部输入输出用的电极，可在扩散工序级中形成，或者也可在安装工序级中布线形成。具体地说，例如，在聚酰亚胺等绝缘树脂膜上用铜形成布线，用镍(Ni)及金(Au)形成电极部。
此外，作为一例可以假定第1半导体芯片4为逻辑芯片，第2半导体芯片8为其外形面积经第1半导体芯片4大的存储器芯片。作为第1半导体芯片4，除了逻辑电路之外，也可以形成了模拟电路或小容量的存储器。
再有，图1B示出把第2凸点5形成得比第1凸点2大，把第1凸点2的硬度作得比第2凸点5高，且第1凸点2陷入第2凸点5中而连接的状态。作为第2凸点5可使用利用锡(Sn)和银(Ag)的二元系的焊锡凸点。作为详细的例子，作成锡(Sn)96.5％、银(Ag)3.5％的Sn-3.5Ag的焊锡凸点。此外，作为第1凸点2，例如可使用镍(Ni)凸点。在表面上形成了薄的金(Au)层的镍凸点是较为理想的。作为第1凸点2的镍凸点的陷入作为第2凸点5的焊锡凸点而接合，在该接合的界面上形成了镍和锡的合金层。
第1凸点2也可以是与第2凸点5相同、利用锡(Sn)和银(Ag)的二元系的焊锡凸点。
其次，说明把上述半导体安装体安装到引线框上而构成半导体装置的形态。图2为示出本实施形态的半导体装置的主要剖面图。
使第1半导体芯片4与引线框的模片底座10的表面适当连接，来安装上述半导体安装体。利用第1金属丝12把引线框的引线部11的表面与第1半导体芯片4的第1外部电极3连接起来，利用第2金属丝13把引线部11的背面与第2半导体芯片8的第2外部电极7连接起来。如上所述，由于第1外部电极3、第2外部电极7在各半导体芯片4、8上的超出了的前端部中露出，故可使用第1金属丝12、第2金属丝13进行连接。利用密封树脂14密封了引线部11、第1半导体芯片4、第2半导体芯片8、第1金属丝12及第2金属丝13。
如上所述，本实施形态的半导体装置作为高效率地内装了2个功能芯片的小型封装而形成。此外，由于第2半导体芯片8的第2外部电极7是在安装工序中用再布线引伸并配置到芯片周缘部上的、高效率形成的外部电极，故即使在作为下侧的第1半导体芯片4使用了逻辑芯片、作为上侧的第2半导体芯片8使用了其外形面积比下侧的芯片大的存储器芯片的情况下，在COC结构中也可以进行有效的导电性的连接。此外，密封在封装内部的半导体安装体中，芯片间的连接是牢固的，可确保在高温下接合的稳定性，可靠性高。作为一例，在150℃保持中，没有时效变化所引起的接合恶化，确认了芯片间连接的稳定性。
再有，在本实施形态中，示出了构成了QFP(四边形扁平封装)结构的半导体装置之例，但有关所采用的半导体封装可根据希望而自由设定。
其次，说明上述半导体装置的制造方法。图3A～D、图4A～C及图5A～C为示出本实施形态的半导体装置的制造方法的各主要工序的剖面图。图3A～D、图4A～C示出半导体安装体的制造工序，图5A～C示出使用半导体安装体来形成树脂密封型的半导体装置的制造工序。
首先，参照图3A～D、图4A～C，说明半导体安装体的制造工序。图3A～D只示出半导体芯片的一部分，但实际上，在形成了多个芯片的半导体晶片状态下，准备了第1半导体芯片4及第2半导体芯片8。
如图3A所示，准备了在一主面上的大致中央部区域中具有第1内部电极1、在周边区域中具有第1外部电极3的第1半导体芯片4。
其次，如图3B所示，以与第1内部电极1连接的方式形成第1凸点2。利用无电解电镀形成第1凸点2，作成其硬度比后述的半导体芯片8的第2凸点5高，其直径比凸点5小。在此，作为一例，形成在表面上形成了薄的金(Au)层的镍(Ni)凸点。此外，在晶片状态下，对背面进行背面研磨，形成规定的厚度。进而，利用划片把在其面内形成了多个第1半导体芯片4的半导体晶片切断，得到第1半导体芯片4的各个片。
作为第1凸点2也可以通过电解电镀来形成钛(Ti)、铜(Cu)、镍(Ni)的阻挡层、层利用锡(Sn)和银(Ag)的2元系的焊锡凸点。
此外，如图3C所示，准备了在一主面上的大致中央部区域中具有第2内部电极6、在周边区域中具有利用再布线与第2内部电极6连接起来的第2外部电极7的第2半导体芯片8。虽然未图示，但在第2半导体芯片的安装工序中，把布线从第2内部电极6引伸到芯片的周边部，形成第2外部电极7。即，在安装工序级中，利用再布线技术进行引伸来形成外部电极，由此能够对应于COC连接的第1半导体芯片4来形成与要求一致的外部电极。因而，在扩散工艺级中，可实现第2半导体芯片的芯片共用化。
其次，如图3D所示，在芯片状态的第2半导体芯片8上的第2内部电极6上，形成第2凸点5。作为第2凸点5通过电解电镀来形成钛(Ti)、铜(Cu)、镍(Ni)的阻挡层、及利用锡(Sn)和银(Ag)的2元系的焊锡凸点。作为更具体的例子，形成锡(Su)96.5％、银(Ag)3.5％的Sn-3.5Ag的焊锡凸点。而且，在晶片状态下，对背面进行背面研磨，形成规定的厚度。进而，利用划片把形成了多个第2半导体芯片8的半导体晶片切断，得到第2半导体芯片8的各个片。
其次，如图4A所示，使用倒装芯片接合器(未图示)使形成了第1凸点2的第1半导体芯片4的表面与形成了第2凸点5的第2半导体芯片8的主面相互间互相对置，对各凸点2、5相互间进行位置重合。重合的位置关系如图1A所示，成为第2半导体芯片8的长边与第1半导体芯片4的长边正交的状态。由此，第2半导体芯片8的两个端部超出第1半导体芯片4的侧缘，第1半导体芯片的两个端部超出第2半导体芯片8的侧缘的状态。
其次，如图4B所示，使第1半导体芯片4及第2半导体芯片8互相加压，使用工具进行加热，由此，使第1半导体芯片4的第1凸点2陷入第2半导体芯片8的第2凸点5中，使两个凸点接合。
其次，如图4C所示，作为底层填料使绝缘性树脂以不覆盖第1外部电极3、第2外部电极7的方式流入第1半导体芯片4与第2半导体芯片8的间隙中并使之热硬化，把间隙密封。由此，形成第1半导体芯片4的两个端部与第2半导体芯片8的两个端部超出了双方的侧缘的半导体安装体15。
其次，参照图5A～C，说明使用上述那样形成的半导体安装体来制造半导体装置的工序。
首先，如图5A所示，准备至少具有支持半导体芯片的模片底座部10及以前端部对置的方式配置在模片底座部10上的引线部11的引线框。以及第1半导体芯片4的底面与模片底座部10的表面适当连接的方式把半导体安装体15安装到该引线框上，使用粘接剂将其固定。
其次，如图5B所示，利用第1金属丝12导电性地连接第1半导体芯片4的第1外部电极3与引线部11的表面，与此同时利用第2金属丝13导电性地连接第2半导体芯片8的第2外部电极7与引线部11的背面。
其次，如图5C所示，用密封树脂14密封引线部11的一部分即除了外侧部分、模片底座部10、半导体安装体15、各金属丝12和13的周围。
最后，切断引线11从密封树脂14伸出的部分并进行成形，由此完成QFP型的COC型半导体装置。
再有，本实施形态的半导体装置的制造方法在作为第1半导体芯片使用逻辑芯片，作为第2半导体芯片使用其外形面积比第1半导体芯片大的存储器芯片的情况下，特别有效。
其次，参照图6A～C，说明应用了本实施形态的半导体装置及其制造方法的结构的情况的、构成半导体安装体的各半导体芯片的大小关系及芯片的迭合关系之典型例。在每一种结构中，都互相实质平行地配置第1半导体芯片4的边与第2半导体导体芯片8的边。
首先，图6A所示的结构与图1A所示的结构相同。该结构是应用于一方半导体芯片的长边方向的尺寸具有比另一方半导体芯片的短边方向的尺寸大的关系的情况之例。按照该结构，可以简便地层叠大多为长方形芯片的存储器元件与系统LSI等。再有，由于存储器元件大多具有把电极连接端集中于2个边上的结构，故可容易地使用现有的存储器元件。
图6B所示的结构是应用于第2半导体芯片8的外形尺寸在整体上比第1半导体芯片4大的情况之例。以使其超出第2半导体芯片8的缘端的方式偏移了第1半导体芯片4的一个端部。就第2半导体芯片8而言，3个端部超出了对方的缘端。按照该结构，为了把第2半导体芯片8与第1半导体芯片4的电路径作成最短，可以部分地通过凸点进行导电性的连接。
图6C所示的结构是即使在2个半导体芯片的尺寸类似的情况下也可以应用之例。把第1半导体芯片4与第2半导体芯片8在对角线方向上偏移后配置起来。由此，形成了第1半导体芯片4的相邻的2个端部及第2半导体芯片8的另一相邻的2个端部互相超出的结构。按照该结构，可以简便地层叠大多为正方形芯片的、利用不同工艺的元件(GaAs、SiGeC、CMOS)。此外，该结构还具有下述优点，能够把2个半导体芯片的4个边的电极连接端2等分，分成凸点接合用的电极连接端及焊丝接合用的电极连接端而分别使用。由此，例如，如果是具有同一的电极连接端的半导体芯片，就可以在全周方向上进行均匀的焊丝接合，能够避免进行过多的布线。
除了上面所示的例子，还可以对照各芯片上的内部电极的配置及外部电极的配置而采用其它各种芯片的层叠形态。但是，互相实质平行地配置第1半导体芯片4的边与第2半导体芯片8的边的情况是用于产生本发明效果的必要条件。根据该条件，可以充分地确保用于配置外部电极的露出面积。
(实施形态2)
下面，参照图7A、图7B，说明实施形态2中的半导体装置。图7A为示出本实施形态的半导体装置的剖面图，图7B为示出各芯片的外形尺寸关系与层叠状态的示意性的平面图。
本实施形态的半导体装置具有与图2示出的半导体装置基本上相同的结构。但构成安装体的2个半导体芯片4、8的外形尺寸的相互关系不同。
在本实施形态中，如图7B所示，第2半导体芯片21的尺寸在整体上比第1半导体芯片20大，其4个端部全都超出了第1半导体芯片20。因而，如图7A所示，在第1半导体芯片20上未设置外部电极。在第2半导体芯片21上，在周边部上形成并露出了与第2内部电极6连接起来的外部电极22。
使第1半导体芯片20与引线框的模片底座10的表面适当连接，来安装由第1半导体芯片20及第2半导体芯片21构成的半导体安装体。利用金属丝23把引线框的引线部11的背面与第2半导体芯片21的外部电极22连接起来。
在本实施形态中，也可以假定第1半导体芯片20为逻辑芯片，第2半导体芯片21为存储器芯片。此外，可以把第2半导体芯片21的外部电极22作为用再布线从第2内部电极6引伸到芯片周边部的外部输入输出用的电极。由此，即使第2半导体芯片使用其外形面积比下侧的芯片大的存储器芯片，也可以有效地实现COC结构。

Claims (10)

1.一种半导体装置，其特征在于，
具备：引线框，具有模片底座部及设置在上述模片底座部附近的引线部；
第1半导体芯片，在表面上具有第1内部电极及第1外部电极，将其安装在上述模片底座部上；
第2半导体芯片，在表面上具有第2内部电极及第2外部电极，以使表面对置的方式将其接合到上述第1半导体芯片上，利用凸点把上述第2内部电极与上述第1内部电极连接起来；
第1及第2金属丝，分别把上述引线部与上述第1及上述第2外部电极连接起来；以及
密封树脂，把上述引线部、上述第1及第2半导体芯片以及上述第1及第2金属丝密封起来，
以使其各端缘在实质平行的状态下相互偏移的方式把上述第1及第2半导体芯片迭合，上述第1及第2半导体芯片的端部的一部分超出另一方半导体芯片的端缘，在其超出了的区域中分别配置了上述第1及第2外部电极。
2.根据权利要求1中所述的半导体装置，其特征在于，上述第1半导体芯片的相对置的一对端部超出上述第2半导体芯片的端缘，上述第2半导体芯片的相对置的一对端部超出上述第1半导体芯片的端缘。
3.根据权利要求1中所述的半导体装置，其特征在于，上述第1半导体芯片的一个端部超出上述第2半导体芯片的端缘，上述第2半导体芯片的3个端部超出上述第1半导体芯片的端缘。
4.根据权利要求1中所述的半导体装置，其特征在于，把上述第1半导体芯片与上述第2半导体芯片在大致对角线方向上偏移后配置，上述第1半导体芯片的相邻的2个端部及上述第2半导体芯片的相邻的2个端部超出。
5.根据权利要求1中所述的半导体装置，其特征在于，在上述第1半导体芯片与上述第2半导体芯片的间隙中填充绝缘性树脂，上述绝缘性树脂的端部从上述第1半导体芯片或上述第2半导体芯片的端部突出而形成凸起，上述第1及第2外部电极位于上述凸起端部的外侧。
6.根据权利要求5中所述的半导体装置，其特征在于，当假定在上述第1半导体芯片/上述第2半导体芯片超出了的部分中的、上述第1半导体芯片/上述第2半导体芯片的厚度与上述绝缘性树脂的厚度相加后的厚度为t，从上述第2半导体芯片/上述第1半导体芯片的端缘到上述第1外部电极/第2外部的电极的内侧端缘的距离为L时，满足t＜L的条件。
7.根据权利要求5中所述的半导体装置，其特征在于，上述第2半导体芯片/上述第1半导体芯片的端部超出了上述第1半导体芯片/上述第2半导体芯片的端缘的长度为0.3mm以上到2.0mm以下。
8.根据权利要求1中所述的半导体装置，其特征在于，上述第1半导体芯片是逻辑芯片或模拟芯片，上述第2半导体芯片是其外形面积比上述第1半导体芯片大的存储器芯片。
9.根据权利要求8中所述的半导体装置，其特征在于，上述第2半导体芯片的至少1个边比上述第1半导体芯片的边更长。
10.一种半导体装置的制造方法，在该方法中，以使双方的表面对置的方式把在表面上具有第1内部电极及第1外部电极的第1半导体芯片、与在表面上具有第2内部电极及第2外部电极的第2半导体芯片迭合而接合起来，作成半导体安装体，把上述半导体安装体安装到引线框上来制造半导体装置，该方法的特征在于，具备：
以使其各端缘在实质平行的状态下相互偏移的方式把上述第1及第2半导体芯片迭合，上述第1及第2半导体芯片的端部的一部分超出另一方半导体芯片的端缘，作为上述第1及第2外部电极分别位于其超出了的区域中的状态、利用凸点连接上述第1内部电极与上述第2内部电极，形成上述半导体安装体的工序；
使用具有模片底座部及设置在上述模片底座附近的引线部的上述引线框，使上述第1半导体芯片与上述模片底座部的表面适当连接，来安装上述半导体安装体进行粘着的工序；
用第1及第2金属丝，分别连接上述第1及第2外部电极与上述引线部的工序；以及
用密封树脂，密封上述引线框的引线部的一部分、上述半导体安装体、第1金属丝及第2金属丝的工序。
CNB021230188A 2001-06-13 2002-06-13 半导体装置及其制造方法 Expired - Fee Related CN1267993C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP178104/2001 2001-06-13
JP178104/01 2001-06-13
JP2001178104 2001-06-13

Publications (2)

Publication Number Publication Date
CN1391278A true CN1391278A (zh) 2003-01-15
CN1267993C CN1267993C (zh) 2006-08-02

Family

ID=19018853

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB021230188A Expired - Fee Related CN1267993C (zh) 2001-06-13 2002-06-13 半导体装置及其制造方法

Country Status (4)

Country Link
US (1) US6677674B2 (zh)
KR (1) KR100497974B1 (zh)
CN (1) CN1267993C (zh)
TW (1) TW544901B (zh)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1622326B (zh) * 2003-11-28 2010-07-07 恩益禧电子股份有限公司 偏移结合的多芯片半导体器件
CN102064135A (zh) * 2010-10-21 2011-05-18 日月光半导体制造股份有限公司 具有金属柱的芯片及具有金属柱的芯片的封装结构
US8552553B2 (en) 2009-10-14 2013-10-08 Advanced Semiconductor Engineering, Inc. Semiconductor device
US8569885B2 (en) 2010-10-29 2013-10-29 Advanced Semiconductor Engineering, Inc. Stacked semiconductor packages and related methods
US8686568B2 (en) 2012-09-27 2014-04-01 Advanced Semiconductor Engineering, Inc. Semiconductor package substrates having layered circuit segments, and related methods
US8698307B2 (en) 2010-09-27 2014-04-15 Advanced Semiconductor Engineering, Inc. Semiconductor package with integrated metal pillars and manufacturing methods thereof
CN104011851A (zh) * 2011-12-22 2014-08-27 英特尔公司 具有窗口插入器的3d集成电路封装
US8884443B2 (en) 2012-07-05 2014-11-11 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing
CN104517936A (zh) * 2013-09-30 2015-04-15 联发科技股份有限公司 封装结构
CN104916552A (zh) * 2014-03-14 2015-09-16 株式会社东芝 半导体装置的制造方法及半导体装置
CN108183098A (zh) * 2017-12-22 2018-06-19 中国电子科技集团公司第四十七研究所 大容量存储器电路的3d错层堆叠封装结构

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003023138A (ja) * 2001-07-10 2003-01-24 Toshiba Corp メモリチップ及びこれを用いたｃｏｃデバイス、並びに、これらの製造方法
JP3787295B2 (ja) * 2001-10-23 2006-06-21 ローム株式会社 半導体装置
JP3851845B2 (ja) * 2002-06-06 2006-11-29 株式会社ルネサステクノロジ 半導体装置
US6815254B2 (en) * 2003-03-10 2004-11-09 Freescale Semiconductor, Inc. Semiconductor package with multiple sides having package contacts
JP2004288815A (ja) * 2003-03-20 2004-10-14 Seiko Epson Corp 半導体装置及びその製造方法
TW591780B (en) * 2003-03-21 2004-06-11 Univ Nat Central Flip chip Au bump structure and method of manufacturing the same
DE10319900A1 (de) * 2003-04-29 2004-11-25 Infineon Technologies Ag Optoelektronische Sende- und/oder Empfangsanordnung
US20040232560A1 (en) * 2003-05-22 2004-11-25 Chao-Yuan Su Flip chip assembly process and substrate used therewith
JP2005243132A (ja) * 2004-02-26 2005-09-08 Renesas Technology Corp 半導体装置
JP4353845B2 (ja) * 2004-03-31 2009-10-28 富士通株式会社 半導体装置の製造方法
US7015587B1 (en) * 2004-09-07 2006-03-21 National Semiconductor Corporation Stacked die package for semiconductor devices
JP4602223B2 (ja) * 2005-10-24 2010-12-22 株式会社東芝 半導体装置とそれを用いた半導体パッケージ
FI119728B (fi) * 2005-11-23 2009-02-27 Vti Technologies Oy Menetelmä mikroelektromekaanisen komponentin valmistamiseksi ja mikroelektromekaaninen komponentti
KR100681263B1 (ko) * 2006-01-17 2007-02-09 삼성전자주식회사 반도체 패키지
JP2007288003A (ja) * 2006-04-18 2007-11-01 Sharp Corp 半導体装置
US8022554B2 (en) 2006-06-15 2011-09-20 Sitime Corporation Stacked die package for MEMS resonator system
JP4910512B2 (ja) * 2006-06-30 2012-04-04 富士通セミコンダクター株式会社 半導体装置および半導体装置の製造方法
US7645638B2 (en) * 2006-08-04 2010-01-12 Stats Chippac Ltd. Stackable multi-chip package system with support structure
US7622333B2 (en) * 2006-08-04 2009-11-24 Stats Chippac Ltd. Integrated circuit package system for package stacking and manufacturing method thereof
US8642383B2 (en) 2006-09-28 2014-02-04 Stats Chippac Ltd. Dual-die package structure having dies externally and simultaneously connected via bump electrodes and bond wires
US7759783B2 (en) * 2006-12-07 2010-07-20 Stats Chippac Ltd. Integrated circuit package system employing thin profile techniques
US7683467B2 (en) * 2006-12-07 2010-03-23 Stats Chippac Ltd. Integrated circuit package system employing structural support
TWI335055B (en) * 2007-06-29 2010-12-21 Chipmos Technologies Inc Chip-stacked package structure
EP2011762B1 (en) * 2007-07-02 2015-09-30 Denso Corporation Semiconductor device with a sensor connected to an external element
US20090152740A1 (en) * 2007-12-17 2009-06-18 Soo-San Park Integrated circuit package system with flip chip
TW201133745A (en) * 2009-08-27 2011-10-01 Advanpack Solutions Private Ltd Stacked bump interconnection structure and semiconductor package formed using the same
US8212342B2 (en) 2009-12-10 2012-07-03 Stats Chippac Ltd. Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof
WO2013153742A1 (ja) 2012-04-11 2013-10-17 パナソニック株式会社 半導体装置
JP5954075B2 (ja) * 2012-09-21 2016-07-20 ソニー株式会社 半導体装置及び半導体装置の製造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0521703A (ja) * 1991-07-11 1993-01-29 Mitsubishi Electric Corp 半導体装置
JP3007023B2 (ja) * 1995-05-30 2000-02-07 シャープ株式会社 半導体集積回路およびその製造方法
US5874781A (en) * 1995-08-16 1999-02-23 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
JP3316409B2 (ja) * 1997-03-13 2002-08-19 ローム株式会社 複数のｉｃチップを備えた半導体装置の構造
EP0890989A4 (en) 1997-01-24 2006-11-02 Rohm Co Ltd SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE DEVICE
US6057598A (en) * 1997-01-31 2000-05-02 Vlsi Technology, Inc. Face on face flip chip integration
KR19990069438A (ko) * 1998-02-09 1999-09-06 김영환 칩 스택 패키지
US6376914B2 (en) * 1999-12-09 2002-04-23 Atmel Corporation Dual-die integrated circuit package
KR20010061886A (ko) * 1999-12-29 2001-07-07 윤종용 적층 칩 패키지
US6252305B1 (en) * 2000-02-29 2001-06-26 Advanced Semiconductor Engineering, Inc. Multichip module having a stacked chip arrangement
JP2001274316A (ja) * 2000-03-23 2001-10-05 Hitachi Ltd 半導体装置及びその製造方法
JP3813788B2 (ja) * 2000-04-14 2006-08-23 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US6448659B1 (en) * 2000-04-26 2002-09-10 Advanced Micro Devices, Inc. Stacked die design with supporting O-ring
US6391682B1 (en) * 2000-06-21 2002-05-21 Siliconware Precision Industries Co., Ltd. Method of performing flip-chip underfill in a wire-bonded chip-on-chip ball-grid array integrated circuit package module
US6900528B2 (en) * 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1622326B (zh) * 2003-11-28 2010-07-07 恩益禧电子股份有限公司 偏移结合的多芯片半导体器件
US8552553B2 (en) 2009-10-14 2013-10-08 Advanced Semiconductor Engineering, Inc. Semiconductor device
US8698307B2 (en) 2010-09-27 2014-04-15 Advanced Semiconductor Engineering, Inc. Semiconductor package with integrated metal pillars and manufacturing methods thereof
CN102064135A (zh) * 2010-10-21 2011-05-18 日月光半导体制造股份有限公司 具有金属柱的芯片及具有金属柱的芯片的封装结构
CN102064135B (zh) * 2010-10-21 2015-07-22 日月光半导体制造股份有限公司 具有金属柱的芯片及具有金属柱的芯片的封装结构
US8569885B2 (en) 2010-10-29 2013-10-29 Advanced Semiconductor Engineering, Inc. Stacked semiconductor packages and related methods
CN104011851A (zh) * 2011-12-22 2014-08-27 英特尔公司 具有窗口插入器的3d集成电路封装
US9224707B2 (en) 2012-07-05 2015-12-29 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing
US8884443B2 (en) 2012-07-05 2014-11-11 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing
US9437532B2 (en) 2012-07-05 2016-09-06 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing
US8686568B2 (en) 2012-09-27 2014-04-01 Advanced Semiconductor Engineering, Inc. Semiconductor package substrates having layered circuit segments, and related methods
CN104517936A (zh) * 2013-09-30 2015-04-15 联发科技股份有限公司 封装结构
US10727202B2 (en) 2013-09-30 2020-07-28 Mediatek Inc. Package structure
US11348900B2 (en) 2013-09-30 2022-05-31 Mediatek Inc. Package structure
CN104916552A (zh) * 2014-03-14 2015-09-16 株式会社东芝 半导体装置的制造方法及半导体装置
CN108183098A (zh) * 2017-12-22 2018-06-19 中国电子科技集团公司第四十七研究所 大容量存储器电路的3d错层堆叠封装结构

Also Published As

Publication number Publication date
CN1267993C (zh) 2006-08-02
KR20020095123A (ko) 2002-12-20
US6677674B2 (en) 2004-01-13
KR100497974B1 (ko) 2005-07-01
TW544901B (en) 2003-08-01
US20020192855A1 (en) 2002-12-19

Similar Documents

Publication Publication Date Title
CN1267993C (zh) 半导体装置及其制造方法
US9589868B2 (en) Packaging solutions for devices and systems comprising lateral GaN power transistors
CN1041254C (zh) 三维结构的半导体器件
KR100470897B1 (ko) 듀얼 다이 패키지 제조 방법
CN1426104A (zh) 半导体器件及其制造方法
CN1836319A (zh) 半导体封装中芯片衬垫布线的引线框
JPH06244231A (ja) 気密半導体デバイスおよびその製造方法
WO2013097581A1 (zh) 一种半导体封装中封装系统结构及制造方法
CN1512580A (zh) 半导体装置及其制造方法
CN1260591A (zh) 半导体封装及其制造方法
CN1319890A (zh) 半导体器件和使用该半导体器件的半导体组件
CN1221027C (zh) 具有散热结构的半导体封装件
KR102633142B1 (ko) 반도체 패키지
CN101060090A (zh) 半导体装置的制造方法
CN1224097C (zh) 半导体装置及其制造方法、电路板和电子仪器
CN1767178A (zh) 半导体载板及其制造方法与半导体封装组件
US12087734B2 (en) Method for forming chip packages and a chip package having a chipset comprising a first chip and a second chip
CN100336217C (zh) 树脂密封型半导体器件及其制造方法
TW200423342A (en) Chip package structure and process for fabricating the same
CN100350581C (zh) 整合打线及倒装封装的芯片结构及工艺
CN1172369C (zh) 具散热片的半导体封装件
CN115966564A (zh) 一种改善散热的芯片封装结构及其制备方法
JP2003068975A (ja) 半導体装置およびその製造方法
CN112599427B (zh) 一种形成封装件的方法及封装件
CN1851912A (zh) 芯片封装体

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20170802

Address after: California, USA

Patentee after: Sony Corp.

Address before: California, USA

Patentee before: Nova Semiconductor Ltd.

Effective date of registration: 20170802

Address after: California, USA

Patentee after: Nova Semiconductor Ltd.

Address before: Osaka Japan

Patentee before: Matsushita Electric Industrial Co.,Ltd.

TR01 Transfer of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20060802

Termination date: 20200613

CF01 Termination of patent right due to non-payment of annual fee