CN1426104A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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Abstract
公开了一种半导体器件,包含:在主面上设置了引线的芯片搭载构件,在所述引线上设置有覆盖预定位置表面的薄膜形状的电镀部;在主面上设置了突点,并且该突点通过所述电镀部电连接所述引线,搭载在所述芯片搭载构件上的半导体芯片;设置在所述半导体芯片和所述芯片搭载构件之间的密封构件。
Description
技术领域
本发明涉及通过倒装法把半导体芯片一次连接密封到安装构件上的技术,特别是涉及对半导体芯片以及安装构件附近的构造和连接状态加以改良的半导体器件及其制造方法。
背景技术
下面,简洁地说明通过一般倒装方式的无引线接合法把半导体芯片连接到封装等安装构件上,并且接合、密封半导体芯片和安装构件的步骤。
例如如图7所示,半导体芯片101和成为安装构件的玻璃环氧衬底103相对配置。这时,使形成在芯片101上的金(Au)柱状突点102和布线在衬底103上的铜(Cu)引线104对位。在引线104上通过电解电镀法预先层叠形成了与它的宽度大致相同程度大小的厚壁形状的突起物(突点设置物)即Sn-Ag电镀突点105。也可以使用Sn形成电镀突点105。另外,电镀突点105的宽度大约为50μm。
然后,在芯片101和衬底103之间填充热硬化性绝缘薄膜等的密封树脂106。在该状态下把芯片101向衬底103一侧热压接。据此,如图8所示,通过电镀突点105连接柱状突点102和引线104。即一次进行了柱状突点102和引线104的电连接以及通过密封树脂106对半导体芯片101和玻璃环氧衬底103的密封。
近年,在半导体器件的制造技术领域中,伴随着器件的微细化和高密度化等,对于窄引线间隔化的要求不断高涨。即对于引线间隔的窄间隔化的要求不断高涨。可是,通常的电镀突点105的宽度约50m,这成为窄间隔化的最大阻碍。但是,如果单纯使引线104的宽度变窄,则当在引线104上形成电镀突点105时,电镀突点105的层叠位置容易偏移,或电镀突点105容易从引线104落下。结果,有可能产生柱状突点102、引线104以及电镀突点105电连接的不良。因此,有可能给半导体器件的电性能和可靠性等半导体器件的质量造成障碍。由于电镀突点105的位置偏移,有可能导致半导体器件的制造成品率下降,半导体器件的生产效率下降。
发明内容
根据本发明的一个方面,提供了一种半导体器件,包含:在主面上设置了引线的芯片搭载构件,在所述引线上设置有覆盖预定位置表面的薄膜形状的电镀部;在主面上设置有突点,并且该突点通过所述电镀部电连接所述引线,搭载在所述芯片搭载构件上的半导体芯片;设置在所述半导体芯片和所述芯片搭载构件之间的密封构件。
根据本发明的另一个方面,提供了一种半导体器件的制造方法,包含:把在主面上设置了突点的半导体芯片和在主面上设置了引线的芯片搭载构件相对配置,在所述引线上设置有覆盖预定位置表面的薄膜形状的电镀部;在所述半导体芯片和所述芯片搭载构件之间设置密封构件;以及通过由所述电镀部电连接所述突点和所述引线,并且使用所述密封构件密封接合所述半导体芯片和所述芯片搭载构件之间,连接密封所述半导体芯片和所述芯片搭载构件。
根据本发明的另一个方面,提供了一种半导体器件的制造方法,包含:把在主面上设置了突点的半导体芯片和在主面上设置了引线并且在所述主面上设置了密封构件的芯片搭载构件相对配置,在所述引线上设置有覆盖预定位置表面的薄膜形状的电镀部;通过由所述电镀部电连接所述突点和所述引线,并且使用所述密封构件密封接合所述半导体芯片和所述芯片搭载构件之间,连接密封所述半导体芯片和所述芯片搭载构件。
附图说明
下面简要说明附图。
图1是表示实施例1的半导体器件的制造方法的步骤剖视图。
图2是表示实施例1的半导体器件的制造方法的步骤剖视图。
图3是表示实施例1的半导体器件的一部分的剖视图。
图4是表示实施例2的半导体器件的制造方法的步骤剖视图。
图5是表示实施例2的半导体器件的制造方法的步骤剖视图。
图6是表示实施例3的半导体器件的一部分的剖视图。
图7是表示以往技术中半导体器件制造方法的步骤剖视图。
图8是表示以往技术中半导体器件制造方法的步骤剖视图。
具体实施方式
下面,根据图示的实施例具体说明本发明。
(实施例1)
图1和图2是表示实施例1的半导体器件的结构和制造步骤的剖视图。本实施例在所谓的倒装方式的无引线接合法中具有特征。
首先,就本实施例的半导体器件的结构加以说明。
如图1所示,在半导体芯片1的一个主面上设置了与图中未显示的电极电连接的突点(柱状突点)2。实际上对于一个半导体芯片1设置了多个该柱状突点2,但是在图中只表示了一个,省略了其他的图示。
在本实施例中,使用难以劣化的材料形成柱状突点2。具体而言,使用难以氧化的金(Au)形成柱状突点2。该Au柱状突点2中,其顶端部2a形成了突出的形状。使用图中未显示的焊头,使预定量的金附着在半导体芯片1的电极上后,在停止供给金的状态下,通过使焊头远离半导体芯片1,就能容易地形成这样的形状。通过这样的形成方法,柱状突点2的顶端部2a变为极力拉伸了用金形成的金属线的状态。
而作为搭载了半导体芯片1的芯片搭载构件(安装衬底)的芯片搭载衬底3例如由玻璃环氧树脂等形成。在该芯片搭载衬底3的内部或表面上设置了图中未显示的各种布线。本实施例的芯片搭载衬底3使用形成了象纸一样薄的薄壁形状的衬底。即芯片搭载衬底3使用所谓的被称作PTP(纸薄封装)衬底的衬底。在该芯片搭载衬底3的一个主面上,设置了与各种布线电连接的铜(Cu)制的引线(内部引线)4。
该铜内部引线4不用象上述以往技术那样,在引线上支撑在宽度方向上充分延伸的厚壁形状的突起物(突点设置物)即Sn-Ag电镀突点105。因此,内部引线4中,它的剖视图形成了随着远离芯片搭载衬底3而变窄的近梯形。另外,内部引线4的衬底一侧端部的宽度形成了与柱状突点2的最大宽度大致相同或比它小的尺寸。即与在以往的技术中说明的Cu引线104的宽度相比,紧凑地形成了内部引线4的衬底一侧,其端部的宽度相当窄。具体而言,内部引线4中,其衬底一侧端部的宽度约为40μm,另外顶端一侧端部的宽度约为20~30μm。内部引线4的顶端一侧端部的宽度尺寸为与柱状突点2的顶端部2a的最大宽度大致同程度的大小。通过把内部引线4形成所述的大小和形状,能实现窄引线间隔化(窄间距化)。本发明者们根据进行的实验可知:以往约为84μm的引线间隔(间距)至少能变窄到它的约70%多的大小,即约60μm。
在内部引线4的表面上进行了电镀。具体而言,在内部引线4上,形成了厚度约0.6μm的薄膜形状的电镀部(电镀薄膜、电镀层)5,使其大致全面覆盖与该柱状突点2连接的部分及其周围的表面。据此,不使用在以往技术中说明的Sn-Ag电镀突点105,就能使柱状突点2和内部引线4的连接部分及其周围的材料难以氧化和老化。另外,也不用再担心象以往技术那样,Sn-Ag电镀突点105从内部引线4的上面偏离,接触相邻的引线104的侧面,引起短路等电连接的不良。当然没必要考虑Sn-Ag电镀突点105的位置偏移等。因此,能简单并且迅速地进行后述的柱状突点和内部引线4的连接作业。
另外,在所谓的通常的TAB(载带自动键合)方式中,设置在内部引线表面上的电镀膜的膜厚通常就是厚也约为0.2μm。而设置在本实施例的内部引线4的表面上的电镀薄膜5的膜厚形成的比较厚,约0.6μm。因此,本实施例的内部引线4对于热和水分的耐久性比较高。即电镀薄膜5内侧的内部引线4难以老化。
在本实施例中,以锡(Sn)为原料,通过无电解电镀法形成电镀薄膜5。该无电解电镀法与电解电镀法相比,不但能缩短工艺所需的时间,而且不需要掩模和电极等特别的构件以及装置。因此,不但能实现省作业化和生产效率的提高,而且能抑制生产成本。
下面,就本实施例的半导体器件的制造方法加以说明。
首先,如图1所示,以柱状突点2与内部引线4相对的姿势,配置半导体芯片1和芯片搭载衬底3。这时,在半导体芯片1和芯片搭载衬底3之间设置(填充)密封了该间隙并且接合半导体芯片1和芯片搭载衬底3的密封树脂6。在不使Sn电镀薄膜5熔化或在连接了柱状突点2和内部引线4时在该连接部分不会发生共晶程度的温度下,通过具有热硬化性和接合性的热硬化性树脂形成了该密封树脂6。具体而言,在约160℃~200℃左右的温度下,通过具有热硬化性和接合性的热硬化性树脂形成了该密封树脂6。须指出的是,在使半导体芯片1与芯片搭载衬底3相对配置之前,可以预先在芯片搭载衬底3上设置密封树脂6。
接着,一边对半导体芯片1、芯片搭载衬底3和密封树脂6加热,一边从它们的厚度方向两侧按压。进行该热压接的温度设定在约160℃~200℃左右的范围内。根据本发明者们进行的实验可知:当在约180℃进行了热压接时,能极迅速地接合以及密封半导体芯片1和芯片搭载衬底3。与此同时,还可知:能使半导体芯片1和芯片搭载衬底3的接合以及密封状态、以及电镀薄膜5的存在状态为极良好的状态。另外,还可知:热压接所需时间极短,能大幅度降低以柱状突点2和内部引线4为主的电气系统的热所导致的负载。
一般在TAB(载带自动键合)法或使突点和引线共晶进行接合的方法中,需要高于200℃的高温。如果在这样的高温下进行热压接,则与本实施例相比,因为对半导体器件的热导致的负载当然变大,所以容易招致半导体器件的质量下降。因此,成为半导体器件的成品率下降,生产效率下降的原因。而本实施例的半导体器件的制造方法中,因为在约180℃的比较低的温度下,能抑制热导致的负载来制造半导体器件,所以能使半导体器件的成品率提高,能提高生产效率。另外,当然由该半导体器件的制造方法制造的半导体器件质量难以下降。
接着,如图2所示,把柱状突点2和内部引线4接触,一边按压一边加热,发生变形直到该顶端部2a的宽度为与内部引线4的顶端一侧端部大致相同程度的宽度。据此,能实现柱状突点2和内部引线4的电镀薄膜5的表面之间的适当的电接合状态。然后,在把按压力保持在一定的大小,使柱状突点2的顶端部2a不过度变形的状态下,继续加热,使密封树脂6凝固。在确认密封树脂6凝固了以后,解除加热和按压,使该热压接步骤结束。据此,通过电镀薄膜5以适当的状态电连接柱状突点2和内部引线4。与此同时,半导体芯片1和芯片搭载衬底3在它们之间通过密封树脂6大致完全密封的状态下,接合(固定)在一起。
这样,根据本实施例的半导体器件的制造方法,能以适当的状态一次进行柱状突点2和内部引线4的连接、半导体芯片1和芯片搭载衬底3的接合以及它们之间间隙的密封。在以下的说明中,把该步骤称作一次连接密封步骤(倒装芯片一次连接密封步骤)。
当通过所述的一次连接密封步骤把半导体芯片1固定搭载在芯片搭载衬底3上后,进入封装步骤。在本实施例中,例如如图3所示,除了密封树脂6,还在半导体芯片1的周围以半导体芯片1为对称中心设置密封树脂7、8。密封树脂7、8由与密封树脂6相同的材料形成。在隔着半导体芯片1与芯片搭载衬底3相反的一侧,设置免于遭受来自外部的冲击和水分等保护半导体芯片1的作为表面衬底的保护衬底9。这时,在保护衬底9和半导体芯片1之间也可以适当设置接合剂(接合树脂)等。
然后与所述的一次连接密封步骤同样,一边对半导体芯片1、芯片搭载衬底3和密封树脂6、7、8、以及保护衬底9加热,一边从它们的厚度方向的两个外侧按压,进行封装。然后通过热压接等安装图中未显示的接地衬底(ground substrate)和球层衬底(ball layersubstrate)等。据此,能制造在一块芯片搭载衬底3上搭载了一块半导体芯片1的半导体器件10。即能制造所谓的单层构造的单片封装的半导体器件10。须指出的是,在半导体器件10中,芯片搭载衬底3也能同时完成所谓封装(封装构件)的功能。
如上所述,根据包含倒装芯片一次连接密封步骤的实施例1的半导体器件的制造方法,能实现引线间隔的窄间距化,能压缩半导体器件。与此同时,能以高效、低成本并且简单地制造很难损害电性能和可靠性,质量优异并且寿命长的半导体器件。另外,因为不使用特殊的装置和设备就能实施实施例1的半导体器件的制造方法,所以极富通用性。因此,几乎不会有半导体器件的制造步骤中的成本的负担。
另外,如图3所示,半导体器件10具有以半导体芯片1为对称中心,在半导体芯片1的周围分别对称配置芯片搭载衬底3、保护衬底9以及由相同的材料构成的密封树脂6、7、8的构造。根据这样的对称构造,在半导体器件10的内部不用设置特别的加强构造和加强零件或使芯片搭载衬底3成形为厚壁,就能良好地抑制芯片搭载衬底3等的翘曲和变形。另外,根据所述的对称构造,即使半导体器件10的内部发生复杂的变形,该变形也是以半导体芯片1为对称中心发生。因此,变形导致的应力向着半导体芯片1的周围大致均匀地分散,很难局部集中在半导体器件10内部的特定位置。特别是变形导致的应力很难局部集中在半导体器件的重要构成要素即半导体芯片1上。这样的能使变形导致的应力分散、缓和的作用和效果在一般对应力脆弱的薄壁并且紧凑的单层构造的单片封装中极有效。即在实施例1的半导体器件10中极有效。
这样,即使半导体器件10是薄壁并且紧凑的,也很难发生变形导致的应力集中的点作为起点,构件彼此剥离,或变形导致的负载集中加到半导体芯片1上。因此,不但半导体器件10质量难以恶化,使用寿命长,而且电性能容易保持稳定的状态,可靠性高。另外,由所述的构造构成的半导体器件10很耐温度和湿度的变化导致的封装全体的翘曲和变形,很难受到其使用环境导致的制约。这样半导体器件10紧凑并且通用性高,所以极富实用性。
(实施例2)
图4和图5是表示实施例2的半导体器件的结构和制造步骤的剖面图。须指出的是,对于与实施例1相同的部分采用了相同的符号,并省略了详细的说明。
本实施例的半导体器件与实施例1的不同点在于:设置在半导体芯片1上的Au柱状突点11的顶端部11a的形状以及柱状突点11与Cu内部引线4的连接状态。
如图4所示,柱状突点11的顶端部11a形成了近平坦的形状。这样的形状能用如下所述的两种方法形成。一种是与实施例1同样使用焊头形成了柱状突点2后,进行按压直到柱状突点2的顶端部2a变为平坦的形状。按压柱状突点2的顶端部2a的步骤例如一般由用于使突点的高度一致的所谓的整平工具进行。另一种是在半导体芯片1的电极上形成了柱状突点的电极一侧端部后,在停止了金的供给的状态下,使焊头在沿着半导体芯片1的主面的方向移动。在该方法中,不象实施例1那样,使焊头向离开半导体芯片1的方向移动。据此,柱状突点11的顶端部11a形成大致平坦的形状。
与实施例1同样,通过一次连接密封步骤,通过电镀薄膜5,把由所述形状构成的柱状突点11和内部引线4电连接。在该实施例2中,如图5所示,把半导体芯片1和芯片搭载衬底3从它们的外侧按压,直到内部引线4的顶端部从该顶端部11a一侧突入(埋没)到柱状突点11的内部预定量的状态。这时柱状突点11和内部引线4的连接部分与实施例1同样,不会发生共晶,通过电镀薄膜5以适当的状态电连接。
在本实施例中,柱状突点11的顶端部11a形成了近平坦的形状,据此,柱状突点11和内部引线4容易以适当的状态电接触。结果,能更简单并且迅速地进行柱状突点11和内部引线4的连接作业。另外,能提高对于进行一次连接密封步骤时的柱状突点11和内部引线4的位置偏移的界限。因此,能提高对于半导体芯片1和芯片搭载衬底3的位置偏移的界限。因此,根据本实施例的半导体器件的制造方法,能以更高效率、低成本并且更简单地制造紧凑的质量优异并且寿命长的半导体器件。
另外,在本实施例中,能容易地把突入柱状突点11内部的内部引线4的突入量(埋没量)调整为适当的量。即与实施例1相比,能容易地调节半导体芯片1和芯片搭载衬底3的间隔,能使半导体器件全体的厚度变薄。在以下的说明中,把半导体芯片1和芯片搭载衬底3的间隔称作芯片连接高度。
如果具体地说明,则以往技术的半导体器件的芯片连接高度和图2中用h1表示的实施例1的半导体器件10的芯片连接高度约为60μm。而根据本发明者们进行的实验可知:图5中用h2表示的实施例2的半导体器件的芯片连接高度约能降低到30μm。在最近的半导体产业界中,芯片连接高度当前的目标值约为40μm。因此,实施例2的半导体器件的芯片连接高度是远远超过该目标值的值。结果,在形成薄壁的半导体封装特别是在封装厚度约0.2mm以下的薄型半导体封装中,是极有效的。
顺便提一下,如果半导体芯片1的厚度约为60μm,芯片搭载衬底3的厚度约50μm,则在以往的技术和实施例1中,从半导体芯片1的外侧到芯片搭载衬底3的外侧的厚度约为170μm。而在能把芯片连接高度h2设定为约30μm的实施例2中,能使从半导体芯片1的外侧到芯片搭载衬底3的外侧的厚度变薄到140μm。
如上所述,根据实施例2的半导体器件和半导体器件的制造方法,能与实施例1同样实现窄间距化。与此同时,能实现半导体器件的薄壁化。因此,能使半导体器件更紧凑。
(实施例3)
图6是表示实施例3的半导体器件的结构的剖视图。须指出的是,对于与实施例1相同的部分采用了相同的符号,省略了它的详细说明。
本实施例的半导体器件21是把通过所述实施例2的半导体器件的制造方法一次连接密封步骤的半导体芯片1和芯片搭载衬底3层叠多层例如4层而成的。即本实施例的半导体器件21的结构为具有多个半导体芯片1的多芯片封装中的所谓层叠型封装。多芯片封装也称作多芯片组件或多块组件。另外,层叠型封装也称作层叠型组件或层叠型器件。
另外,在本实施例的半导体器件21中,例如使用256MB的DRAM作为半导体芯片1。因此,本实施例的半导体器件21的结构为所谓的层叠型DRAM封装21。层叠型DRAM封装21是把存储器芯片层叠为多层的称作层叠型存储器封装或层叠型存储器组件的半导体器件的一种。
下面,说明基于本实施例的半导体器件的制造方法的DRAM封装21的制造步骤。
首先,根据实施例2的半导体器件的制造方法,把半导体芯片1搭载并且一次连接密封在芯片搭载衬底3上。接着,把这一组的半导体芯片1和芯片搭载衬底3层叠四层。这时,对于四层的各芯片搭载衬底3,沿着层叠方向交替配置作为中间基体材料的中间衬底22。接着,使用表面衬底23、电源接地衬底24和球层衬底25,从它们层叠方向的两个外侧夹这些层叠完的各半导体芯片1、芯片搭载衬底3和中间衬底22。这时,在各衬底3、22、23、24、25之间也可以适当设置结合剂。然后,通过沿着它们的层叠方向热压接各衬底3、22、23、24、25,制造图6所示的层叠型DRAM封装21。
在该层叠型DRAM封装21中,表面衬底23兼有作为保护内部的半导体芯片的保护衬底的功能。另外,在四块各中间衬底上,层间连接用布线26和层间连接用端子(层间连接用通路栓塞)27分别形成在预定的位置,并且形成了预定的形状。同样,在电源接地衬底24上,电源接地用布线28和电源接地用端子(电源接地用通路栓塞)29分别形成在预定的位置,并且形成了预定的形状。在球层衬底25上,外部端子连接用布线30和外部端子31分别形成在预定的位置,并且形成了预定的形状。四块各半导体芯片1通过四块各芯片搭载衬底3具有的布线、层间连接用布线26以及层间连接用端子27、电源接地用布线28以及电源接地用端子29、和外部端子连接用布线30以及外部端子31,分别用预定的电路线电连接了图中未显示的外部电源或外部装置。
这里,说明本发明者们为了把本实施例3的层叠型DRAM封装21的厚度与以往技术的图中未显示的层叠型DRAM封装的厚度做比较而进行的实验。具体而言,使用由以往的技术一体化的半导体芯片1和芯片搭载衬底103的组合,制造由与层叠型DRAM封装21同样结构构成的图中未显示的四层型半导体器件作为以往技术的层叠型DRAM封装。这时,以往技术的层叠型DRAM封装的厚度约为1.8mm。而本实施例的层叠型DRAM封装21中,各层的芯片连接高度能分别降低约20μm。而且,通过使内部引线等的厚度变薄,能使各层的连接高度再分别降低约15μm。作为结果可知:四层的芯片连接高度约降低了140μm,能进行薄壁化。
另外,通过使表面衬底23、电源接地衬底24和球层衬底25分别薄壁化,能使层叠型DRAM封装21全体实现合计约400μm的薄壁化。因此,本实施例的层叠型DRAM封装21能使图6中用H表示的该厚度变为约1.4mm。
如上所述,本实施例的半导体器件是多层构造的,是紧凑的。即根据本实施例的半导体器件的制造方法,能紧凑并且容易制造多层构造的半导体器件。并且,该薄壁化的效果随着层数增加而变得更有效。
须指出的是,本发明的半导体器件和半导体器件的制造方法并不局限于所述的实施例1~3。在不脱离本发明的宗旨的范围内,能对这些结构或步骤等的一部分变更为各种设定,或组合使用各种设定后实施。
例如Cu内部引线的剖面形状如果能形成与Au柱状突点相同程度的大小,实现窄间距化,则不局限于所述梯形。可以是长方形、正方形或半圆形等。Au柱状突点的形状也是同样的。例如实施例2的Au柱状突点11可以形成其顶端部11a向着芯片1一侧凹陷的形状。据此,内部引线4的顶端一侧端部能容易地突入(埋没)在柱状突点11中。
另外,内部引线和柱状突点的材料并不局限于铜和金。只要是能把半导体器件的电性能维持在所希望水准的材料就可以了。同样,芯片搭载衬底的形成材料也不局限于玻璃环氧树脂。另外,Sn电镀薄膜5可以不由所述无电解电镀法,而是由电解电镀法形成。
另外,如果在内部引线全体中的至少与柱状突点电连接的部分上形成了Sn电镀薄膜5就足够了。例如象实施例1的内部引线4那样,当它的剖面图形成了梯形时,如果至少在该顶端一侧端(上底)之上形成了电镀薄膜,就能抑制柱状突点和内部引线的连接部分的氧化。而且,能抑制半导体器件的电性能受损。下面,举一个例子简洁地说明这样的微小并且薄壁的电镀薄膜的形成方法。
首先,与实施例1同样,通过无电解电镀法形成内部引线,使其大致整个面地覆盖内部引线的连接了柱状突点的部分和其周围。接着,只在设置在内部引线的顶端一侧端部之上的电镀薄膜之上设置防止蚀刻用掩模。在该状态下,向着内部引线的左右两侧进行蚀刻,除去设置在它们之上的电镀薄膜。据此,在形成的比以往技术的内部引线104的宽度窄的内部引线的顶端一侧端部之上,能几乎排除形成时产生位置偏移的可能性,形成微小并且薄壁的电镀薄膜。
另外,根据这样的方法,能在不损坏柱状突点和内部引线的电连接状态的前提下,在除去电镀薄膜时,也一起蚀刻内部引线的左右两侧部,形成宽度更窄的长方形或正方形的内部引线。据此,能实现进一步的窄间距化。
另外,在实施例2中,内部引线对于柱状突点的相对大小和形状可以形成内部引线的大致全体突入(埋没)到柱状突点的内部中。据此,能使柱状突点和内部引线的连接区域增大,把该电连接状态保持为良好的状态,实现进一步的紧凑化。
另外,各密封树脂可以组合由彼此不同的多种材料形成的密封树脂,配置为对于半导体芯片彼此非对称。
预先通过实验和计算机模拟分析加在半导体芯片上的热和应力等各种负载,可以采用难以集中地对半导体芯片外加这些负载的材料和配置状态。
另外,芯片搭载衬底上搭载的半导体芯片并不局限于实施例3中描述的256MB的DRAM。也可以在一个半导体器件的内部使逻辑芯片和存储器芯片混合搭载。能按照所希望的半导体器件的性能和功能,适宜地采用适当的半导体芯片。
可以按照所希望的半导体器件的性能和功能,适当设计向一块芯片搭载衬底的搭载数、芯片搭载衬底以及中间衬底的数量、或半导体器件全体的内部结构等。根据本发明的半导体器件的制造方法,与其它的制造方法相比,能制造质量好并且紧凑的半导体器件。
那些熟知此技术的人会容易地进行修改并得到附加的优点。因此,本发明的体现并不局限于这里表示和描述的特殊细节和代表实施例。因此,在不偏离于附加的权利要求和它们的等价物所定义的本发明的概念的精神和范围的前提下,可以做出各种修改。
Claims (20)
1.一种半导体器件,包含:
在主面上设置了引线的芯片搭载构件,在所述引线上设置有覆盖预定位置表面的薄膜形状的电镀部;
在主面上设置有突点,并且该突点通过所述电镀部电连接所述引线,搭载在所述芯片搭载构件上的半导体芯片;
设置在所述半导体芯片和所述芯片搭载构件之间的密封构件。
2.根据权利要求1所述的半导体器件,包含:所述电镀部设置成大致整个面地覆盖所述引线和所述突点的连接部分及其周围。
3.根据权利要求1所述的半导体器件,包含:所述电镀部用锡通过无电解电镀法形成。
4.根据权利要求1所述的半导体器件,包含:所述突点的顶端部形成为向着所述引线一侧突出的形状。
5.根据权利要求1所述的半导体器件,包含:所述突点的顶端部形成为大致平坦的形状,并且在与所述引线的连接部分中,所述引线突入内部。
6.根据权利要求1所述的半导体器件,包含:所述半导体芯片和所述芯片搭载构件层叠为多层。
7.一种半导体器件的制造方法,包含:
把在主面上设置了突点的半导体芯片和在主面上设置了引线的芯片搭载构件相对配置,在所述引线上设置有覆盖预定位置表面的薄膜形状的电镀部;
在所述半导体芯片和所述芯片搭载构件之间设置密封构件;以及
通过由所述电镀部电连接所述突点和所述引线,并且使用所述密封构件密封接合所述半导体芯片和所述芯片搭载构件之间,连接密封所述半导体芯片和所述芯片搭载构件。
8.根据权利要求7所述的半导体器件的制造方法,包含:设置所述电镀部,使其大致整个面地覆盖所述引线和所述突点的连接部分及其周围。
9.根据权利要求7所述的半导体器件的制造方法,包含:使用锡通过无电解电镀法设置所述电镀部。
10.根据权利要求7所述的半导体器件的制造方法,包含:把所述突点形成为其顶端部向着所述引线一侧突出的形状。
11.根据权利要求7所述的半导体器件的制造方法,包含:把所述突点形成为其顶端部为大致平坦的形状,并且把所述半导体芯片和所述芯片搭载构件连接密封,使所述引线突入所述突点的内部。
12.根据权利要求7所述的半导体器件的制造方法,包含:在160℃以上200℃以下进行所述半导体芯片和所述芯片搭载构件的连接密封。
13.根据权利要求7所述的半导体器件的制造方法,包含:把通过上述连接密封而连接的所述半导体芯片和所述芯片搭载构件层叠多层。
14.一种半导体器件的制造方法,包含:把在主面上设置了突点的半导体芯片和在主面上设置了引线并且在所述主面上设置了密封构件的芯片搭载构件相对配置,在所述引线上设置有覆盖预定位置表面的薄膜形状的电镀部;
通过由所述电镀部电连接所述突点和所述引线,并且使用所述密封构件密封接合所述半导体芯片和所述芯片搭载构件之间,连接密封所述半导体芯片和所述芯片搭载构件。
15.根据权利要求14所述的半导体器件的制造方法,包含:设置所述电镀部,使其大致整个面地覆盖所述引线和所述突点的连接部分及其周围。
16.根据权利要求14所述的半导体器件的制造方法,包含:使用锡通过无电解电镀法设置所述电镀部。
17.根据权利要求14所述的半导体器件的制造方法,包含:把所述突点形成为其顶端部向着所述引线一侧突出的形状。
18.根据权利要求14所述的半导体器件的制造方法,包含:把所述突点形成为其顶端部为大致平坦的形状,并且把所述半导体芯片和所述芯片搭载构件连接密封,使所述引线突入所述突点的内部。
19.根据权利要求14所述的半导体器件的制造方法,包含:在160℃以上200℃以下进行所述半导体芯片和所述芯片搭载构件的连接密封。
20.根据权利要求14所述的半导体器件的制造方法,包含:把通过上述连接密封而连接的所述半导体芯片和所述芯片搭载构件层叠多层。
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KR20030051276A (ko) | 2003-06-25 |
KR100523495B1 (ko) | 2005-10-25 |
US20030111722A1 (en) | 2003-06-19 |
TW200301007A (en) | 2003-06-16 |
CN1266764C (zh) | 2006-07-26 |
JP2003179099A (ja) | 2003-06-27 |
US6897552B2 (en) | 2005-05-24 |
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