CN1324658C - 切削方法、切削装置及半导体器件的制造方法 - Google Patents
切削方法、切削装置及半导体器件的制造方法 Download PDFInfo
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- CN1324658C CN1324658C CNB2004100616984A CN200410061698A CN1324658C CN 1324658 C CN1324658 C CN 1324658C CN B2004100616984 A CNB2004100616984 A CN B2004100616984A CN 200410061698 A CN200410061698 A CN 200410061698A CN 1324658 C CN1324658 C CN 1324658C
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- 238000005520 cutting process Methods 0.000 title claims abstract description 158
- 239000004065 semiconductor Substances 0.000 title claims abstract description 121
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 239000011888 foil Substances 0.000 claims description 51
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 239000008393 encapsulating agent Substances 0.000 claims description 7
- 238000013316 zoning Methods 0.000 claims description 6
- 238000009434 installation Methods 0.000 claims description 5
- 238000003475 lamination Methods 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 238000005286 illumination Methods 0.000 claims 2
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 238000003466 welding Methods 0.000 description 40
- 238000007789 sealing Methods 0.000 description 13
- 229920005989 resin Polymers 0.000 description 11
- 239000011347 resin Substances 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 10
- 239000010949 copper Substances 0.000 description 10
- 230000035611 feeding Effects 0.000 description 10
- 238000007747 plating Methods 0.000 description 10
- 239000003566 sealing material Substances 0.000 description 10
- 239000000498 cooling water Substances 0.000 description 9
- CNQCVBJFEGMYDW-UHFFFAOYSA-N lawrencium atom Chemical compound [Lr] CNQCVBJFEGMYDW-UHFFFAOYSA-N 0.000 description 8
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 6
- 239000004411 aluminium Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000004744 fabric Substances 0.000 description 3
- 238000005755 formation reaction Methods 0.000 description 3
- 238000013007 heat curing Methods 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229920005992 thermoplastic resin Polymers 0.000 description 3
- 229910000640 Fe alloy Inorganic materials 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000004904 UV filter Substances 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 238000005868 electrolysis reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- XWUCFAJNVTZRLE-UHFFFAOYSA-N 7-thiabicyclo[2.2.1]hepta-1,3,5-triene Chemical compound C1=C(S2)C=CC2=C1 XWUCFAJNVTZRLE-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000008151 electrolyte solution Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 150000004291 polyenes Chemical class 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 125000004805 propylene group Chemical group [H]C([H])([H])C([H])([*:1])C([H])([H])[*:2] 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
- H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H01L2924/183—Connection portion, e.g. seal
- H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
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Abstract
一种切削方法及其切削装置,可有效地除去毛刺。该切削方法用于切削半导体器件组的边界部而分离成各个半导体器件,其中,半导体器件组由将具有延展性的第一层和第二层叠层在周边侧的半导体器件排列多个而构成,该方法包括:切削工序,将第一旋转体从所述半导体器件组的边界部向所述第一和所述第二层的叠层方向移动,并切削所述第一和所述第二层;以及毛刺除去工序,将与所述第一旋转体相比为软质并且宽度在其同等以上的第二旋转体从所述半导体器件组的已被切削的边界部向所述叠层方向移动,以除去所述第一层中的毛刺。
Description
技术领域
本发明涉及可有效地除去毛刺的切削方法、切削装置及半导体器件的制造方法。
背景技术
在半导体器件的制造工序中,利用被称为切片机和切片锯等的切削装置(参照以下所示的专利文献1),进行用于分离在半导体晶片(“半导体器件组”)上形成了规定的电路图形的各划分区域(芯片:“半导体器件”)的切削工序、用于从实施了芯片搭载和引线键合并且通过具有绝缘性的密封材料而成为密封状态的板状的引线框架(“半导体器件组”)中分离成各划分区域(封装:“半导体器件”)的切削工序。
这里,在半导体晶片的切削工序通过将该半导体晶片相对于旋转驱动的环状的切削刀片向切削线方向移动来进行。再有,在半导体晶片中,在具有硬并且脆性质的硅基板(“第二层”)上叠层将铝和铜等软质并具有延展性的金属作为材料的金属布线层(“第一层”),通过该切削工序切削在各芯片的边界上叠层的金属布线层和硅基板。
另一方面,密封后的引线框架的切削工序也同样通过将该引线框架相对于旋转驱动的环状的切削刀片向切削线方向移动来进行。再有,在密封后的引线框架中的各封装的至少侧面的一侧,在将位于安装面侧的铜、铝或铁/镍合金等作为材料的电极(“第一层”)上,叠层热固化性树脂或可热塑性树脂等硬并且脆的密封材料层(“第二层”),通过该切削工序切削在各芯片的边界上叠层的电极和密封材料层。
专利文献1特开2001-77055号公报(日本)
可是,在上述切削工序中,切削铜或铝等软质并且具有延展性的金属材料,而在切削这种金属材料时,已知在其切削剖面上产生毛刺(多余的材料、屑)。
这里,介由这样产生的毛刺,配置于芯片的表面周边部的电极(键合焊盘)间和配置于封装的安装面周边部的电极(外部)端子间可能短路,会增加产生半导体器件的制造不良。
而且,随着近年来的对于半导体器件的小型化、薄型化的发展,采用细间距技术,如果在窄小的间距间隔中发生毛刺,则上述课题很可能更突出。
发明内容
本发明是鉴于上述课题的发明,其目的在于提供可有效地除去毛刺的切削方法和切削装置。
主要用于解决上述课题的本发明,提供一种切削方法,用于切削半导体器件组的边界部而分离成各个半导体器件,其中,半导体器件组由将具有延展性的第一层和第二层叠层在周边侧的半导体器件排列多个而构成,其中,该方法包括:切削工序,将第一旋转体从所述半导体器件组的边界部向所述第一和所述第二层的叠层方向移动,并切削所述第一和所述第二层;以及毛刺除去工序,将与所述第一旋转体相比为软质并且旋转轴方向的宽度在所述第一旋转体的旋转轴方向的宽度以上的第二旋转体从所述半导体器件组的已被切削的边界部向所述第一和所述第二层的叠层方向移动,以除去所述第一层中的毛刺。
此外,本发明提供一种用于分离上述各个半导体器件的切削方法,切削半导体器件组的边界部而分离成各个半导体器件,其中,半导体器件组由将具有延展性的第一层和第二层叠层在周边侧的半导体器件排列多个而构成,其中,该方法包括:第一切削工序,将第一旋转体从作为所述第一层侧的所述半导体器件组的边界部向所述第一和所述第二层的叠层方向移动,并切削所述第一层,同时除去所述第一层中的毛刺;以及第二切削工序,将与所述第一旋转体相比为硬质并且旋转轴方向的宽度低于所述第一旋转体的旋转轴方向的宽度的第二旋转体从切削了所述第一层的所述边界部向所述第一和所述第二层的叠层方向移动,并切削所述第二层。
根据本发明,在切削第一层和第二层时,可以有效地除去具有半导体器件的第一层中的毛刺。
本发明的其他特征通过附图和说明书的论述将更清楚。
根据本发明,可以提供能够有效地除去毛刺的切削方法和切削装置。
附图说明
图1是表示本发明一实施方式的半导体器件的安装面的立体图。
图2是本发明一实施方式的半导体器件的剖面图。
图3是说明本发明一实施方式的平行双轴型切削装置的图。
图4是说明本发明一实施方式的对置双轴型切削装置的图。
图5是说明本发明一实施方式的刀片周边部结构的图。
图6是说明本发明一实施方式的半导体器件的制造工序的流程图。
图7是说明本发明一实施方式的半导体器件的制造工序的图。
图8是说明本发明一实施方式的半导体器件的制造工序的图。
图9是说明本发明一实施方式的半导体器件的制造工序的图。
图10是说明本发明一实施方式的半导体器件的制造工序的图。
图11是说明本发明一实施方式的半导体器件的制造工序的图。
图12是说明本发明一实施方式的半导体器件的制造工序的图。
图13是说明本发明一实施方式的半导体器件的制造工序的图。
图14是说明本发明另一实施方式的半导体器件的制造工序的流程图。
图15是说明本发明另一实施方式的半导体器件的制造工序的图。
图16是说明本发明另一实施方式的半导体器件的制造工序的图。
具体实施方式
以下,根据附图来具体地说明本发明的实施方式。
<半导体器件的结构>
图1是表示根据本发明的切削方法制造的半导体器件100的一实施方式的立体图。
可将本发明的半导体器件100假设为无引线型切削方法,如图所示,该切削方法从介由接合材料与VQFN(Very Quad Flat Nonleaded Package)和VSON(Very Thin Small Outline Nonleaded Package)等印刷基板接合一侧的安装面(底面)露出外部端子106。再有,本发明的半导体器件100当然不限定于无引线型,也可以为BGA(Ball Grid Array)等其他的CSP(Chip SizePackage)。此外,也可以采用FBGA(Fine-Pitch BGA)和FLGA(Fine-PitchLand Grid Array)等印刷基板或挠性基板的封装。以下,举例说明无引线型。
图2是半导体器件100的剖面图。如图所示,在铜等构成的管芯焊盘101上,介由银膏等用于管芯键合的接合材料102将半导体元件103固定(管芯键合)。在半导体元件103的表面上形成电极焊盘(未图示),该电极焊盘和铜等构成的键合焊盘104介由金属细线105进行电连接(引线键合)。再有,键合焊盘104采用在该半导体器件100的上面侧具有突起的形状,以便提高与密封材料107的贴紧性(锚效应),不用说,也可以形成除去了该突起部的形状。
在管芯焊盘101、半导体元件103和键合焊盘104分别电连接的状态下,通过被具有绝缘性的密封材料107密封而形成密封体110。再有,作为密封材料107,可以采用环氧树脂等热固化性树脂(转移模法的情况)、聚酰亚胺树脂、对聚苯硫等可热塑性树脂(注射模法的情况)等。
对于密封后的管芯焊盘101,可使其底面不露出到密封体110的安装面,也可以露出。在不露出管芯焊盘101的底面时,能可靠地保护管芯焊盘101和半导体元件103的绝缘性。在露出管芯焊盘101的底面时,可以使没有密封该底面部分的该半导体器件100的厚度薄。此外,还可以将该半导体器件100产生的热从该管芯焊盘101的底面放出。
对于密封后的键合焊盘104,使其底面露出到密封体110的安装面。这里,露出密封体110的安装面的键合焊盘104的部位介由接合材料300形成用于将该半导体器件100接合(安装)在印刷布线板200上的外部端子106。再有,在外部端子106上,形成焊料镀敷或金属镀敷(镍、金、银等)的镀敷层108。
以上,是半导体器件100的概要说明。如图2所示,在该半导体器件100的侧面一侧,在铜或铝等柔软(软质)并且具有延展性的材料构成的键合焊盘(“第一层”)104上,叠层比热固化性树脂或可热塑性树脂等比键合焊盘104硬(硬质)并且具有脆的性质的密封材料107的层(以下,称为密封材料层107,“第二层”)。
<切削装置的结构>
在制造图1和图2所示的半导体器件100的工序中,有用于从将半导体器件100排列多个而构成的导电箔700中分离出各个半导体器件100的工序。这里,在切削导电箔700的各半导体器件100的边界部时,同时切削键合焊盘104和密封材料层107,但由于键合焊盘104由上述那样的软质并且具有延展性的材料构成,所以在该键合焊盘104的切削剖面上容易产生毛刺。
因此,在本发明的切削方法中,为了抑制这样产生的毛刺,如图3所示,采用平行双轴型切削装置(平行双轴型切片机或分割装置:“第一切削装置”)1000,该装置双轴配有在前端安装了环状刀片的电机内置主轴,并且该双轴的主轴平行。再有,以下说明平行双轴型切削装置1000的情况,但如图4所示,也可以采用将双轴部分的主轴对置配置的对置双轴型切削装置(对置双轴型切片机或分割装置:“第一切削装置”)。
平行双轴型切削装置1000包括:在前端安装了切削刀片(方案1和方案13所述的“第一旋转体”)400的主轴410;在前端安装了毛刺除去刀片(方案1和方案13所述的“第二旋转体”)500的主轴510;粘贴了用于切割的粘结片600的用于吸附保持对应的导电箔700的工作台800;用于在将毛刺除去后的导电箔700运送到旋转清洗部(未图示)前进行预清洗的预清洗喷嘴900等。
切削刀片400在后述的全切割工序中使用,成为具有可同时切削在导电箔700的边界部中形成的键合焊盘104和密封材料层107的硬度的刀片。作为切削刀片400,可以采用在圆形基板的周边上配有金刚石砂轮的金刚石刀片等。
毛刺除去刀片500在后述的毛刺除去工序中使用,成为用于除去在导电箔700切削后的切削剖面上产生的毛刺的刀片。再有,毛刺除去刀片500由比切削刀片400软质的坯料构成。此外,毛刺除去刀片500最好采用具有与构成键合焊盘104的材料的软质并且延展性对应的软硬度的刀片,以便容易地除去键合焊盘104的切削剖面上产生的毛刺。此外,由于毛刺除去刀片500的旋转轴方向的宽度在切削刀片400的旋转轴方向的宽度以上,在将切削刀片400切削进给一次时,可以同时沿两侧的切削剖面除去毛刺。
在主轴510的前端,除了上述毛刺除去刀片500以外,还可以安装用于研磨加工的抛光轮(方案1和方案13所述的“第二层”)。再有,抛光轮是将布剪成圆形并以一定的厚度缝在一起、或在布的外周面上涂敷研磨剂等。作为抛光轮的坯材,例如,除了上述的布以外,还可以采用铁、铜和锌等的合金、塑料等。
主轴410和510并排配置在沿导电箔700的切削线的X轴方向(参照图3)上。此外,主轴410和510分别通过未图示的驱动部件在垂直于切削线的Y轴方向(参照图3)上被分度(index)进给,同时在作为叠层了键合焊盘104和密封材料层107的方向的Z轴方向(参照图3)上被切入进给。然后,工作台800沿导电箔700的切削线向X轴方向(参照图3)切削进给。这样,通过主轴410和510、工作台800的一连串的动作,进行对于导电箔700的一切削线的切削。再有,工作台800可向θ方向旋转驱动,以使切削刀片400和毛刺除去刀片500位于导电箔700的切削线上。
可是,平行双轴型切削装置1000中的切削刀片400和毛刺除去刀片500的周边部为图5所示的结构。这里,仅说明切削刀片400的周边部的结构。
首先,切削刀片400被在其下部有开口部的凸缘盖420覆盖(参照图3)。在凸缘盖420中包括:设置在工作台800的切削进给侧的切削水喷嘴430;在对切削刀片400进行加工情况下的这一侧和里侧(主轴410侧)以可夹入切削刀片400而设置的一对冷却水喷嘴440a和440b;设置在工作台800切削进给侧的一对清洗水喷嘴450a和450b。
这里,如果在后述的全切割工序(S607)和/或毛刺除去工序(S608)的过程中产生的切削屑(被除去的“毛刺”)残存在导电箔700的安装面上,则在后面干燥该导电箔700时难以除去该切削屑。因此,在后述的全切割工序(S607)或毛刺除去工序(S608)的至少其中一个过程中,为了用从各喷嘴(430、440、450)射出的水流使该切削屑流出到导电箔700的安装面的外周侧,设定各喷嘴(430、440、450)中的各自水的射出方向。由此,该切削屑不易残存在导电箔700的安装面上,可以避免该切削屑引起的电极间的短路等制造不良。
再有,本发明的切削装置例如在采用干法方式切削的情况下,由于不需要切削水、冷却水和清洗水,所以也可以是不配有各喷嘴(430、440、450)的结构。
<半导体器件的制造工序>
下面,适当参照图7至图13,同时根据图6的流程图来说明图1和图2所示的半导体器件100的制造工序。
管芯键合~镀敷层形成
首先,准备以铜、铝或铁/镍合金等作为材料的具有导电性的板状的导电箔(引线框架)。如图7所示,在导电箔700的上下周边上设定分度孔730,用于各工序的定位。此外,在导电箔700中,具有多个搭载部(“划分区域”)750的块710经由起到吸收导电箔700的应力作用的缝隙(slit)720来配置。再有,在块710的周边的内侧上,设定切削时定位的标记740。
在该导电箔700上形成抗蚀剂图形后,通过将该抗蚀剂图形作为掩模并实施腐蚀,在该导电箔700中的各搭载部750中形成管芯焊盘101和键合焊盘104。再有,将键合焊盘104配置在搭载部750的周围,而相邻的搭载部750的相互的键合焊盘104处于连接的状态。
对于这种状态的导电箔700,将从半导体晶片中预先分割的半导体元件103介由接合材料102固定(管芯键合)在形成于搭载部750中的管芯焊盘101上(S600)。然后,通过固化工序使接合材料102固化后(S601),将配置在半导体元件103的表面周边部的电极焊盘(未图示)和搭载部750周围形成的键合焊盘104介由金属细线105进行电连接(引线键合)(S602)。再有,这里,作为半导体元件103的安装方式,示出引线键合的正面安装的情况,但也可以在半导体元件103的电极焊盘(未图示)上形成金属焊盘来进行背面安装。
然后,为了将键合焊盘104作为外部端子106露出,对于导电箔700实施集中的密封(S603)。其结果,将键合焊盘104露出在安装面侧的密封体110形成在搭载部750中。
可是,如果在导电箔700的安装面侧粘贴了聚酰亚胺等树脂片(未图示)的状态下进行密封,则可通过该树脂片来防止键合焊盘104的安装面侧被密封材料107密封。而且,通过柱塞(未图示)等产生的加压,覆盖密封材料107的树脂片的部位略微侵入密封体110的内侧。
即,通过采用树脂片,外部端子106容易露出密封体110的安装面,所以最好是在密封工序(S603)之前将树脂片预先粘贴在导电箔700上。再有,在采用树脂片的情况下,需要密封工序(S603)后从导电箔700中除去树脂片的工序(S604)。
这里,在树脂片除去后的导电箔700中,在相邻的密封体110的相互的外部端子106连结的状态下露出安装面侧。因此,根据电解镀敷法,在将规定的外部端子106连接到阴极电极端子后,可对外部端子106上集中形成镀敷层108(S605)。再有,电解镀敷法是在铜镀敷浴等的电解溶液中设置阳极和阴极电极,通过在将被镀敷物作为阴极电极配置并在电极间施加电压,在被镀敷物的表面上析出电子而形成镀敷层。
UV片粘贴~封装分离
接着,如图8所示,在与密封后的导电箔700中的安装面正相反的上面,在粘贴了分割粘结片600的状态下(S606),将该导电箔700通过真空吸附保持在平行双轴型切削装置1000的工作台800上。
这里,作为分割粘结片600,采用对于以聚烯等作为坯料的可透过紫外线的基材膜的表面形成了紫外线固化型粘结材料的紫外线固化型粘结片(UV片)。再有,紫外线固化型粘结材料是通过将紫外线照射规定时间而固化,其粘结力下降的粘结材料(例如丙烯类粘结材料)。
如果导电箔700与分割粘结片600一起被吸附保持在工作台800上,则平行双轴型切削装置1000检测形成在导电箔700的安装面侧的各半导体器件100的边界部(切削线)。然后,在将主轴410在Y轴方向(参照图8)分度进给,同时在Z轴方向(参照图8)切入进给时,实施对该检测出的切削线上的切削刀片400的定位等。
再有,如图9所示,在将主轴410向Z轴方向(参照图8)切入进给时,通过贯通键合焊盘104和密封材料层107并移动至分割粘结片600,实施全分割。
此外,在上述定位后,在旋转驱动主轴410和切削刀片400时,将切削水从切削水喷嘴430向切削刀片400的刀尖射出,同时将冷却水从一对冷却水喷嘴440a和440b射出到切削刀片400的侧面。而且,将清洗水从一对清洗水喷嘴450a和450b对着隔开切削刀片400的导电箔700上的这一侧和里侧射出。再有,这里,作为湿法方式的切削情况,在切削时使用切削水、冷却水和清洗水,但也可以使用切削水、冷却水和清洗水的其中一种水。此外,进行干法方式的切削时,在切削时也可以不使用切削水、冷却水和清洗水。
在这种状态下,通过将吸附保持了导电箔700的工作台800在X轴方向(参照图8)切削进给,实施对该检测出的一切削线的切削。然后,通过将主轴410和切削刀片400分度进给一间距量,切削后面的切削线,实施全切割工序(S607)。
可是,在按现有的干法方式进行切削时,在全切割工序的过程中产生的切削屑1110在密封后的导电箔700上被捕获,成为产生电极间短路等问题的原因。此外,分割粘结片600对于具有某一面积以上的物体(芯片、封装)的固定性优异,但对于该切削屑1110那样的微小物体的固定性差。即,如果切削屑1110固定(捕获)在分割粘结片600上,则被区分为立即分离的物体。
因此,本发明的切削装置也可以采用湿法方式的切削,同时通过切削水、冷却水或清洗水的至少其中之一,从分割区域(导电箔700的安装面)向作为其周围的分割粘结片600一侧形成水流。由此,在全切割工序的过程中产生的切削屑1110不易残存在分割区域上,而容易在该分割区域的周围的分割粘结片600上被捕获(参照图8)。
可是,如图10所示,在全切割工序(S607)后形成的切削剖面、特别是在键合焊盘106的切削剖面上容易产生毛刺1100。因此,与上述的切削刀片400的定位同样,进行对该切削的切削线上的毛刺除去刀片500的定位,实施以下的毛刺除去工序(S608)。
毛刺除去工序(S608)与全切割工序(S607)同样,在从各喷嘴(430、440、450)射出水的状态下,通过将工作台800在X轴方向(参照图8)上切削进给来进行。再有,在毛刺除去工序(S608)中,也可以使用从各喷嘴(430、440、450)射出的各种水的其中一种,而在采用干法方式的切削时,也可以不使用切削水、冷却水和清洗水。这里,如图11所示,与主轴510一起旋转驱动的毛刺除去刀片500的侧面一侧为产生毛刺1100的切削剖面,所以如图12所示,毛刺1100被除去。
接着,毛刺除去工序(S608)后的导电箔700经由预清洗喷嘴900进行预清洗,然后被运送到旋转清洗部(未图示)进行旋转清洗。可是,通过进行预清洗和旋转清洗,上述切削工序过程中特意在分割粘结片600上捕获的切削屑1110有可能通过预清洗水或旋转清洗水的流动而再次在导电箔700上捕获。因此,本发明的切削装置在进行预清洗和旋转清洗时,必需通过预清洗水或旋转清洗水形成从分割区域(导电箔700的安装面)向其周围的分割粘结片600一侧的水流。
在上述的毛刺除去工序(S608)或旋转清洗工序后,解除对于工作台800的吸附保持,粘贴在分割粘结片600上的导电箔700被运送到用于进行紫外线照射的规定位置。然后,如图13所示,对于分割粘结片600的背面,介由紫外线灯1210来照射紫外线(S609)。由此,分割粘结片600中的紫外线照射部固化,粘结力下降,导电箔700从分割粘结片600中分离。
此时,介由紫外线切割坯材构成的紫外线滤色器1200,如果仅对粘贴了导电箔700的分割区域照射紫外线,则维持切削屑1110被捕获的其他区域的粘结力。由此,通过在后面的工序中运送粘贴在分割粘结片600上的导电箔700时的振动等,在导电箔700的安装面上不易捕获切削屑1110,所以在紫外线照射时最好使用紫外线滤色器1200。
接着,将粘贴在分割粘结片600上的导电箔700运送到用于进行分离工序的规定位置。然后,通过膨胀器夹具(未图示)拉伸分割粘结片600,从导电箔700中分离各密封体110、即各半导体器件100(S610)。对于这种分离后的各个半导体器件100,实施外观检查、工艺检查、电特性检查等各种检查工序(S611),仅挑选作为合格品的半导体器件100最终出厂。
以上,根据本发明,通过上述的全切割工序和毛刺除去工序两次切削工序,从导电箔700中切削分离各半导体器件100。再有,在毛刺除去工序中,使用比全切割工序中使用的切削刀片400软质并且旋转轴方向的宽度在切削刀片400的旋转轴方向的宽度以上的毛刺除去刀片500来进行。因此,可以有效地除去键合焊盘104的切削剖面中的毛刺,可以提供除去了毛刺的半导体器件100。
<其他实施方式>
关于本发明的实施方式,根据上述实施方式具体地进行了说明,但并不限于此,在不脱离其主要精神的范围内可进行各种变更。
半导体器件的其他制造工序
作为本发明的其他切削方法中使用的切削装置(“第二切削装置”),在上述平行双轴型切削装置1000和对置双轴型切削装置(参照图4)中,采用将主轴410的前端上安装的切削刀片400变更为半切割刀片(方案6和方案14所述的“第一旋转体”)460,而将主轴510的前端上安装的毛刺除去刀片500变更为全切割刀片(方案6和方案14所述的“第二旋转体”)。
半切割刀片460是用于切割至少叠层在导电箔700的各密封体110的边界部上的键合焊盘104的刀片,可以采用具有与构成键合焊盘104的软质材料并且延展性对应的软硬度的刀片。
全切割刀片560是用于完全切削在半切割刀片460切削后残存的密封材料层107的刀片,由比半切割刀片460硬质的坯材构成。再有,作为全切割刀片560,例如可以采用金刚石刀片等。此外,全切割刀片560的旋转轴方向的宽度低于半切割刀片460的旋转轴方向的宽度,以便在键合焊盘104的切削剖面上不再产生毛刺。
接着,使用图14的流程图,说明根据本发明的另一切削方法的半导体器件的制造工序。这里,如果要说明与上述实施方式的制造工序(参照图6)的不同点,则首先在分割粘结片600粘贴在相对于密封后的导电箔700的安装面的正反面上后(S1406),实施半切割工序(S1407)。
如图15所示,半切割工序(S1407)在旋转驱动安装于主轴410的前端上的半切割刀片460的状态下,在垂直于导电箔700的安装面的键合焊盘104的厚度方向(“第一及第二层的叠层方向”)上移动,切削键合焊盘104。在此时的使用半切割刀片460的切削中,在键合焊盘104的切削剖面上不易产生毛刺。
在该状态下,如图16所示,在将安装在主轴510前端上的全切割用刀片560旋转驱动的状态下,向半切割后残留的密封材料层107的厚度方向(“第一及第二层的叠层方向”)移动至分割粘结片600,实施完全切削该密封材料层107的全切割工序(S1408)。然后,实施全切割工序以后的后工序,由导电箔700来制造各个半导体器件100。
半导体晶片
此外,在上述实施方式中,示出了作为半导体器件组排列多个半导体器件100而构成的导电箔700的例子,但本发明的切削方法也可以应用于在硅等具有又硬又脆性质的半导体基板(“第二层”)中的各划分区域上,叠层了用铜和铝等软质并且具有延展性的材料构成的金属布线层(“第一层”)的半导体晶片。即,通过本发明的切削方法和切削装置,在从半导体晶片中分离各半导体芯片时,可以有效地除去金属布线层中的毛刺,可以提供除去了毛刺的半导体芯片。
Claims (11)
1.一种半导体器件的制造方法,用于切削半导体器件组的边界部而分离成各个半导体器件,其中,半导体器件组由将具有延展性的第一层和第二层叠层在周边侧的半导体器件排列多个而构成,其特征在于,该方法包括:
切削工序,将第一旋转体从所述半导体器件组的边界部向所述第一和所述第二层的叠层方向移动,并切削所述第一和所述第二层;以及
毛刺除去工序,将与所述第一旋转体相比为软质并且旋转轴方向的宽度在所述第一旋转体的旋转轴方向的宽度以上的第二旋转体从所述半导体器件组的已被切削的边界部向所述第一和所述第二层的叠层方向移动,以除去所述第一层中的毛刺。
2.如权利要求1所述的切削方法,其特征在于,所述第二旋转体具有与所述第一层的硬度对应的可除去所述毛刺的硬度。
3.如权利要求1所述的切削方法,其特征在于:
在所述切削工序或所述毛刺除去工序的至少一个中,为了将已被除去的毛刺流出到所述半导体器件组的外周侧,向所述边界部喷射水。
4.如权利要求1任何一项所述的切削方法,其特征在于:
在所述切削工序的前工序中,在基材上形成了粘结材料层而构成的粘结片中,在所述粘结材料层上,粘贴所述半导体器件组。
5.如权利要求4所述的切削方法,其特征在于:
所述粘结片是通过紫外线照射进行固化而粘结力降低的紫外线固化型粘结片,
在所述毛刺除去工序的后工序中,从所述粘结片中的所述基材面侧,仅对粘贴了所述半导体器件组的区域照射紫外线。
6.如权利要求4所述的切削方法,其特征在于:
所述粘结片是通过紫外线照射进行固化而粘结力降低的紫外线固化型粘结片,
在所述毛刺除去工序的后工序中,从所述粘结片中的所述基材面侧,从与粘贴了所述半导体器件组的正相反的另一面侧,仅对粘贴了所述半导体器件组的区域照射紫外线。
7.如权利要求1所述的切削方法,其特征在于:为了在介由接合材料与安装基板接合的安装面的周围露出作为所述第一层的电极,通过作为所述第二层的具有绝缘性的密封材料来密封导电箔的各划分区域中电连接的该电极和半导体元件而形成所述半导体器件组。
8.如权利要求7所述的切削方法,其特征在于:所述半导体器件组在作为所述第二层的半导体基板中的各划分区域上,叠层形成作为所述第一层的金属布线层。
9.一种切削装置,用于切削半导体器件组的边界部而分离成各个半导体器件,其中,半导体器件组由将具有延展性的第一层和第二层叠层在周边侧的半导体器件排列多个而构成,其特征在于,该装置包括:
切削部件,将第一旋转体从所述半导体器件组的边界部向所述第一和所述第二层的叠层方向移动,并切削所述第一和所述第二层;以及
毛刺除去部件,将与所述第一旋转体相比为软质并且旋转轴方向的宽度在所述第一旋转体的旋转轴方向的宽度以上的第二旋转体从所述半导体器件组的已被切削的边界部向所述第一和所述第二层的叠层方向移动,以除去所述第一层中的毛刺。
10.一种切削装置,用于切削半导体器件组的边界部而分离成各个半导体器件,其中,半导体器件组由将具有延展性的第一层和第二层叠层在周边侧的半导体器件排列多个而构成,其特征在于,该装置包括:
第一切削部件,将第一旋转体从作为所述第一层侧的所述半导体器件组的边界部向所述第一和所述第二层的叠层方向移动,并切削所述第一层,同时除去所述第一层中的毛刺;以及
第二切削部件,将与所述第一旋转体相比为硬质并且旋转轴方向的宽度低于所述第一旋转体的旋转轴方向的宽度的第二旋转体从切削了所述第一层的所述边界部向所述第一和所述第二层的叠层方向移动,并切削所述第二层。
11.一种半导体器件的制造方法,用于切削半导体器件组的边界部而分离成各个半导体器件,其中,半导体器件组由将具有延展性的第一层和第二层叠层在周边侧的半导体器件排列多个而构成,其特征在于,该方法包括:
第一切削工序,将第一旋转体从作为所述第一层侧的所述半导体器件组的边界部向所述第一和所述第二层的叠层方向移动,并切削所述第一层,同时除去所述第一层中的毛刺;以及
第二切削工序,将与所述第一旋转体相比为硬质并且旋转轴方向的宽度低于所述第一旋转体的旋转轴方向的宽度的第二旋转体从切削了所述第一层的所述边界部向所述第一和所述第二层的叠层方向移动,并切削所述第二层。
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JPH06326185A (ja) * | 1993-05-17 | 1994-11-25 | Hitachi Ltd | ダイシング装置およびダイシング用ブレード |
JPH06338562A (ja) * | 1993-05-31 | 1994-12-06 | Nec Kansai Ltd | 半導体ウェーハのダイシング装置 |
JP4394210B2 (ja) | 1999-09-08 | 2010-01-06 | 株式会社ディスコ | 切削方法 |
JP2002093753A (ja) * | 2000-09-14 | 2002-03-29 | Seiko Epson Corp | ダイシングブレード及び半導体装置の製造方法 |
JP2003124149A (ja) * | 2001-10-09 | 2003-04-25 | Mitsui High Tec Inc | 半導体装置の製造方法 |
US6841414B1 (en) * | 2002-06-19 | 2005-01-11 | Amkor Technology, Inc. | Saw and etch singulation method for a chip package |
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2003
- 2003-07-16 JP JP2003275400A patent/JP2005039088A/ja active Pending
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- 2004-06-30 CN CNB2004100616984A patent/CN1324658C/zh not_active Expired - Fee Related
- 2004-07-16 US US10/892,398 patent/US7056768B2/en active Active
Patent Citations (5)
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JPS5572045A (en) * | 1978-11-24 | 1980-05-30 | Mitsubishi Electric Corp | Apparatus for removing resin burr removing of resin sealing type semiconductor device |
JPH01128696A (ja) * | 1987-11-13 | 1989-05-22 | Nec Corp | ボタン電話装置の局線回路 |
JPH08124881A (ja) * | 1994-10-28 | 1996-05-17 | Nec Corp | ダイシングテープ及びそれを用いた半導体装置の組立方 法 |
JP2000068238A (ja) * | 1998-08-18 | 2000-03-03 | Seiko Epson Corp | 被切削物の切削方法及び切削装置 |
JP2002184721A (ja) * | 2000-11-27 | 2002-06-28 | Samsung Electronics Co Ltd | 垂直型ウェーハソーイング装置 |
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CN1591787A (zh) | 2005-03-09 |
JP2005039088A (ja) | 2005-02-10 |
US20050012193A1 (en) | 2005-01-20 |
US7056768B2 (en) | 2006-06-06 |
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