CN1702839A - 制造半导体器件的方法和半导体衬底的支撑结构 - Google Patents

制造半导体器件的方法和半导体衬底的支撑结构 Download PDF

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CN1702839A
CN1702839A CNA2005100713705A CN200510071370A CN1702839A CN 1702839 A CN1702839 A CN 1702839A CN A2005100713705 A CNA2005100713705 A CN A2005100713705A CN 200510071370 A CN200510071370 A CN 200510071370A CN 1702839 A CN1702839 A CN 1702839A
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adhesive phase
semiconductor substrate
semiconductor device
substrate
supporting construction
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CNA2005100713705A
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CN1702839B (zh
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山野孝治
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Shinko Electric Co Ltd
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Shinko Electric Co Ltd
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Abstract

本发明公开了一种制造半导体器件的方法。这种方法包括研磨与在其上形成有半导体器件元件的半导体衬底的第一主表面相反的半导体衬底的第二主表面的第一步骤、在第一步骤之后将被构造成支撑半导体衬底的支撑结构连接到第二主表面的第二步骤和使半导体衬底与支撑结构分离的第三步骤。

Description

制造半导体器件的方法 和半导体衬底的支撑结构
技术领域
本发明涉及一种制造半导体器件的方法和用于该方法的半导体衬底的支撑结构。
背景技术
随着近年来对更小且更高性能的半导体器件日益增长的需要，要求半导体的封装具有更小的尺寸并提供更高的性能。
例如，人们需要减小半导体器件的厚度。为满足这种需要，需要通过在所谓背面研磨处理中增加研磨量来减小封装的半导体衬底的厚度，在背面研磨处理中半导体衬底的背面或与在其上形成半导体器件元件的表面相反的表面被研磨以减小半导体衬底的厚度。
附图1所示为具有CSP(芯片尺寸封装)结构的半导体器件10的示意图，这种CSP结构是可以减小半导体器件的尺寸的一种结构实例。
参考附图1，半导体器件10包括半导体衬底11，半导体衬底11可以是Si晶片等，并且具有在其上形成半导体器件元件的器件表面11A和与器件表面11A相反的背面11B。由Al等制造的电极焊盘12形成在器件表面11A上。由SiN等制造的钝化层12A被形成以覆盖除了形成有电极焊盘12之外的器件表面11A。钝化层12A通过由树脂比如聚酰亚胺制造的钝化层13覆盖。此外，这个钝化层13通过密封树脂层15覆盖。
由Cu制造的布线部分14形成在钝化层12A和钝化层13中的开孔中以连接到电极焊盘12。布线部分14被构图以部分地延伸到钝化层13上。
布线柱16垂直地形成在形成于钝化层13上的布线部分14上以连接到布线部分14。每个布线柱16的侧面通过密封树脂层15包围，但它的上端面从密封树脂层15中暴露出来。阻挡金属层17形成在每个布线柱16的暴露的上端部上。由焊料等制造的突起球18形成在阻挡金属层17上。
在这种具有CSP结构类型的半导体器件中，将半导体器件元件连接到金属突起的布线高度致密地形成在半导体衬底上。因此，可以减小半导体器件的尺寸。
为了进一步减小半导体器件的尺寸或厚度，半导体衬底的厚度D需要被减小。因此，通过研磨背面11B使半导体器件更薄的尝试已经在半导体器件封装技术中实施。
然而，半导体衬底的厚度减小增加了缺陷比如半导体衬底的损坏或翘曲，因此降低了半导体器件的生产量。已经试图防止由通过在半导体衬底的背面上形成钝化膜来减小半导体衬底的厚度引起的缺陷(参见例如日本专利公开No.2002-231854和No.2002-270720)。
然而，如果钝化膜形成在半导体衬底的背面上，半导体器件变得更厚。因此，半导体器件的厚度的减小仍然困难。
在半导体衬底的背面上形成钝化膜的另一问题是在形成半导体器件的过程中钝化膜通常与半导体衬底部分地分离。特别是，具有与半导体衬底的特性不同的特性(例如刚性)的钝化膜在将半导体衬底切割成为小片的所谓的切割过程中通常与半导体衬底分离。这种钝化膜的部分分离也降低了半导体器件的产量。
发明内容
本发明的一般目的是提供一种制造半导体器件的新颖且有效的方法和半导体衬底的支撑结构以解决上述的至少一个问题。
本发明的具体目的是提供一种减小了为制造薄的半导体器件而具有薄的半导体衬底的半导体器件的制造缺陷的制造半导体器件的方法和用于半导体衬底的支撑结构。
根据本发明的一方面，提供一种制造半导体器件的方法，这种方法包括研磨与在其上形成有半导体器件元件的半导体衬底的第一主表面相反的半导体衬底的第二主表面的第一步骤、在第一步骤之后将被构造成支撑半导体衬底的支撑结构连接到第二主表面的第二步骤和使半导体衬底与支撑结构分离的第三步骤。
通过制造半导体器件的这种方法，在防止损坏半导体衬底的同时可以稳定地制造薄的半导体器件。
优选地，本制造半导体器件的方法进一步包括在第二步骤和第三步骤之间切割半导体衬底的切割过程。应用这种方法，在防止切割过程中损坏半导体衬底的同时可以制造半导体器件。
也是优选地，本制造半导体器件的方法进一步包括在第二步骤和第三步骤之间以树脂层覆盖第一主表面的密封过程。这种方法可以防止在密封过程中损坏半导体器件。
也是优选地，本制造半导体器件的方法进一步包括在第三步骤之前在要连接到半导体器件元件的第一主表面上形成布线部分的布线步骤。应用这种方法，可以形成更高密度的布线。
也是优选地，在本制造半导体器件的方法中，支撑结构包括形成为与半导体衬底接触的粘合剂层和支撑粘合剂层的支撑层，该粘合剂层包括粘合到半导体衬底的第一粘合剂层、被构造成粘合到支撑层并具有大于第一粘合剂层之粘合力的粘合力的第二粘合剂层和置于第一粘合剂层和第二粘合剂层之间的底层。应用这种方法，可以将半导体衬底与粘合剂层分离并可以将粘合剂层与支撑层分离。
根据本发明的另一方面，提供一种用于半导体衬底的支撑结构，该支撑结构适合于粘合到半导体衬底并包括形成为粘合到半导体衬底的粘合剂层和支撑粘合剂层的支撑层，其中粘合剂层包括粘合到半导体衬底的第一粘合剂层、被构造成粘合到支撑层并具有大于第一粘合剂层之粘合力的粘合力的第二粘合剂层和置于第一粘合剂层和第二粘合剂层之间的底层。
这种支撑结构可以保护薄的半导体衬底不受到损坏和翘曲，同时支撑着半导体衬底。此外，这种支撑结构允许半导体衬底与粘合剂层分离并允许粘合剂与支撑层分离。
优选地，在用于半导体衬底的支撑结构中，支撑层包括Si晶片。如果这样，支撑层可以容易地形成。
根据本发明的这些方面，可以减小为制造薄的半导体器件而具有薄的半导体衬底的半导体器件的制造缺陷。
附图说明
附图1所示为具有CSP结构的半导体器件的示意性横截面视图；
附图2所示为根据第一实施例的支撑结构的示意性横截面视图；
附图3A至3P所示为根据第二实施例制造半导体器件的方法。
具体实施方式
下文的描述参考附图提供了本发明的实例性的实施例。
[第一实施例]
附图2所示为根据第一实施例用于半导体衬底的支撑结构200的示意性横截面视图。
参考附图2，本实施例的支撑结构200是一种适合于粘合到半导体衬底的类型，包括形成为粘合到半导体衬底的粘合剂层202和被构造成支撑粘合剂层202的支撑层201。粘合剂层202包括粘合到半导体衬底的第一粘合剂层202A和具有大于第一粘合剂层202A之粘合力的粘合力并粘合到支撑层201的第二粘合剂层202B。
由PET(聚对苯二甲酸乙二醇酯)、PEN(聚萘二甲酸乙二醇酯)等制成的底层202C插入在第一粘合剂层202A和第二粘合剂层202B之间。
在本实施例的支撑结构200连接到半导体衬底的背面时，第一粘合剂层202A粘合到半导体衬底的背面。
在典型的半导体器件制造过程中，半导体衬底经过所谓的背面研磨过程，在这个过程中研磨半导体衬底的背面以减小它的厚度。然而，具有由此减小厚度的半导体衬底可能翘曲或损坏。在背面研磨过程中减小半导体衬底的厚度之后半导体衬底的这种翘曲或损坏可以通过将本实施例的支撑结构200连接到半导体衬底的背面防止。
调节第一粘合剂层202A的粘合力以允许连接到第一粘合剂层202A的半导体衬底可以与支撑结构200分离。
因此，与常规的技术不同的是，半导体衬底的钝化层(或支撑层)没有保留在完成的半导体器件的背面上。因此，在半导体器件的制造过程比如封装过程中可以防止半导体衬底翘曲或损坏，同时可以减小半导体器件的厚度。
如前文所述，第二粘合剂层202B的粘合力大于第一粘合剂层202A的粘合力。因此，在半导体衬底与支撑结构200分离时，粘合剂层202仍然保留在支撑层201上，而不与支撑层201分开(分离)。
在另一方面，以比分离半导体衬底所要求的力更大的力可以使包括第一粘合剂层202A和第二粘合剂层202B的粘合剂层202与支撑层201分开(分离)。更具体地说，在第二粘合剂层202B和支撑层201之间的界面上粘合剂层202与支撑层201分离。
这种构造允许粘合剂层202和支撑层201单个地再使用。例如，如果支撑结构200受到冲击因此支撑层201被损坏，则粘合剂层202可以与支撑层201分离以便与新的支撑层201一起再使用。在另一方面，如果粘合剂层202被损坏或者由于粘合力的丧失而变得不稳定，则支撑层201可以与受到损坏或不可使用的粘合剂层202分离以与新的粘合剂层202再利用。
粘合剂层202优选被形成为使第一粘合剂层202A和第二粘合剂层202B连接在由PET、PEN等制成的底层202C的每个侧面上。这样，粘合剂层202可以被容易地形成为具有不同的粘合力的上部表面和下部表面并与半导体衬底和支撑层201两者可分离。
支撑层201优选具有预定的刚性以支撑半导体衬底并保护半导体衬底不受到损坏和翘曲。
优选地，具有耐热和耐化学能力以在半导体器件制造过程(封装过程)中的各种处理中防止损坏、腐蚀和蚀刻。也是优选地，具有与半导体衬底的物理特性相同或类似的物理特性比如热膨胀系数。
支撑层201优选由Si晶片形成以满足上文描述的要求。具体地，在通过支撑结构200支撑的半导体衬底由Si晶片形成的情况下，有利的是，不需要处理支撑结构，因为支撑结构200和被支撑的半导体衬底基本具有相同的尺寸和材料以及它们容易获得。此外，通过使用所谓回收的Si晶片作为支撑层201可以降低成本，通过蚀刻或研磨在其上事先形成有半导体器件元件和薄膜的表面形成这种晶片。
应该理解的是，如果满足上述的要求，玻璃片或陶瓷片可用作支撑层201。
下文描述使用本实施例的支撑结构制造半导体器件的方法。
[第二实施例]
附图3A至3P所示为根据第二实施例的步骤制造半导体器件步骤的方法。
首先，在附图3A所示的过程中，制备在其上形成有半导体器件元件的衬底101。例如，由半导体衬底比如Si晶片形成的衬底101具有在其上形成有半导体器件元件的器件表面101A。也形成由Al等制成的电极焊盘102以连接到该器件的一部分。在衬底101的器件表面101A和与器件表面101A相反的背面101B之间的距离(即衬底101的厚度dA)大约为700微米，但并不限于这个厚度。
由SiN等制成的钝化层103被形成为覆盖器件表面101A，同时通过孔暴露电极焊盘102。由聚酰亚胺等形成的钝化层104形成在钝化层103上，同时也通过孔暴露电极焊盘102。
然后在附图3所示的过程中，由金属比如Cr和Ti制成的金属粘合层105通过溅射形成在电极焊盘102和钝化层104上。此外，由Cu制成的籽晶层106通过溅射形成在金属粘合层105上。
然后，在附图3C所示的过程中，形成光致抗蚀剂层107。然后掩模(未示)形成在光致抗蚀剂层107上，并通过曝光和显影对光致抗蚀剂进行构图。
在构图上清除了光致抗蚀剂的地方形成电连接到电极焊盘102的布线部分108。使用籽晶层106作为电源层通过Cu电解电镀形成布线部分108。
然后在附图3D所示的过程中，通过有机溶剂等清除光致抗蚀剂。
然后在附图3E所示的过程中，由光敏干膜等制成的光致抗蚀剂层109被连接以覆盖布线部分108和籽晶层106。通过使用掩模进行曝光和显影对光致抗蚀剂层109进行构图。布线柱110直立地形成在其上清除了光致抗蚀剂的布线部分108上。通过使用籽晶层106作为电源层进行Cu电解电镀形成布线柱110。
例如具有Ni/Pd/Au结构的电镀层111然后通过电解电镀形成在布线柱110上。电镀层111在改善粘性的同时还用作阻挡层(或用于防止扩散)。优选地，电镀层111的上端部表面与光致抗蚀剂层109的上端部表面基本平齐。
光致抗蚀剂层109的厚度d1例如为100微米，虽然并不限于这个厚度。
然后在附图3F所示的过程中，由树脂等制成的背面研磨带112连接在光致抗蚀剂层109和电镀层111上。背面研磨带112具有例如150微米的厚度d2。在后面对衬底101的背面101B研磨的过程中，背面研磨带112用作器件表面101A、布线柱110、电镀层111和布线部分108的钝化层，并且也使得在研磨机(未示)中容易保持(卡住)衬底101。
然后在附图3G所示的过程中，通过研磨机对衬底101的背面101B进行研磨以便减小衬底101的厚度到厚度dB。该厚度例如是大约200微米至300微米，虽然并不限于这个厚度。
然后在附图3H所示的过程中，衬底101连接到附图2的支撑结构200。在附图3H中，与已经描述的元件相同的元件以相同的参考标号表示，并不再进一步描述。
如附图2所示的支撑结构200包括支撑层201和在其上形成的粘合剂层202。粘合剂层202包括底层202C和分别连接在底层202C的上表面和下表面上的第一粘合剂层202A和第二粘合剂层202B。
在附图3H所示的过程中，衬底101的背面101B连接到支撑结构200的第一粘合剂层202A。第一粘合剂层202A的粘合力被调节到小于第二粘合剂层202B的粘合力。因此，在后面的过程中衬底101容易与粘合剂层202分离，同时可以防止粘合剂层202与支撑层201分离。
在这个过程以及后面的过程中支撑层201防止了衬底101的翘曲，并且也防止了对衬底101的损坏以改善了半导体器件的生产量。
在支撑层201由Si晶片制成的情况下，支撑层201和衬底101具有包括热膨胀系数的相同的物理特性。因此，支撑层201随着衬底101的膨胀和变形而膨胀和变形，因此防止了衬底101的断裂。
在这个过程中保护或保持其背面连接到上述的支撑结构的半导体衬底的方法在包括为减小衬底的厚度而进行研磨过程的半导体器件制造过程中特别有效。此外，这个方法适合于满足更高性能和更小的半导体器件的新近的要求。
在本实施例中描述的支撑结构200通过第一粘合剂层202A连接衬底101时，支撑结构200可以与衬底101分离。因此，与形成在衬底的背面上并且不容易与其分离的常规的钝化膜不同的是，支撑结构200使得可以实现更薄的半导体器件而不增加厚度。
然后在附图3I的过程中，去除背面研磨带112。然后在附图3J所示的过程中，分离光致抗蚀剂层109。
然后在附图3K所示的过程中，通过湿蚀刻去除籽晶层106的暴露的部分，然后通过湿蚀刻暴露的粘合层105的部分也通过湿蚀刻去除。因此，没有被布线部分108覆盖的籽晶层106和金属粘合层105通过蚀刻去除。
然后在附图3L所示的过程中，形成模制的树脂层113以覆盖钝化层104、布线部分108和布线柱110的侧壁，然后加热并固化模制的树脂。应该注意，电镀层111的上端部暴露在用于电连接的模制的树脂上。
树脂层113可替换地通过树脂膜的层叠形成。
然后在附图3M所示的过程中，通过电镀层111电连接到布线柱110的焊接突起114形成在电镀层111上。
然后在附图3N所示的过程中，具有连接到其上的衬底101的支撑结构200连接在具有切割框的切割带115上以为后面的切割过程准备。在附图3N所示的过程中，除了切割过程(即将衬底101切割成小片的过程)之外完成了半导体器件(半导体芯片)的生产。即，获得了具有衬底101、器件表面101A、电极焊盘102、钝化层103、金属粘合层105、籽晶层106、布线部分108、布线柱110、电镀层111、模制的树脂层113和焊接突起114的半导体器件(半导体芯片)100。虽然附图3N仅仅示出了一个半导体器件100，但是也可以具有在衬底101延伸的方向上在平面上以阵列形成的多个半导体器件100。
然后在附图30所示的过程中，通过切割技术切割衬底101以形成彼此分离的多个半导体器件100。切粒机优选被控制为仅切割通过衬底101的模制的树脂层113而不是支撑结构200上。
然后在附图3P所示的过程中，通过切割技术彼此分离的半导体器件(半导体小片)100通过使用切片拾取器等使每个半导体器件100的背面101B与第一粘合剂层202A分离而与支撑结构200分开，因此获得了完成的半导体器件100。
这样，衬底101容易与支撑结构200分开，由此防止了由于使用支撑结构200而使半导体器件100的厚度增加。半导体器件100的厚度因此可以减小。在常规的情况下，连接在衬底的背面上的钝化膜和衬底在切割过程中一起被切割，通常产生了缺陷比如钝化膜和芯片的部分分离或损失。这种钝化膜的部分分离或损失例如导致了半导体器件的厚度和形状的变化。这个实施例可以防止这些问题，因此可以稳定地制造具有相同形状的半导体器件，即提供形状的再现性。
在本实施例中，在支撑结构200连接到衬底101之后的过程中，因为通过支撑结构200支撑或保持衬底101，因此防止了衬底101的断裂和翘曲。
例如，支撑结构200用于防止在如附图3I所示取消背面研磨带112的过程、如附图3J所示分离光致抗蚀剂层109的过程、如附图3K所示蚀刻籽晶层106和粘合层105的过程以及如附图3M所示形成焊接突起114的过程中衬底101的断裂和翘曲。
特别是，在如附图3L所示形成模制的树脂的过程中，可以防止由于反作用力引起对衬底101的损坏，在通过蚀刻固化模制的树脂时这种反作用力可能施加给包括形成在衬底101上的模制的树脂的层上。
此外，在如附图30所示的切割过程中，在防止缺陷比如对在衬底101中的芯片的损坏的同时可以稳定地执行切割操作。
在使半导体器件100与支撑结构200分离的步骤中，半导体器件100可以与粘合剂层202分离而不使粘合剂层202与支撑层201分离，因为第一粘合剂层202A的粘合力小于第二粘合剂层202B的粘合力。
以大于分离衬底101所要求的力的力可以使包括第一粘合剂层202A和第二粘合剂层202B的粘合剂层202与支撑层201分开(分离)。更具体地说，粘合剂层202与在第二粘合剂层202B和支撑层201之间的界面上的支撑层201分离。这个结构允许粘合剂层202和支撑层201分别被再使用。
由于可以再使用本实施例的支撑结构200，因此可以减小衬底101的保护所要求的成本。此外，支撑层201和粘合剂层202可以独立地再使用，因此也减小了维护成本。
虽然上述的实施例简化了制造具有CSP结构的半导体器件的方法，但是应该注意，本发明并不限于这些。本发明可适用于制造具有研磨半导体衬底的背面以减小半导体衬底的厚度的所谓的背面研磨过程的制造半导体器件的其它方法中。如果本发明应用到这些方法中，则这些方法通过防止衬底的断裂和翘曲可以改善半导体器件的生产量，允许衬底与支撑结构分开，因此以制造具有CSP结构的半导体器件的方法可以实现减小半导体器件的厚度。
虽然根据优选的实施例已经描述了本发明，但是很显然，在不脱离如附加的权利要求中阐述的本发明的范围的前提下本领域普通技术人员可以做出变型和修改。
本发明基于2004年5月28日在日本专利局申请的日本在先申请No.2004-159871，在此以引用参考的方式将其全部内容并入在本申请中。

Claims (7)

1.一种制造半导体器件的方法，包括：
研磨与在其上形成有半导体器件元件的半导体衬底第一主表面相反的半导体衬底第二主表面的第一步骤；
在第一步骤之后将被构造成支撑半导体衬底的支撑结构连接到第二主表面的第二步骤；和
使半导体衬底与支撑结构分离的第三步骤。
2.如权利要求1所述的制造半导体器件的方法，进一步包括：
在第二步骤和第三步骤之间切割半导体衬底的切割过程。
3.如权利要求1所述的制造半导体器件的方法，进一步包括：
在第二步骤和第三步骤之间以树脂层覆盖第一主表面的密封过程。
4.如权利要求1所述的制造半导体器件的方法，进一步包括：
在第三步骤之前在要连接到半导体器件元件的第一主表面上形成布线部分的布线步骤。
5.如权利要求1所述的制造半导体器件的方法，
其中支撑结构包括：
形成为与半导体衬底接触的粘合剂层；和
支撑粘合剂层的支撑层；
该粘合剂层包括：
粘合到半导体衬底的第一粘合剂层；
粘合到支撑层并具有大于第一粘合剂层之粘合力的粘合力
的第二粘合剂层；和
置于第一粘合剂层和第二粘合剂层之间的底层。
6.一种用于半导体衬底的支撑结构，该支撑结构适合于粘合到半导体衬底上，包括：
形成为粘合到半导体衬底的粘合剂层；和
支撑粘合剂层的支撑层；
其中粘合剂层包括
粘合到半导体衬底的第一粘合剂层；
粘合到支撑层并具有大于第一粘合剂层之粘合力的粘合力
的第二粘合剂层；和
置于第一粘合剂层和第二粘合剂层之间的底层。
7.如权利要求6所述的用于半导体衬底的支撑结构，支撑层包括Si晶片。
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