JP4851214B2 - パッケージ基板の分割方法 - Google Patents
パッケージ基板の分割方法 Download PDFInfo
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- JP4851214B2 JP4851214B2 JP2006083737A JP2006083737A JP4851214B2 JP 4851214 B2 JP4851214 B2 JP 4851214B2 JP 2006083737 A JP2006083737 A JP 2006083737A JP 2006083737 A JP2006083737 A JP 2006083737A JP 4851214 B2 JP4851214 B2 JP 4851214B2
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- cutting blade
- package substrate
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- 239000000758 substrate Substances 0.000 title claims description 54
- 238000000034 method Methods 0.000 title claims description 30
- 238000005520 cutting process Methods 0.000 claims description 145
- 230000001105 regulatory effect Effects 0.000 claims description 10
- 239000002184 metal Substances 0.000 description 18
- 229910052751 metal Inorganic materials 0.000 description 18
- 229920005989 resin Polymers 0.000 description 12
- 239000011347 resin Substances 0.000 description 12
- 238000004140 cleaning Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000011218 segmentation Effects 0.000 description 3
- 239000006061 abrasive grain Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
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- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
22 デバイス
26 パッケージ基板
30 パッケージデバイス
40 第一の切削ブレード
40a,40b 切刃
41a,41b 規制溝
43 第二の切削ブレード
CL 分割予定ライン
E1 第一の側部
E2 第二の側部
Claims (1)
- デバイス側に突出して電極が形成された分割予定ラインによって複数のデバイスが区画され形成されたパッケージ基板を保持し、送り機構によって移動可能な移動基台に支持された回転可能なチャックテーブルと、前記パッケージ基板を支持するダイシングフレームと、前記ダイシングフレームを支持するフレームクランプと、前記分割予定ラインを規制する間隔で切刃が2枚配されて前記パッケージ基板に規制溝形成を行う第一の切削ブレードと、前記第一の切削ブレードの切刃の幅より大きい幅で構成された第二の切削ブレードとを有する切削装置を用い、前記パッケージ基板を前記第一の切削ブレードおよび前記第二の切削ブレードによって切削し個々のパッケージデバイスに分割するとともに前記電極を各パッケージデバイス毎に分極するパッケージ基板の分割方法であって、
前記分割予定ラインを規制する第一の側部と第二の側部とに前記第一の切削ブレードを位置づけて切削し、前記分割予定ラインに2条の規制溝を形成して前記電極と前記分割予定ラインとを分断する規制溝形成工程と、
前記規制溝形成工程後に、前記2条の規制溝の外側より幅が狭く該2条の規制溝の内側より幅の広い前記第二の切削ブレードを該2条の規制溝の中央部に位置づけて前記分割予定ラインを切削して個々のパッケージデバイスに分割する分割工程と、を含む
ことを特徴とするパッケージ基板の分割方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006083737A JP4851214B2 (ja) | 2006-03-24 | 2006-03-24 | パッケージ基板の分割方法 |
US11/723,639 US7344960B2 (en) | 2006-03-24 | 2007-03-21 | Separation method for cutting semiconductor package assemblage for separation into semiconductor packages |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006083737A JP4851214B2 (ja) | 2006-03-24 | 2006-03-24 | パッケージ基板の分割方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007258590A JP2007258590A (ja) | 2007-10-04 |
JP4851214B2 true JP4851214B2 (ja) | 2012-01-11 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2006083737A Active JP4851214B2 (ja) | 2006-03-24 | 2006-03-24 | パッケージ基板の分割方法 |
Country Status (2)
Country | Link |
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US (1) | US7344960B2 (ja) |
JP (1) | JP4851214B2 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008258383A (ja) * | 2007-04-04 | 2008-10-23 | Spansion Llc | 半導体装置及びその製造方法 |
JP5610673B2 (ja) * | 2008-04-15 | 2014-10-22 | 新日本無線株式会社 | リードフレームの設計方法 |
JP2012109327A (ja) * | 2010-11-16 | 2012-06-07 | Disco Abrasive Syst Ltd | 分割方法 |
JP2013069814A (ja) * | 2011-09-21 | 2013-04-18 | Renesas Electronics Corp | 半導体装置の製造方法 |
JP5960532B2 (ja) * | 2012-07-25 | 2016-08-02 | 株式会社ディスコ | パッケージ基板の加工方法 |
CN109152214B (zh) | 2017-06-19 | 2023-02-24 | 松下知识产权经营株式会社 | 布线基板及其制造方法 |
JP6999450B2 (ja) | 2018-03-02 | 2022-01-18 | 株式会社ディスコ | ブレードカバー |
JP7391465B2 (ja) * | 2019-03-26 | 2023-12-05 | 株式会社ディスコ | パッケージチップの製造方法 |
JP2020194894A (ja) * | 2019-05-28 | 2020-12-03 | 株式会社ディスコ | デバイスチップの製造方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03296254A (ja) * | 1990-02-06 | 1991-12-26 | Dainippon Printing Co Ltd | リードフレーム |
US6413150B1 (en) * | 1999-05-27 | 2002-07-02 | Texas Instruments Incorporated | Dual dicing saw blade assembly and process for separating devices arrayed a substrate |
JP2002118080A (ja) * | 2000-10-06 | 2002-04-19 | Disco Abrasive Syst Ltd | 半導体プレートの分割方法および切削ブレード |
JP2002261193A (ja) * | 2001-03-06 | 2002-09-13 | Hitachi Ltd | 半導体装置の製造方法 |
TW498443B (en) * | 2001-06-21 | 2002-08-11 | Advanced Semiconductor Eng | Singulation method for manufacturing multiple lead-free semiconductor packages |
US6841414B1 (en) * | 2002-06-19 | 2005-01-11 | Amkor Technology, Inc. | Saw and etch singulation method for a chip package |
JP2004023007A (ja) * | 2002-06-20 | 2004-01-22 | Sony Corp | 半導体パッケージ用リードフレーム及び半導体パッケージ並びに半導体パッケージの製造方法。 |
JP2004228166A (ja) * | 2003-01-20 | 2004-08-12 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
GB0303285D0 (en) * | 2003-02-13 | 2003-03-19 | Atlantic Technology Uk Ltd | Electronic component packaging |
JP2005039088A (ja) | 2003-07-16 | 2005-02-10 | Sanyo Electric Co Ltd | 切削方法、切削装置及び半導体装置の製造方法 |
JP2007165789A (ja) * | 2005-12-16 | 2007-06-28 | Olympus Corp | 半導体装置の製造方法 |
-
2006
- 2006-03-24 JP JP2006083737A patent/JP4851214B2/ja active Active
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2007
- 2007-03-21 US US11/723,639 patent/US7344960B2/en active Active
Also Published As
Publication number | Publication date |
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JP2007258590A (ja) | 2007-10-04 |
US20070224781A1 (en) | 2007-09-27 |
US7344960B2 (en) | 2008-03-18 |
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