JP4643464B2 - パッケージ基板の分割方法および分割装置 - Google Patents
パッケージ基板の分割方法および分割装置 Download PDFInfo
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- JP4643464B2 JP4643464B2 JP2006042282A JP2006042282A JP4643464B2 JP 4643464 B2 JP4643464 B2 JP 4643464B2 JP 2006042282 A JP2006042282 A JP 2006042282A JP 2006042282 A JP2006042282 A JP 2006042282A JP 4643464 B2 JP4643464 B2 JP 4643464B2
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- package substrate
- dividing
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- 239000000758 substrate Substances 0.000 title claims description 49
- 238000000034 method Methods 0.000 title claims description 26
- 238000005520 cutting process Methods 0.000 claims description 67
- 239000002184 metal Substances 0.000 claims description 62
- 229910052751 metal Inorganic materials 0.000 claims description 62
- 229920005989 resin Polymers 0.000 claims description 26
- 239000011347 resin Substances 0.000 claims description 26
- 238000005530 etching Methods 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000011218 segmentation Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005323 electroforming Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000032258 transport Effects 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
14 電極
22 デバイス
24 充填樹脂
25 樹脂層
26 パッケージ基板
40 スクライブ手段
41 罫書き溝
42 切削ブレード
56 切削手段
CL 分割予定ライン
Claims (3)
- デバイスが配設される領域を区画する分割予定ラインに沿って複数の電極が形成された金属枠体と、前記分割予定ラインによって区画された領域に配設された複数のデバイスと、前記複数のデバイスが配設された側に樹脂が充填され金属層と樹脂層とで前記デバイスがパッケージングされたパッケージ基板をデバイス毎に分割するパッケージ基板の分割方法であって、
回転自在なそろばん珠形状の超硬チップを備えるスクライブ手段によって前記分割予定ラインを罫書き、前記金属層に所定深さの罫書き溝を形成する溝形成工程と、
該溝形成工程で形成された前記罫書き溝に切削手段の切削ブレードを位置づけて前記金属層と前記樹脂層とを切断して前記パッケージ基板を個々のデバイス毎に分割する分割工程と、
を含むことを特徴とするパッケージ基板の分割方法。 - 前記溝形成工程において形成する前記罫書き溝の深さは、前記金属層の厚みの1/2以上であることを特徴とする請求項1に記載のパッケージ基板の分割方法。
- デバイスが配設される領域を区画する分割予定ラインに沿って複数の電極が形成された金属枠体と、前記分割予定ラインによって区画された領域に配設された複数のデバイスと、前記複数のデバイスが配設された側に樹脂が充填され金属層と樹脂層とで前記デバイスがパッケージングされたパッケージ基板をデバイス毎に分割するパッケージ基板の分割装置であって、
前記分割予定ラインを罫書き、前記金属層に所定深さの罫書き溝を形成する回転自在なそろばん珠形状の超硬チップを備えるスクライブ手段と、
該スクライブ手段で形成された前記罫書き溝に位置づけられて前記金属層と前記樹脂層とを切断して前記パッケージ基板を個々のデバイス毎に分割する切削ブレードを有する切削手段と、
を備えたことを特徴とするパッケージ基板の分割装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006042282A JP4643464B2 (ja) | 2006-02-13 | 2006-02-20 | パッケージ基板の分割方法および分割装置 |
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JP2006035789 | 2006-02-13 | ||
JP2006042282A JP4643464B2 (ja) | 2006-02-13 | 2006-02-20 | パッケージ基板の分割方法および分割装置 |
Publications (2)
Publication Number | Publication Date |
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JP2007242643A JP2007242643A (ja) | 2007-09-20 |
JP4643464B2 true JP4643464B2 (ja) | 2011-03-02 |
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JP2006042282A Active JP4643464B2 (ja) | 2006-02-13 | 2006-02-20 | パッケージ基板の分割方法および分割装置 |
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JP (1) | JP4643464B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20140022499A (ko) * | 2012-08-13 | 2014-02-25 | 주식회사 엠엔비그린어스 | 고무배합용 유기 가황제, 이의 제조방법 및 이를 포함하는 고무배합 조성물 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0982741A (ja) * | 1995-09-19 | 1997-03-28 | Seiko Epson Corp | チップキャリアの構造およびその製造方法 |
JPH11171574A (ja) * | 1997-12-12 | 1999-06-29 | Disco Abrasive Syst Ltd | スクライバー |
JPH11191561A (ja) * | 1997-12-26 | 1999-07-13 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2000036474A (ja) * | 1998-07-16 | 2000-02-02 | Murata Mfg Co Ltd | 電子部品の製造方法 |
JP2002026217A (ja) * | 2000-07-04 | 2002-01-25 | Mitsui High Tec Inc | 半導体装置の切出し方法及び装置 |
JP2003031595A (ja) * | 2001-07-17 | 2003-01-31 | Sharp Corp | 半導体パッケージの製造方法および半導体パッケージ |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7553700B2 (en) * | 2004-05-11 | 2009-06-30 | Gem Services, Inc. | Chemical-enhanced package singulation process |
-
2006
- 2006-02-20 JP JP2006042282A patent/JP4643464B2/ja active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0982741A (ja) * | 1995-09-19 | 1997-03-28 | Seiko Epson Corp | チップキャリアの構造およびその製造方法 |
JPH11171574A (ja) * | 1997-12-12 | 1999-06-29 | Disco Abrasive Syst Ltd | スクライバー |
JPH11191561A (ja) * | 1997-12-26 | 1999-07-13 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2000036474A (ja) * | 1998-07-16 | 2000-02-02 | Murata Mfg Co Ltd | 電子部品の製造方法 |
JP2002026217A (ja) * | 2000-07-04 | 2002-01-25 | Mitsui High Tec Inc | 半導体装置の切出し方法及び装置 |
JP2003031595A (ja) * | 2001-07-17 | 2003-01-31 | Sharp Corp | 半導体パッケージの製造方法および半導体パッケージ |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20140022499A (ko) * | 2012-08-13 | 2014-02-25 | 주식회사 엠엔비그린어스 | 고무배합용 유기 가황제, 이의 제조방법 및 이를 포함하는 고무배합 조성물 |
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JP2007242643A (ja) | 2007-09-20 |
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