JP2007258590A - パッケージ基板の分割方法 - Google Patents
パッケージ基板の分割方法 Download PDFInfo
- Publication number
- JP2007258590A JP2007258590A JP2006083737A JP2006083737A JP2007258590A JP 2007258590 A JP2007258590 A JP 2007258590A JP 2006083737 A JP2006083737 A JP 2006083737A JP 2006083737 A JP2006083737 A JP 2006083737A JP 2007258590 A JP2007258590 A JP 2007258590A
- Authority
- JP
- Japan
- Prior art keywords
- cutting
- cutting blade
- dividing
- package substrate
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000000758 substrate Substances 0.000 title claims description 51
- 238000005520 cutting process Methods 0.000 claims abstract description 142
- 230000001105 regulatory effect Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 230000000052 comparative effect Effects 0.000 abstract 1
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 18
- 229910052751 metal Inorganic materials 0.000 description 18
- 229920005989 resin Polymers 0.000 description 12
- 239000011347 resin Substances 0.000 description 12
- 238000004140 cleaning Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000011218 segmentation Effects 0.000 description 3
- 239000006061 abrasive grain Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
【解決手段】分割予定ラインCLを規制する第一の側部E1と第二の側部E2とに比較的薄い第一の切削ブレード40を位置づけて切削し、分割予定ラインCLに2条の規制溝41a,41bを形成して電極14と分割予定ラインCLとを分断する規制溝形成工程と、2条の規制溝41a,41bの外側より幅が狭く該2条の規制溝41a,41bの内側より幅の広い比較的厚い第二の切削ブレード43を該2条の規制溝41a,41bの中央部に位置づけて分割予定ラインCLを切削して個々のパッケージデバイスに分割する分割工程と、を含むようにした。
【選択図】 図4
Description
22 デバイス
26 パッケージ基板
30 パッケージデバイス
40 第一の切削ブレード
40a,40b 切刃
41a,41b 規制溝
43 第二の切削ブレード
CL 分割予定ライン
E1 第一の側部
E2 第二の側部
Claims (3)
- デバイス側に突出して電極が形成された分割予定ラインによって複数のデバイスが区画され形成されたパッケージ基板を、切削ブレードによって切削し個々のパッケージデバイスに分割するとともに前記電極を各パッケージデバイス毎に分極するパッケージ基板の分割方法であって、
前記分割予定ラインを規制する第一の側部と第二の側部とに第一の切削ブレードを位置づけて切削し、前記分割予定ラインに2条の規制溝を形成して前記電極と前記分割予定ラインとを分断する規制溝形成工程と、
前記2条の規制溝の外側より幅が狭く該2条の規制溝の内側より幅の広い第二の切削ブレードを該2条の規制溝の中央部に位置づけて前記分割予定ラインを切削して個々のパッケージデバイスに分割する分割工程と、
を含むことを特徴とするパッケージ基板の分割方法。 - 前記第一の切削ブレードは、前記分割予定ラインを規制する間隔を持って切刃が2枚配されていることを特徴とする請求項1に記載のパッケージ基板の分割方法。
- 前記第一の切削ブレードの幅は、前記第二の切削ブレードの幅より細いことを特徴とする請求項1または2に記載のパッケージ基板の分割方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006083737A JP4851214B2 (ja) | 2006-03-24 | 2006-03-24 | パッケージ基板の分割方法 |
US11/723,639 US7344960B2 (en) | 2006-03-24 | 2007-03-21 | Separation method for cutting semiconductor package assemblage for separation into semiconductor packages |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006083737A JP4851214B2 (ja) | 2006-03-24 | 2006-03-24 | パッケージ基板の分割方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007258590A true JP2007258590A (ja) | 2007-10-04 |
JP4851214B2 JP4851214B2 (ja) | 2012-01-11 |
Family
ID=38534021
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006083737A Active JP4851214B2 (ja) | 2006-03-24 | 2006-03-24 | パッケージ基板の分割方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7344960B2 (ja) |
JP (1) | JP4851214B2 (ja) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009259927A (ja) * | 2008-04-15 | 2009-11-05 | New Japan Radio Co Ltd | リードフレームの設計方法 |
JP2012109327A (ja) * | 2010-11-16 | 2012-06-07 | Disco Abrasive Syst Ltd | 分割方法 |
JP2014024136A (ja) * | 2012-07-25 | 2014-02-06 | Disco Abrasive Syst Ltd | パッケージ基板の加工方法 |
KR20190104906A (ko) | 2018-03-02 | 2019-09-11 | 가부시기가이샤 디스코 | 블레이드 커버 |
US10629792B2 (en) | 2017-06-19 | 2020-04-21 | Panasonic Intellectual Property Management Co., Ltd. | Wiring substrate and production method thereof |
JP2020161615A (ja) * | 2019-03-26 | 2020-10-01 | 株式会社ディスコ | パッケージチップの製造方法 |
JP2020194894A (ja) * | 2019-05-28 | 2020-12-03 | 株式会社ディスコ | デバイスチップの製造方法 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008258383A (ja) * | 2007-04-04 | 2008-10-23 | Spansion Llc | 半導体装置及びその製造方法 |
JP2013069814A (ja) * | 2011-09-21 | 2013-04-18 | Renesas Electronics Corp | 半導体装置の製造方法 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03296254A (ja) * | 1990-02-06 | 1991-12-26 | Dainippon Printing Co Ltd | リードフレーム |
JP2000357672A (ja) * | 1999-05-27 | 2000-12-26 | Texas Instr Inc <Ti> | ダイシングのこ刃集成体 |
JP2002118080A (ja) * | 2000-10-06 | 2002-04-19 | Disco Abrasive Syst Ltd | 半導体プレートの分割方法および切削ブレード |
JP2002261193A (ja) * | 2001-03-06 | 2002-09-13 | Hitachi Ltd | 半導体装置の製造方法 |
JP2004023007A (ja) * | 2002-06-20 | 2004-01-22 | Sony Corp | 半導体パッケージ用リードフレーム及び半導体パッケージ並びに半導体パッケージの製造方法。 |
JP2004228166A (ja) * | 2003-01-20 | 2004-08-12 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
EP1447847A2 (en) * | 2003-02-13 | 2004-08-18 | Atlantic Technology (UK) Ltd. | Lead frame for an electronic component package |
JP2007165789A (ja) * | 2005-12-16 | 2007-06-28 | Olympus Corp | 半導体装置の製造方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW498443B (en) * | 2001-06-21 | 2002-08-11 | Advanced Semiconductor Eng | Singulation method for manufacturing multiple lead-free semiconductor packages |
US6841414B1 (en) * | 2002-06-19 | 2005-01-11 | Amkor Technology, Inc. | Saw and etch singulation method for a chip package |
JP2005039088A (ja) | 2003-07-16 | 2005-02-10 | Sanyo Electric Co Ltd | 切削方法、切削装置及び半導体装置の製造方法 |
-
2006
- 2006-03-24 JP JP2006083737A patent/JP4851214B2/ja active Active
-
2007
- 2007-03-21 US US11/723,639 patent/US7344960B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03296254A (ja) * | 1990-02-06 | 1991-12-26 | Dainippon Printing Co Ltd | リードフレーム |
JP2000357672A (ja) * | 1999-05-27 | 2000-12-26 | Texas Instr Inc <Ti> | ダイシングのこ刃集成体 |
JP2002118080A (ja) * | 2000-10-06 | 2002-04-19 | Disco Abrasive Syst Ltd | 半導体プレートの分割方法および切削ブレード |
JP2002261193A (ja) * | 2001-03-06 | 2002-09-13 | Hitachi Ltd | 半導体装置の製造方法 |
JP2004023007A (ja) * | 2002-06-20 | 2004-01-22 | Sony Corp | 半導体パッケージ用リードフレーム及び半導体パッケージ並びに半導体パッケージの製造方法。 |
JP2004228166A (ja) * | 2003-01-20 | 2004-08-12 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
EP1447847A2 (en) * | 2003-02-13 | 2004-08-18 | Atlantic Technology (UK) Ltd. | Lead frame for an electronic component package |
JP2007165789A (ja) * | 2005-12-16 | 2007-06-28 | Olympus Corp | 半導体装置の製造方法 |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009259927A (ja) * | 2008-04-15 | 2009-11-05 | New Japan Radio Co Ltd | リードフレームの設計方法 |
JP2012109327A (ja) * | 2010-11-16 | 2012-06-07 | Disco Abrasive Syst Ltd | 分割方法 |
JP2014024136A (ja) * | 2012-07-25 | 2014-02-06 | Disco Abrasive Syst Ltd | パッケージ基板の加工方法 |
US10629792B2 (en) | 2017-06-19 | 2020-04-21 | Panasonic Intellectual Property Management Co., Ltd. | Wiring substrate and production method thereof |
KR20190104906A (ko) | 2018-03-02 | 2019-09-11 | 가부시기가이샤 디스코 | 블레이드 커버 |
JP2020161615A (ja) * | 2019-03-26 | 2020-10-01 | 株式会社ディスコ | パッケージチップの製造方法 |
JP7391465B2 (ja) | 2019-03-26 | 2023-12-05 | 株式会社ディスコ | パッケージチップの製造方法 |
JP2020194894A (ja) * | 2019-05-28 | 2020-12-03 | 株式会社ディスコ | デバイスチップの製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20070224781A1 (en) | 2007-09-27 |
JP4851214B2 (ja) | 2012-01-11 |
US7344960B2 (en) | 2008-03-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4851214B2 (ja) | パッケージ基板の分割方法 | |
JP4751634B2 (ja) | 半導体装置の製造方法 | |
JP4879012B2 (ja) | 切削ブレードの先端形状検査方法 | |
US20160086853A1 (en) | Wafer processing method | |
KR20070073583A (ko) | 플래시 메모리카드의 구조 및 패키지 방법 | |
US6609965B2 (en) | Cutting blade | |
CN108289375A (zh) | 高像素摄像头模组软硬结合板加工方法 | |
JP5709593B2 (ja) | 加工装置 | |
US11587831B2 (en) | Method for machining workpiece | |
JP6525643B2 (ja) | 製造装置及び製造方法 | |
JP6643663B2 (ja) | ダイシング装置及びダイシング方法 | |
JP5005605B2 (ja) | パッケージ基板の切削方法 | |
JP6448302B2 (ja) | パッケージ基板の研削方法 | |
JP4643464B2 (ja) | パッケージ基板の分割方法および分割装置 | |
JP2012227485A (ja) | パッケージ基板の加工方法 | |
JP2006041261A (ja) | バリ除去方法,ダイシング方法 | |
JP2018060882A (ja) | パッケージ基板の加工方法 | |
JP2020194894A (ja) | デバイスチップの製造方法 | |
JP2007005366A (ja) | 半導体装置の製造方法 | |
JP2007227726A (ja) | 集合基板加工方法 | |
JP2016082192A (ja) | パッケージ基板の分割方法 | |
JP2019021703A (ja) | 板状の被加工物の切断方法 | |
JP2018152453A (ja) | 被加工物の加工方法 | |
JP2013222835A (ja) | パッケージ基板の分割方法及び分割装置 | |
JP7190295B2 (ja) | 切削装置及びパッケージ基板の加工方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090217 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100301 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110816 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110908 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20111004 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20111020 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4851214 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20141028 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20141028 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |