CN1307724C - 使用晕圈植入而制造半导体装置的方法及系统 - Google Patents

使用晕圈植入而制造半导体装置的方法及系统 Download PDF

Info

Publication number
CN1307724C
CN1307724C CNB008127190A CN00812719A CN1307724C CN 1307724 C CN1307724 C CN 1307724C CN B008127190 A CNB008127190 A CN B008127190A CN 00812719 A CN00812719 A CN 00812719A CN 1307724 C CN1307724 C CN 1307724C
Authority
CN
China
Prior art keywords
haloing
semiconductor device
photoresist
implant
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB008127190A
Other languages
English (en)
Other versions
CN1373904A (zh
Inventor
阿哈曼德·格汉麦分米
诺伦·克瑞渥卡皮克
布莱恩·史汪森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of CN1373904A publication Critical patent/CN1373904A/zh
Application granted granted Critical
Publication of CN1307724C publication Critical patent/CN1307724C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供一种半导体层晕圈植入的方法和系统。此方法和系统包含有为半导体装置提供薄光阻层。此方法和系统亦包含有对半导体装置的适当区域提供晕圈植入。因此，在依据本发明的系统和方法中，使用能够具有较薄厚度的光阻材料，如DUV光阻。这使得可将光阻材料的厚度降低至所建议的1000A(在此领域中)或假如程序许可的话降更低。在考虑此光阻材料厚度的同时亦将其它高度变量加以考虑，可依所需仅将源极或漏极区开启。可以45度角对在目标区域的电路中的所有晶体管执行植入且仅将大量的掺杂物(多达掺杂物的3/4)植入位于沟渠边缘的晶体管边缘。因为必须通过相反种类的掺杂物定义晕圈程序，所以此方法亦可减少源极漏极的反相掺杂。在0.18μm工艺或更低的较小几何形状中，栅极的高度对降低不必要的源极/漏极区反相掺杂是真正有利且有帮助的。以此方法可将反相掺杂维持在最小值。其最终的优点为通过此薄光阻，我们可提高对较小几何形状植入的能力。

Description

使用晕圈植入而制造半导体装置的方法及系统
发明领域
本发明涉及半导体装置，尤其涉及当制造半导体装置时所使用的晕圈(halo)植入。
发明背景
晕圈植入基本上用于在半导体装置上植入掺杂物。线上光刻或真空紫外线(deep ultraviolet，即DUV)光阻基本上用于为晕圈植入程序作屏蔽。通常，为晕圈植入使用相同的掩膜(微掺杂漏极)(LDD)，因为晕圈植入通常是发生在LDD植入之后。因为光阻材料的化学性质，所以在使用传统的程序时(掩膜和光阻材料组)常发生植入阴影的问题，所以在将此制造程序应用至具较小几何形状的装置时会对此装置的产量和性能产生不利的影响。
第一个问题为植入区内光阻材料的厚度，此厚度使得以45度角所执行的植入会产生非对称及有泄漏的晶体管。第二个问题为光阻材料与装置沟渠槽氧化区相关的厚度。因此，假如将厚光阻材料(0.55μm或更大)放置在沟渠氧化区，则因为光阻材料的柔性胶状特性常常使得光阻材料会覆盖在将进行植入的区域。就算在较小范围处理技术中光阻材料是垂直站立，晕圈植入亦无法抵达目的区。除此之外，传统的程序基本并不考虑选择源极/漏极区的掺杂物的需求。
因此，所需要的是可在较小处理范围上克服上述所发现问题的系统和方法。本发明可满足此需求。
发明概述
本发明的目的为提供一种对半导体装置晕圈植入的系统和方法。此方法和系统包含有为半导体装置提供薄光阻(photoresist)对半导体装置的适当区域进行晕圈植入。
因此，在依据本发明的系统和方法中，使用能够具有较薄厚度的光阻材料，如DUV光阻。这使得可将光阻材料的厚度降低至所建议的1000A(在此领域中)或假如程序许可的话降更低。在考虑此光阻材料厚度的同时亦将其它的高度变量加以考虑，故可依所需仅将源极或漏极区开启。
可以45度角，对在目标区域的电路中的所有晶体管执行植入且仅将大量的掺杂物(多达掺杂物的3/4)植入位于沟渠边缘的晶体管边缘。因为必须通过相反种类的掺杂物定义晕圈程序，所以此方法亦可减少源极漏极的反相掺杂。
在0.18μm工艺或更低的较小几何形状中，栅极的高度对降低不必要的源极/漏极区反相掺杂是真正有利且有帮助的。以此方法可将反相掺杂维持在最小值。其最终的优点为通过此薄光阻，我们可提高对较小几何形状植入的能力。因此，依据本发明的程序可改善制造技能并且加强处理能力及装置的性能和速度。
附图简要说明
图1显示提供晕圈植入的传统程序的流程图。
图2显示在传统晕圈植入后的半导体装置。
图3显示依据本发明的系统的流程图。
图4显示在依据本发明的晕圈植入后的半导体装置。
详细说明
图1显示提供晕圈植入的传统程序的流程图。基本上在传统的程序中，首先在步骤102中设置厚光阻。然后，经由步骤104提供LDD植入。在传统程序中的厚光阻或LDD掩膜通常为高度0.55μm的光阻。在提供LDD植入之后，经由步骤106提供所谓的晕圈植入。晕圈植入通常以45度角植入栅极区下方。对以45度角植入的晶圆而言，使用没有覆盖源极或漏极区的LDD掩膜以便固定地植入所预期的区域。在PATENT ABSTRACT OF JAPAN vol.1998，No.03，27 February 1998(1998-02-27)以及EP-A-0 899 793中，公开了传统晕圈植入工艺的实例。
图2显示在传统晕圈植入后的半导体装置200。因此常常以晕圈植入202结束提供掺杂物给所有的源极区204和漏极区206。因为只希望为在栅极正下方的区域进行植入，所以在此有与其相关的泄漏和其它问题。因此，因为光阻掩膜是成45度角所以整个有源区212最初是关断的，故无法将紫外线正确地提供至栅极正下方。
如图所示，利用厚度为0.5μm的光阻掩膜212，在其所要求的45度下将使得大部分的紫外线辐射因为此角度而无法抵达所要求的区域，所以利用此厚光阻是不可行的。除此之外，假如将厚光阻(厚度为0.5μm或更大)放置在沟渠氧化物207之上时，因为光阻材料的柔性胶状特性常常使得光阻材料会跌落在沟渠氧化物上且覆盖在将进行植入的区域上。就算在小范围工艺中光阻材料是垂直站立，晕圈植入亦无法抵达目的区。
在依据本发明的方法中，其是以对选择区域进行植入而非对整个区域执行植入。通过使用厚度为0.1μm至0.2μm的较薄光阻掩膜取代在传统程序中所使用的厚度为0.55μm至0.8μm的光阻。为了更详细说明本发明，现参考下列与图式相关的讨论。
图3系显示依据本发明的系统流程图。与传统程序相同，首先通过步骤302提供厚光阻。然后，通过步骤304提供LDD植入。其后，在步骤306中将厚光阻移除。之后，在步骤308中提供薄光阻。之后，在步骤310中提供晕圈植入。通常是以45度角对在栅极区正下方执行晕圈植入。对以45度角晕圈植入的晶圆，为了对固定区域进行植入，使用LDD掩膜覆盖在源极或漏极区的部分上方。
图4显示在依据本发明的晕圈植入后的半导体装置400。如图所示，光阻掩膜402的高度较传统程序中的小(0.1μm至0.2μm)，其使得可通过光阻402分别屏蔽较多的源极和漏极区404和406。
因此，在依据本发明的方法中，使用能够具有较薄厚度的光阻材料，如DUV光阻。这使得可将光阻材料的厚度降低至所建议的1000A(在此领域中)或假如程序许可的话降更低。在考虑此光阻材料厚度的同时亦将其它的高度变量加以考虑，故可依所需仅将源极或漏极区开启。在45度角，可对在目标区域的电路中的所有晶体管执行植入且仅将大量的掺杂物(多达掺杂物的3/4)植入位于沟渠边缘的晶体管边缘。因为必须通过相反种类的掺杂物定义晕圈程序，所以此方法亦可减少源极漏极的反相掺杂。
在0.18μm工艺或更低的较小几何形状中，栅极的高度对降低不必要的源极/漏极区反相掺杂是真正有利且有帮助的。以此方法可将反相掺杂维持在最小值。其最终的优点为通过此薄光阻，我们可提高对较小几何形状植入的能力。因此，依据本发明的程序可改善制造技能并且加强处理能力及装置的性能和速度。

Claims (12)

1.一种对半导体装置(400)进行晕圈植入的方法，其特征在于该方法包含有下列步骤：
(a)(308)对该半导体装置提供薄光阻层(402)，该薄光阻层的厚度在0.1μm至0.2μm之间；和
(b)(310)对该半导体装置提供该晕圈植入，其中该薄光阻层用作该晕圈植入的掩膜。
2.如权利要求1所述的方法，其中该光阻层(402)包含有真空紫外线层。
3.如权利要求1或2所述的方法，其中该光阻层覆盖该半导体装置(400)的有源区的实际区域。
4.如权利要求3所述的方法，其中该有源区包含有该半导体装置的源极区和漏极区。
5.如权利要求3所述的方法，其中该晕圈植入以45度角进行。
6.如权利要求3所述的方法，其包含有在提供晕圈植入步骤(b)之前提供微掺杂漏极植入的步骤(304)。
7.如权利要求1或2所述的方法，其中该晕圈植入以45度角进行。
8.如权利要求7所述的方法，其包含有在提供晕圈植入步骤(b)之前提供微掺杂漏极植入的步骤(304)。
9.如权利要求4所述的方法，其中该晕圈植入以45度角进行。
10.如权利要求9所述的方法，其包含有在提供晕圈植入步骤(b)之前提供微掺杂漏极植入的步骤(304)。
11.如权利要求1或2所述的方法，其包含有在提供晕圈植入步骤(b)之前提供微掺杂漏极植入的步骤(304)。
12.如权利要求4所述的方法，其包含有在提供晕圈植入步骤(b)之前提供微掺杂漏极植入的步骤(304)。
CNB008127190A 1999-11-29 2000-06-23 使用晕圈植入而制造半导体装置的方法及系统 Expired - Lifetime CN1307724C (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US16815599P 1999-11-29 1999-11-29
US60/168,155 1999-11-29
US09/497,320 US7192836B1 (en) 1999-11-29 2000-02-03 Method and system for providing halo implant to a semiconductor device with minimal impact to the junction capacitance
US09/497,320 2000-02-03
PCT/US2000/017271 WO2001039273A1 (en) 1999-11-29 2000-06-23 Method of manufacturing a semiconductor device using a halo implantation

Publications (2)

Publication Number Publication Date
CN1373904A CN1373904A (zh) 2002-10-09
CN1307724C true CN1307724C (zh) 2007-03-28

Family

ID=26863843

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB008127190A Expired - Lifetime CN1307724C (zh) 1999-11-29 2000-06-23 使用晕圈植入而制造半导体装置的方法及系统

Country Status (7)

Country Link
US (1) US7192836B1 (zh)
EP (1) EP1234335B1 (zh)
JP (1) JP2003515931A (zh)
KR (1) KR100647884B1 (zh)
CN (1) CN1307724C (zh)
DE (1) DE60031881T2 (zh)
WO (1) WO2001039273A1 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6462371B1 (en) * 1998-11-24 2002-10-08 Micron Technology Inc. Films doped with carbon for use in integrated circuit technology
US6677646B2 (en) 2002-04-05 2004-01-13 International Business Machines Corporation Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS
KR100531105B1 (ko) * 2003-07-23 2005-11-28 동부아남반도체 주식회사 반도체 소자 제조방법
US8216903B2 (en) * 2005-09-29 2012-07-10 Texas Instruments Incorporated SRAM cell with asymmetrical pass gate
KR100752173B1 (ko) * 2005-12-29 2007-08-24 동부일렉트로닉스 주식회사 반도체 소자의 포켓 이온 주입 감광막 패턴 및 그 형성방법
KR101416316B1 (ko) 2007-12-12 2014-07-08 삼성전자주식회사 국부적인 할로 이온 영역을 포함하는 전계 효과트랜지스터, 이를 포함하는 반도체 메모리, 메모리 카드 및시스템
US8822293B2 (en) * 2008-03-13 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned halo/pocket implantation for reducing leakage and source/drain resistance in MOS devices
US8877596B2 (en) 2010-06-24 2014-11-04 International Business Machines Corporation Semiconductor devices with asymmetric halo implantation and method of manufacture
KR200454335Y1 (ko) * 2011-01-21 2011-06-29 임석우 조명장치를 갖춘 모자
KR101647324B1 (ko) * 2011-09-30 2016-08-10 인텔 코포레이션 비평면 트랜지스터 핀 제조
CN103337482A (zh) * 2013-06-17 2013-10-02 上海集成电路研发中心有限公司 可调节阈值电压的静态随机存储器晶体管单元制造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5837587A (en) * 1991-09-30 1998-11-17 Sgs-Thomson Microelectronics, Inc. Method of forming an integrated circuit device

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62163374A (ja) 1986-01-14 1987-07-20 Toshiba Corp 半導体装置の製造方法
JPS63312678A (ja) * 1987-06-16 1988-12-21 Sanyo Electric Co Ltd Ｍｏｓ半導体装置の製造方法
US5045486A (en) * 1990-06-26 1991-09-03 At&T Bell Laboratories Transistor fabrication method
US5320974A (en) * 1991-07-25 1994-06-14 Matsushita Electric Industrial Co., Ltd. Method for making semiconductor transistor device by implanting punch through stoppers
JPH05198804A (ja) * 1991-07-25 1993-08-06 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JPH06196492A (ja) * 1992-12-24 1994-07-15 Nippon Steel Corp 半導体装置及びその製造方法
JP3246094B2 (ja) * 1993-06-11 2002-01-15 ソニー株式会社 トランジスタの製造方法
US5378659A (en) 1993-07-06 1995-01-03 Motorola Inc. Method and structure for forming an integrated circuit pattern on a semiconductor substrate
KR970004074A (ko) * 1995-06-05 1997-01-29 빈센트 비. 인그라시아 절연 게이트 전계 효과 트랜지스터 및 그 제조 방법
US5675166A (en) * 1995-07-07 1997-10-07 Motorola, Inc. FET with stable threshold voltage and method of manufacturing the same
AU7257496A (en) * 1995-10-04 1997-04-28 Intel Corporation Formation of source/drain from doped glass
US5595919A (en) * 1996-02-20 1997-01-21 Chartered Semiconductor Manufacturing Pte Ltd. Method of making self-aligned halo process for reducing junction capacitance
JPH09289315A (ja) * 1996-04-22 1997-11-04 Sony Corp 半導体装置の製造方法
JPH09304945A (ja) * 1996-05-10 1997-11-28 Hitachi Ltd パターン形成方法
US6020244A (en) * 1996-12-30 2000-02-01 Intel Corporation Channel dopant implantation with automatic compensation for variations in critical dimension
US5899719A (en) 1997-02-14 1999-05-04 United Semiconductor Corporation Sub-micron MOSFET
US6083794A (en) * 1997-07-10 2000-07-04 International Business Machines Corporation Method to perform selective drain engineering with a non-critical mask
US6037107A (en) * 1997-08-28 2000-03-14 Shipley Company, L.L.C. Photoresist compositions
EP0899793A3 (en) * 1997-08-28 1999-11-17 Texas Instruments Incorporated Transistor having localized source and drain extensions and method
US5976937A (en) * 1997-08-28 1999-11-02 Texas Instruments Incorporated Transistor having ultrashallow source and drain junctions with reduced gate overlap and method
US6008094A (en) * 1997-12-05 1999-12-28 Advanced Micro Devices Optimization of logic gates with criss-cross implants to form asymmetric channel regions
US5970353A (en) * 1998-03-30 1999-10-19 Advanced Micro Devices, Inc. Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion
US6051458A (en) * 1998-05-04 2000-04-18 Taiwan Semiconductor Manufacturing Company Drain and source engineering for ESD-protection transistors
JP2000068509A (ja) * 1998-08-26 2000-03-03 Sony Corp 半導体装置の製造方法
US6171913B1 (en) * 1998-09-08 2001-01-09 Taiwan Semiconductor Manufacturing Company Process for manufacturing a single asymmetric pocket implant
US6114211A (en) * 1998-11-18 2000-09-05 Advanced Micro Devices, Inc. Semiconductor device with vertical halo region and methods of manufacture
US6320236B1 (en) * 1999-10-06 2001-11-20 Advanced Micro Devices, Inc. Optimization of logic gates with criss-cross implants to form asymmetric channel regions

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5837587A (en) * 1991-09-30 1998-11-17 Sgs-Thomson Microelectronics, Inc. Method of forming an integrated circuit device

Also Published As

Publication number Publication date
KR20020060980A (ko) 2002-07-19
EP1234335B1 (en) 2006-11-15
DE60031881D1 (de) 2006-12-28
EP1234335A1 (en) 2002-08-28
WO2001039273A1 (en) 2001-05-31
US7192836B1 (en) 2007-03-20
DE60031881T2 (de) 2007-07-05
JP2003515931A (ja) 2003-05-07
KR100647884B1 (ko) 2006-11-23
CN1373904A (zh) 2002-10-09

Similar Documents

Publication Publication Date Title
CN1307724C (zh) 使用晕圈植入而制造半导体装置的方法及系统
US5770502A (en) Method of forming a junction in a flash EEPROM cell by tilt angle implanting
JPH04359477A (ja) Ｎチャネル単一ポリシリコンレベルｅｐｒｏｍセルを得るプロセスおよびそのプロセスによって得たセル
EP0201111A2 (en) Semiconductor device manufacture using an implantation step
US6171914B1 (en) Synchronized implant process to simplify NLDD/PLDD stage and N+/P+stage into one implant
CN101211855B (zh) 适用于有源区只读存储器的浅掺杂漏极版图逻辑运算方法
US6913872B1 (en) Dual-wavelength exposure for reduction of implant shadowing
US5411899A (en) Transistor fabrication of a twin tub using angled implant
JPH0391262A (ja) 半導体装置の製造方法
US20020102785A1 (en) Method for forming shallow junctions by increasing width of photoresist and using implanting through poly film
US6077746A (en) Using p-type halo implant as ROM cell isolation in flat-cell mask ROM process
US6569606B1 (en) Method of reducing photoresist shadowing during angled implants
US6127222A (en) Non-self-aligned side channel implants for flash memory cells
EP0851478B1 (en) Method of forming oxide isolation regions
JPH08227936A (ja) 半導体装置及びその製造方法
KR100280814B1 (ko) 플래쉬 이이피롬의 공통 소오스 라인 형성 방법
JPS60253217A (ja) 半導体装置の製造方法
KR100358571B1 (ko) 반도체소자의 제조방법
KR890005197B1 (ko) 씨모오스 반도체장치의 제조방법
US20040142519A1 (en) Methods of manufacturing a semiconductor device
KR100495090B1 (ko) Eeprom의 터널영역 축소방법
JPH0424963A (ja) マスクｒｏｍの製造方法
JPH01220471A (ja) 半導体装置の製造方法
EP0800207A1 (en) Semiconductor devices
JPH07235610A (ja) Ｃｍｏｓ型半導体装置の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: GLOBALFOUNDRIES

Free format text: FORMER OWNER: ADVANCED MICRO DEVICES INC.

Effective date: 20100702

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: CALIFORNIA, THE UNITED STATES TO: CAYMAN ISLANDS, BRITISH

TR01 Transfer of patent right

Effective date of registration: 20100702

Address after: Grand Cayman, Cayman Islands

Patentee after: Globalfoundries Semiconductor Inc.

Address before: American California

Patentee before: Advanced Micro Devices Inc.

CX01 Expiry of patent term

Granted publication date: 20070328

CX01 Expiry of patent term