DE60031881D1 - Verfahren zur herstellung einer halbleiterbauelement mittels einer halo-implantierung - Google Patents
Verfahren zur herstellung einer halbleiterbauelement mittels einer halo-implantierungInfo
- Publication number
- DE60031881D1 DE60031881D1 DE60031881T DE60031881T DE60031881D1 DE 60031881 D1 DE60031881 D1 DE 60031881D1 DE 60031881 T DE60031881 T DE 60031881T DE 60031881 T DE60031881 T DE 60031881T DE 60031881 D1 DE60031881 D1 DE 60031881D1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- semiconductor component
- halo implantation
- halo
- implantation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000002513 implantation Methods 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- High Energy & Nuclear Physics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16815599P | 1999-11-29 | 1999-11-29 | |
US168155P | 1999-11-29 | ||
US497320 | 2000-02-03 | ||
US09/497,320 US7192836B1 (en) | 1999-11-29 | 2000-02-03 | Method and system for providing halo implant to a semiconductor device with minimal impact to the junction capacitance |
PCT/US2000/017271 WO2001039273A1 (en) | 1999-11-29 | 2000-06-23 | Method of manufacturing a semiconductor device using a halo implantation |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60031881D1 true DE60031881D1 (de) | 2006-12-28 |
DE60031881T2 DE60031881T2 (de) | 2007-07-05 |
Family
ID=26863843
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60031881T Expired - Lifetime DE60031881T2 (de) | 1999-11-29 | 2000-06-23 | Verfahren zur herstellung einer halbleiterbauelement mittels einer halo-implantierung |
Country Status (7)
Country | Link |
---|---|
US (1) | US7192836B1 (de) |
EP (1) | EP1234335B1 (de) |
JP (1) | JP2003515931A (de) |
KR (1) | KR100647884B1 (de) |
CN (1) | CN1307724C (de) |
DE (1) | DE60031881T2 (de) |
WO (1) | WO2001039273A1 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6462371B1 (en) * | 1998-11-24 | 2002-10-08 | Micron Technology Inc. | Films doped with carbon for use in integrated circuit technology |
US6677646B2 (en) | 2002-04-05 | 2004-01-13 | International Business Machines Corporation | Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS |
KR100531105B1 (ko) * | 2003-07-23 | 2005-11-28 | 동부아남반도체 주식회사 | 반도체 소자 제조방법 |
US8216903B2 (en) * | 2005-09-29 | 2012-07-10 | Texas Instruments Incorporated | SRAM cell with asymmetrical pass gate |
KR100752173B1 (ko) * | 2005-12-29 | 2007-08-24 | 동부일렉트로닉스 주식회사 | 반도체 소자의 포켓 이온 주입 감광막 패턴 및 그 형성방법 |
KR101416316B1 (ko) | 2007-12-12 | 2014-07-08 | 삼성전자주식회사 | 국부적인 할로 이온 영역을 포함하는 전계 효과트랜지스터, 이를 포함하는 반도체 메모리, 메모리 카드 및시스템 |
US8822293B2 (en) * | 2008-03-13 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned halo/pocket implantation for reducing leakage and source/drain resistance in MOS devices |
US8877596B2 (en) | 2010-06-24 | 2014-11-04 | International Business Machines Corporation | Semiconductor devices with asymmetric halo implantation and method of manufacture |
KR200454335Y1 (ko) * | 2011-01-21 | 2011-06-29 | 임석우 | 조명장치를 갖춘 모자 |
KR101647324B1 (ko) * | 2011-09-30 | 2016-08-10 | 인텔 코포레이션 | 비평면 트랜지스터 핀 제조 |
CN103337482A (zh) * | 2013-06-17 | 2013-10-02 | 上海集成电路研发中心有限公司 | 可调节阈值电压的静态随机存储器晶体管单元制造方法 |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62163374A (ja) | 1986-01-14 | 1987-07-20 | Toshiba Corp | 半導体装置の製造方法 |
JPS63312678A (ja) * | 1987-06-16 | 1988-12-21 | Sanyo Electric Co Ltd | Mos半導体装置の製造方法 |
US5045486A (en) * | 1990-06-26 | 1991-09-03 | At&T Bell Laboratories | Transistor fabrication method |
US5320974A (en) * | 1991-07-25 | 1994-06-14 | Matsushita Electric Industrial Co., Ltd. | Method for making semiconductor transistor device by implanting punch through stoppers |
JPH05198804A (ja) * | 1991-07-25 | 1993-08-06 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US5894158A (en) | 1991-09-30 | 1999-04-13 | Stmicroelectronics, Inc. | Having halo regions integrated circuit device structure |
JPH06196492A (ja) * | 1992-12-24 | 1994-07-15 | Nippon Steel Corp | 半導体装置及びその製造方法 |
JP3246094B2 (ja) * | 1993-06-11 | 2002-01-15 | ソニー株式会社 | トランジスタの製造方法 |
US5378659A (en) | 1993-07-06 | 1995-01-03 | Motorola Inc. | Method and structure for forming an integrated circuit pattern on a semiconductor substrate |
KR970004074A (ko) * | 1995-06-05 | 1997-01-29 | 빈센트 비. 인그라시아 | 절연 게이트 전계 효과 트랜지스터 및 그 제조 방법 |
US5675166A (en) * | 1995-07-07 | 1997-10-07 | Motorola, Inc. | FET with stable threshold voltage and method of manufacturing the same |
KR19990064285A (ko) * | 1995-10-04 | 1999-07-26 | 피터 엔. 데트킨 | 도핑된 글라스로부터의 소스/드레인의 형성 |
US5595919A (en) * | 1996-02-20 | 1997-01-21 | Chartered Semiconductor Manufacturing Pte Ltd. | Method of making self-aligned halo process for reducing junction capacitance |
JPH09289315A (ja) * | 1996-04-22 | 1997-11-04 | Sony Corp | 半導体装置の製造方法 |
JPH09304945A (ja) * | 1996-05-10 | 1997-11-28 | Hitachi Ltd | パターン形成方法 |
US6020244A (en) * | 1996-12-30 | 2000-02-01 | Intel Corporation | Channel dopant implantation with automatic compensation for variations in critical dimension |
US5899719A (en) | 1997-02-14 | 1999-05-04 | United Semiconductor Corporation | Sub-micron MOSFET |
US6083794A (en) * | 1997-07-10 | 2000-07-04 | International Business Machines Corporation | Method to perform selective drain engineering with a non-critical mask |
US6037107A (en) * | 1997-08-28 | 2000-03-14 | Shipley Company, L.L.C. | Photoresist compositions |
EP0899793A3 (de) | 1997-08-28 | 1999-11-17 | Texas Instruments Incorporated | Transistor mit lokalisierten Source- und Drain-Ausdehnungen und Verfahren |
US5976937A (en) * | 1997-08-28 | 1999-11-02 | Texas Instruments Incorporated | Transistor having ultrashallow source and drain junctions with reduced gate overlap and method |
US6008094A (en) * | 1997-12-05 | 1999-12-28 | Advanced Micro Devices | Optimization of logic gates with criss-cross implants to form asymmetric channel regions |
US5970353A (en) * | 1998-03-30 | 1999-10-19 | Advanced Micro Devices, Inc. | Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion |
US6051458A (en) * | 1998-05-04 | 2000-04-18 | Taiwan Semiconductor Manufacturing Company | Drain and source engineering for ESD-protection transistors |
JP2000068509A (ja) * | 1998-08-26 | 2000-03-03 | Sony Corp | 半導体装置の製造方法 |
US6171913B1 (en) * | 1998-09-08 | 2001-01-09 | Taiwan Semiconductor Manufacturing Company | Process for manufacturing a single asymmetric pocket implant |
US6114211A (en) * | 1998-11-18 | 2000-09-05 | Advanced Micro Devices, Inc. | Semiconductor device with vertical halo region and methods of manufacture |
US6320236B1 (en) * | 1999-10-06 | 2001-11-20 | Advanced Micro Devices, Inc. | Optimization of logic gates with criss-cross implants to form asymmetric channel regions |
-
2000
- 2000-02-03 US US09/497,320 patent/US7192836B1/en not_active Expired - Fee Related
- 2000-06-23 CN CNB008127190A patent/CN1307724C/zh not_active Expired - Lifetime
- 2000-06-23 JP JP2001540842A patent/JP2003515931A/ja active Pending
- 2000-06-23 DE DE60031881T patent/DE60031881T2/de not_active Expired - Lifetime
- 2000-06-23 WO PCT/US2000/017271 patent/WO2001039273A1/en active IP Right Grant
- 2000-06-23 KR KR1020027006835A patent/KR100647884B1/ko not_active IP Right Cessation
- 2000-06-23 EP EP00944804A patent/EP1234335B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
CN1373904A (zh) | 2002-10-09 |
EP1234335A1 (de) | 2002-08-28 |
JP2003515931A (ja) | 2003-05-07 |
KR100647884B1 (ko) | 2006-11-23 |
KR20020060980A (ko) | 2002-07-19 |
EP1234335B1 (de) | 2006-11-15 |
US7192836B1 (en) | 2007-03-20 |
DE60031881T2 (de) | 2007-07-05 |
WO2001039273A1 (en) | 2001-05-31 |
CN1307724C (zh) | 2007-03-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: GLOBALFOUNDRIES INC., GRAND CAYMAN, KY |
|
8328 | Change in the person/name/address of the agent |
Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER, |