CN1231770A - 高压半导体元件 - Google Patents

高压半导体元件 Download PDF

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CN1231770A
CN1231770A CN97198189A CN97198189A CN1231770A CN 1231770 A CN1231770 A CN 1231770A CN 97198189 A CN97198189 A CN 97198189A CN 97198189 A CN97198189 A CN 97198189A CN 1231770 A CN1231770 A CN 1231770A
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A·瑟德贝尔格
P·斯维德贝尔格
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Infineon Technologies AG
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Abstract

本发明公开了一种具有扩展漂移区的高频MOS晶体管结构,它能调制MOS晶体管漂移区中的电阻。用额外的半导体层在薄栅氧化层上形成第二MOS结构来得到扩展栅层。由此电场均匀地横向分布在扩展漂移区中。用这种设计可以制造短沟道长度、有低掺杂浓度的扩展漂移区、还有非常低的导通电阻以及高击穿电压的MOS晶体管。

Description

高压半导体元件
本发明涉及MOS晶体管的改进，具体涉及漂移区具有电阻调制的扩展漂移区的MOS晶体管。
很早就知道，MOS型场效应晶体管可以有效地用作开关元件。这种晶体管应该具有低的导通电阻和低的截止电容。但是，常规MOS晶体管中栅氧化物和沟道区之间的低击穿电压限制了这种设计的晶体管的最大可能工作电压。
在沟道区与栅氧化物区域外引入扩展漂移区，可以降低栅氧化物上的垂直电场。由此可以增加元件的击穿电压。但是为了避免扩展漂移区中的雪崩击穿，该区必须具有低的掺杂浓度，以增加元件的总导通电阻。
已经提出了各种技术来改善横向解决方案。一种技术通称为RESURF，即降低表面电场。在图1中例示了有扩展漂移区的DMOS结构，是用RESURF技术设计的。想法主要是从下面耗尽n型掺杂漂移区，而尽量少地从主体与漂移区之间的pn结来耗尽它。该技术的详细信息可参照J.A.Appels等的“薄层高压器件”、Philips J.Res.,35卷，1-13页，1980年。根据Apples等，可以用3-15微米的相对薄外延层的技术来制备集电极-发射极电压高达1000伏的高压晶体管。
该主题的其他背景可以在其他文章中发现，例如J.G.Mena和C.A.T.Salama在1986年29卷6期的<固态电子学>中第647-656页的“高压多电阻漂移区LDMOS”；A.Soderbarg等在1995年IEEE-IEDM-95会议文集975-978页的文章“新型高压GHz DMOS晶体管与标准CMOS工艺的集成”。其中在不引入雪崩击穿的情况下，可以在扩展漂移区中使用较高的掺杂水平。但是在有些开关应用中，这些及其类似的方案具有过高的导通电阻。
在1992年授予P.Svedberg的专利号为89037618的瑞士专利“互补沟道晶体管”、以及S.Tiensuu等在1994年的<24次欧洲固体器件研究会议(ESSDERC 94)>会议文集225页的“多晶体管-大功率MOS型开关”中，都说明了长沟道器件。在该器件中，用有互补沟道区的第二硅层代替栅材料，如图2所示，该图例示了该互补沟道晶体管的剖面。图2的结构如下：在绝缘衬底1上，形成具有n+掺杂源极2、p掺杂沟道3和n+掺杂漏极4的第一场效应晶体管。在第一NMOS FET上，使用绝缘氧化硅层5。在层5上另外形成有p+掺杂源极11、n掺杂沟道12和p+掺杂漏极13的第二场效应晶体管。这样第二场效应晶体管构成PMOSFET。如图2所示，下面的NMOS晶体管的沟道比上面的PMOS晶体管的沟道稍长。沟道的宽度取决于器件所需的电流处理能力。如果两掺杂剂间平衡，则上下结构层中的两低掺杂区彼此耗尽。沟道对必须足够长以承受截止时源漏之间的电场。
由于两沟道区的互相串扰，可以在不采用扩展漂移区的情况下，让器件在导通状态时象常规MOS器件一样工作，而在截止时有效分布高压。不再需要用低掺杂漂移区来增加器件的导通电阻。而且如果合适地平衡两个沟道区之间的掺杂，便可以非常好地分布源漏之间的电场。总之，使用这种互补沟道晶体管技术，可以在更小的芯片面积上设计有非常低的导通电阻和高击穿电压的元件。使用这种元件设计的缺点是：它不能由短沟道实现，限制了高频特性。而且元件需要两个分离的栅控制器，一个给低电压端，一个给高电压端，使得开关控制变得更复杂。
另一个降低导通电阻的普通技术是用少数载流子调制漂移区，如各种IGBT(绝缘栅双极晶体管)方案，也可参考D.R.Disney的“绝缘体上的硅衬底中的横向功率器件的物理与技术”，ICL93-020，斯坦福大学集成电路实验室，1993年6月。但是这种调制技术导致了非线性导通电阻，且有很差的频率特性。
因此，当晶体管用于需要高压和低导通电阻的高频应用时，还需要改进MOS晶体管的设计。
本发明提供了一种横向MOS晶体管，特别适于高频使用，由于使用了扩展漂移区，可以控制栅电流且可以使用常规沟道控制电压，通过在漂移区上使用额外半导体层或扩展栅，扩展漂移区能调制漂移区的电阻。因而有可能设计短沟道长度、有低掺杂浓度的扩展漂移区、且仍有非常低的导通电阻和高击穿电压的MOS晶体管。根据本发明的晶体管可以是n型也可以是p型DMOS器件。
本发明的范围如独立权利要求1和10所述，而本发明的不同实施例如从属权利要求2-9和11-19所述。
参照附图和下面说明将很好地理解本发明、及其其他目的和优点，其中：
图1例示了用RESURF技术设计的具有扩展漂移区的已有技术DMOS的剖面；
图2表示已有技术中互补沟道晶体管的剖面；
图3表示根据本发明第一实施例在体硅材料中设计的晶体管的剖面；
图4表示根据本发明第二实施例用SOI技术设计的晶体管的剖面；
图5表示根据本发明第三实施例在体硅材料中设计的晶体管的剖面；
图6表示根据本发明第四实施例设计的晶体管的剖面；
图3表示本发明一实施例的剖面。在p-掺杂的衬底20上形成n-掺杂层21作为沟道。在层21上形成p掺杂体22和n+掺杂漏区23。然后在p掺杂体内形成n+掺杂源区24和另外的p+掺杂区25。源区24和25以及漏区23按标准方式提供有将器件连接到电子电路的接触(未示出)。在作为沟道的层21的上部，加一薄绝缘层26，如氧化硅，该层将作为栅绝缘层。在构成漂移区的该结构上再加一层硅或多晶硅，形成扩展栅层30。扩展栅层有类似的结构，但是与所述漂移区有相反的掺杂类型，且包含p-沟道31、n+漏区32和p+源区33以及另外的n+掺杂区34。区域31、32、33、34和25将另外按常规方法提供所需的接触(未示出)，以将该器件连接到电子电路。
可以用标准CMOS技术设计和制备沟道和栅区。可以用相反掺杂类型的硅或多晶硅层来调制漂移区。可以用和栅材料相同的层。为了横向均匀地分布高压，上层的高压端必须连接到漏。为了避免在晶体管处于导通时(当栅压高于漏压时)上层栅的高栅漏电流，可以通过集成二极管40来实现上层和漏接触之间的连接，如图3所示。
在导通状态，栅电压高于源和漏的电压。沟道电阻按普通MOS器件的相同方式来调制。由于扩展漂移区上的层的较高电势，多数载流子将聚集在硅表面附近。多数载流子的聚集急剧降低漂移区的电阻。由此电阻调制为多数载流子型，这将没有IGBT中的高频和非线性问题。漏端的反偏二极管降低了栅漏电流。
在截止状态，沟道区按普通MOS器件中相同的方式截止。扩展漂移区上的层上的电势一直等于或小于下面硅层的电势。因此，扩展漂移区可以垂直耗尽，象在已知RESURF技术(见J.A.Appels等)中一样。然后电场将均匀地横向分布在扩展漂移区中。由于该硅层也从漂移区下面耗尽，所以降低了上层的漏电流。所示的实施例公开了一种n型DMOS器件，但是通过改变掺杂极性，可以容易相应地实现p型DMOS器件，如图5所示。在例示实施例中，为了在某一种程度上简化用来说明本发明的附图，图中不包括本领域技术人员公知的钝化层，如氧化层和氮化层。
如图3和图4所示的n型DMOS器件，本发明的器件可以在体硅材料和SOI材料上实现。同样图5例示的p型DMOS有对应于图4的n型SOI DMOS对应形状。在这种情况下，沟道电阻按普通PMOS器件相同的方式来调制，即由少数载流子调制。在另一实施例中，图3中，在体20和n-掺杂层21之间使用如二氧化硅等绝缘层来实现体材料型和SOI型器件的复合，对应于图5所示的p型DMOS。图6是和图3类似的本发明的再一个实施例。栅结构的不同在于：栅的n+部分与扩展栅层分离，同时，与图3的结构相比，扩展栅层下面的绝缘层较厚。
可以用标准MOS或DMOS工艺流程来制备本发明的器件，漂移区上的第二半导体层可以和栅多晶硅层或第二多晶硅层集成在一起。也可以用晶片键合或者淀积另外一种半导体材料来附加该第二层。可以在淀积栅材料之前通过加到衬底中的掺杂剂来限定沟道区，如区域22，或也可以通过掺杂剂从栅层边沿的横向扩散来限定。
本领域的技术人员应该明白，在不偏离所附权利要求书中所限定的本发明的精神和范围的情况下，根据本发明思想的器件可以有很多变型和改变。

Claims (18)

1．一种形成高压MOS晶体管结构的器件，包括具有n-掺杂半导体层(21)的衬底(20,50)，n-半导体层(21)有第一n+掺杂漏区(23)和p掺杂体(22)，p掺杂体(22)包含形成源区的第二n+掺杂区(24)和第一p+掺杂区(25)，所说n-掺杂部分在所说源与漏区之间构成漂移沟道，其中在所说漂移沟道顶部有绝缘栅氧化层(26)，其上有半导体层与绝缘栅氧化层一起形成扩展栅层，由此二极管(40)接在所说漏区与所说扩展栅层中的第三n+掺杂区(32)之间。
2．如权利要求1的器件，其特征为：所说扩展栅层还包括p-掺杂区(31)、第二p+掺杂区(33)、和第四n+掺杂区(34)，它们在所说绝缘栅氧化物上形成MOS结构。
3．如权利要求1的器件，其特征为：所说衬底(20)为p-掺杂的半导体。
4．如权利要求1的器件，其特征为：所说衬底(50)为由兰宝石等形成的绝缘体。
5．如权利要求1的器件，其特征为：形成掩埋SOI层的二氧化硅层将所说n-掺杂半导体层(21)与下面的衬底隔开。
6．如权利要求1的器件，其特征为：所说二极管(40)是合适的外部半导体二极管，其接在所说n-掺杂半导体层中的所说第一n+掺杂区(23)与所说扩展栅层中的所说第三n+掺杂区(32)之间。
7．如权利要求1的器件，其特征为：所说二极管(40)是集成在所说n-掺杂半导体层中的所说第一n+掺杂区(23)与所说扩展栅层之间的半导体二极管，由此所说第三n+掺杂区(32)可以是集成二极管的一部分。
8．如权利要求1的器件，其特征为：形成源区的所说第二n+掺杂区(24)和所说第一p+掺杂区(25)具有分别的接触焊盘。
9．如权利要求1的器件，其特征为：形成所说扩展栅层的源区的所说第二p+掺杂区(33)和所说第四n+掺杂区(34)具有分别的接触焊盘。
10．一种形成高压MOS晶体管结构的器件，包括具有p-掺杂半导体层的衬底，p-掺杂半导体层有第一p+掺杂漏区和n掺杂体，n掺杂体包含形成源区的第二p+掺杂区和第一n+掺杂区，所说p-掺杂部分在所说源与漏区之间构成漂移沟道，其中在所说漂移沟道顶部有绝缘栅氧化层，其上有半导体层与绝缘栅氧化层一起形成扩展栅层，由此二极管接在所说漏区与所说扩展栅层中的第三p+掺杂区之间。
11．如权利要求10的器件，其特征为：所说扩展栅层还包括n-掺杂区、第二n+掺杂区、和第四p+掺杂区，它们在所说绝缘栅氧化物上形成MOS结构。
12．如权利要求10的器件，其特征为：所说衬底为n-掺杂的半导体。
13．如权利要求10的器件，其特征为：所说衬底为由兰宝石等形成的绝缘体。
14．如权利要求10的器件，其特征为：形成掩埋SOI层的二氧化硅层将所说p-掺杂半导体层与下面的衬底隔开。
15．如权利要求10的器件，其特征为：所说二极管是合适的外部半导体二极管，其接在所说p-掺杂半导体层中的所说第一p+掺杂区与所说扩展栅层中的所说第三p+掺杂区之间。
16．如权利要求10的器件，其特征为：所说二极管是集成在所说p-掺杂半导体层中的所说第一p+掺杂区与所说扩展栅层之间的半导体二极管，由此所说第三p+掺杂区可以是集成二极管的一部分。
17．如权利要求10的器件，其特征为：形成源区的所说第二p+掺杂区和所说第一n+掺杂区具有分别的接触焊盘。
18．如权利要求10的器件，其特征为：形成所说扩展栅层的源区的所说第二n+掺杂区和所说第四p+掺杂区具有分别的接触焊盘。
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