WO2009133485A1

WO2009133485A1 - A field effect transistor and a method of manufacturing the same

Info

Publication number: WO2009133485A1
Application number: PCT/IB2009/051414
Authority: WO
Inventors: Anco Heringa; Jan Sonsy
Original assignee: Nxp B.V.
Priority date: 2008-04-30
Filing date: 2009-04-03
Publication date: 2009-11-05

Abstract

A field effect transistor (700), the field effect transistor (700) comprising a substrate (702), a well structure comprising a well region (704) formed in a first surface portion of the substrate (702) and a well extension (706) formed in a second surface portion of the substrate (702) adjacent the first surface portion, a gate structure comprising a gate region (708) formed over the first surface portion of the substrate (702) and a gate extension (710) formed over the second surface portion of the substrate (702), and a gate insulating structure (712) for ohmically decoupling the gate structure from the well structure and having a uniform thickness (d) along the gate structure, wherein the gate structure has a spatially varying doping profile.

Description

A field effect transistor and a method of manufacturing the same

FIELD OF THE INVENTION The invention relates to a field effect transistor.

Moreover, the invention relates to a method of manufacturing a field effect transistor.

BACKGROUND OF THE INVENTION In semiconductor technology, the efficient manufacture of field effect transistors is essential. For modern applications, the demands on the quality and on the performance of transistors increases.

US 2006/0001050 discloses a FET device for operation at high voltages which includes a substrate, a first well and a second well within the substrate that are doped with implants of a first type and second type, respectively. The first and second wells define a pn- junction. A field oxide layer within the second well defines a first surface region to receive a drain contact. A third well is located at least partially in the first well, includes doped implants of the second type, and is adapted to receive a source contact. As such, the third well defines a channel between itself and the second well within the first well. A gate is disposed over the channel. At least a first portion of the gate is disposed over the pn-junction, and includes doped implants of the first type. A number of permutations are allowed for doping the remainder of the gate.

However, conventional transistor manufacture procedures may lack sufficient performance when the dimensions become smaller and smaller.

OBJECT AND SUMMARY OF THE INVENTION

It is an object of the invention to provide a transistor architecture which is appropriate for small dimensions.

In order to achieve the object defined above, a field effect transistor, and a method of manufacturing a field effect transistor according to the independent claims are provided.

According to an exemplary embodiment of the invention, a field effect transistor (for instance an extended drain field effect transistor) is provided, the field effect transistor comprising a substrate (for instance a semiconductor substrate), a well structure comprising a well region formed in a first surface portion of the substrate and a well extension formed in a second surface portion of the substrate adjacent the first surface portion, a gate structure (particularly a gate structure made of a semiconductor material such as silicon) comprising a gate region formed (for instance exclusively) over (or above) the first surface portion of the substrate and a gate extension formed (for instance exclusively) over (or above) the second surface portion of the substrate, and a gate insulating structure (particularly arranged or vertically sandwiched between the gate structure and the well structure) for ohmically decoupling the gate structure from the well structure (that is for preventing a direct flow of charge carriers from the gate structure to the well structure, or vice versa) and having a uniform (for instance constant) thickness (particularly a uniform vertical thickness in a direction perpendicular to a main surface of the substrate) along the (for instance entire) gate structure, wherein the gate structure has a spatially varying (for instance in a direction along which the gate region and the gate extension are aligned next to one another) doping profile (for instance a stepwise or gradually varying doping profile), particularly having a spatially varying doping profile along a direction which is parallel to a surface plane of the substrate. The well region may differ from the well extension by a different type of dopant implanted in the well region and in the well extension. The gate region may differ from the gate extension by a different kind of doping profile.

According to another exemplary embodiment of the invention, a method of manufacturing a field effect transistor is provided, the method comprising forming a well structure comprising a well region in a first surface portion of a substrate and a well extension in a second surface portion of the substrate adjacent the first surface portion, forming a gate structure comprising a gate region over the first surface portion of the substrate and a gate extension over the second surface portion of the substrate, and forming a gate insulating structure for ohmically decoupling the gate structure from the well structure and having a uniform thickness along the gate structure, wherein the gate structure is formed to have a spatially varying doping profile.

The term "field effect transistor" (FET) may denote a transistor in which an output current (source-drain current) may be controlled by the voltage applied to a gate which can be an MOS structure (MOSFET). Such a field effect transistor may be part of a monolithically integrated circuit and may provide a function such as a memory function, a logic function, a switch function and/or an amplifier function.

The term "substrate" may denote any suitable material, such as a semiconductor, glass, plastic, etc. According to an exemplary embodiment, the term "substrate" may be used to define generally the elements for layers that underlie and/or overlie a layer or portions of interest. Also, the substrate may be any other base on which a layer is formed, for example a semiconductor wafer such as a silicon wafer or silicon chip.

The term "well structure" may particularly denote a doped surface portion of a substrate.

The term "source" may particularly denote a heavily doped region from which majority carriers are flowing into the channel.

The term "drain" may particularly denote a heavily doped region in semiconductor substrates located at the end of the channel in field effect transistors, wherein carriers are flowing out of the transistor through the drain.

Although the description of this application distinguishes sometimes between a "source" and a "drain", these components may also be denoted as first and second source/drain regions.

The term "gate structure" may denote an electrically conductive structure to which an electric voltage may be applied to control a conductivity of a channel region of a semiconductor substrate/well.

The term "gate insulating structure" may denote an electrically insulating structure which prevents a direct ohmic connection between gate and channel, thereby contributing to the field effect. For instance, the gate insulating structure may be a layer of silicon oxide having a homogeneous thickness.

The term "extended drain transistor" (EDMOS) may particularly denote a transistor having a drain extension between a channel region and a drain region. By means of such an extension, the drain may be shifted to a remote location and may also withstand a higher voltage The term "spatially varying doping profile" may particularly denote that a dopant type of conductivity (for example n-doped or p-doped), a dopant material (for instance boron or aluminium), and/or a dopant concentration (number of dopant atoms per volume) may be spatially dependent along the gate structure. This may include an architecture in which the doping profile is constant over a first portion of the gate structure (for instance along the entire gate region) but is not constant over a second portion of the gate structure (for instance along the entire gate extension).

According to an exemplary embodiment of the invention, a FET is provided which has two distinguished well portions (which may be oppositely doped), wherein the two well portions may be arranged facing or opposing assigned gate portions, so that a gate region opposing a well region and a gate extension opposing a well extension can be formed. Thus, an EDMOS structure may be provided which has an extended drain and precisely adjustable transistor properties resulting from a spatially varying doping profile of the gate structure as a design parameter, particularly a spatially varying doping profile of one or both of the gate region and the gate extension. A thin gate insulating structure may separate the well structure from the gate structure. The gate insulating structure may be a layer having a constant thickness so as to prevent any disturbation of the deeper located current flow path by the gate insulating structure. In contrast to this, the doping profile of the gate structure in combination with the doping characteristic of the well structure may allow to manipulate or adjust a current flow between source and drain of the FET deeply inside of the substrate which allows a precise field shaping.

According to an exemplary embodiment of the invention, a field effect transistor may be provided comprising a well region, an extended well region extending substantially in plane to the well region, a gate region adapted for electrically influencing the well region wherein a gate oxide region is interposed between the well region and gate region, and an extended gate region extending substantially in plane to the gate region thereby covering at least a part of the extended well region, wherein the extended gate region comprises a gradually doped profile and/or different type of dopants.

With such an architecture, it may be possible to obtain a breakdown voltage improvement without on-resistance penalty and signification improvement of hot carrier reliability in for instance extended drain MOSFETs without any additional process step and thus free of additional cost. This may allow an improvement for devices such as used e.g. in embedded power management (voltage regulators or DC:DC converters), power amplifiers for connectivity solutions or LED drivers. According to an exemplary embodiment of the invention, a field effect transistor may be provided comprising a well structure including a well region and a well extension region, and a gate structure including a gate portion and a gate extension portion, wherein the gate structure extends over the well structure and there is a doping variation in the gate structure. Therefore, such a device may be characterized particularly by the feature that the separation between the gate electrode and the wells/channel/semiconductor substrate surface/extension region is constant. A device according to an exemplary embodiment of the invention may be characterized by its gate and drain being isolated from one another.

Next, further exemplary embodiments of the field effect transistor will be explained. However, these embodiments also apply to the method. The well region may have a first type of conductivity (for instance p-type or n- type), and the well extension may have a second type of conductivity (for instance n-type or p- type) differing from the first type of conductivity. For example, the substrate may be a semiconductor substrate such as a silicon substrate. The well region may be formed in the substrate by a dopant of a first type of conductivity, for instance by a dopant of the p-type of conductivity (such as aluminium). In contrast to this, the well extension may have a second type of conductivity, which may be complementary to the first type of conductivity. In the present example, the second type of conductivity may have an n-type conductivity, which may be obtained by a dopant such as arsenide. However, in another embodiment, it is also possible that the first type of conductivity is the n-type of conductivity and the second type of conductivity is the p-type of conductivity. By taking such a measure, a pn-junction and thus a diode like architecture may be formed between the well region and the well extension.

The gate region may have a first type of conductivity, and the gate extension may have a second type of conductivity differing from the first type of conductivity. For example, the gate region may be made of a semiconductor being n-doped, whereas the gate extension may be made of a semiconductor being p-doped. Alternatively, it is also possible that the gate region is p-doped and the gate extension is n-doped. According to a further exemplary embodiment, both the gate region and the gate extension may have the same type of conductivity (both p-type or both n-type) but may differ regarding the concentration of the dopant. In such embodiments, the concentration of the dopant within the gate region may be constant, and the concentration in the gate extension may be constant.

According to another exemplary embodiment, a dopant concentration of the gate extension may be graded along the second surface portion. In other words, in a lateral direction perpendicular to a normal of a main surface of the substrate, the dopant concentration of the gate extension may be spatially dependent, for instance may increase or decrease in a (mathematically) continuous manner. It is also possible that such a spatial dependence is achieved by a non-continuous stepwise configuration in which the dopant concentration is increased or decreased in steps. In other words, it is possible that the doping concentration within the gate region is a function of the distance of a sub-portion of the gate extension from a border between gate region and gate extension. Different materials, doping profiles, etc, may distinguish gate region and gate extension.

In a similar manner as described above for the gate extension, it is also possible that a dopant concentration of the gate region is graded along the first surface portion, for instance in a continuous or step-wise manner. However, alternatively, it is possible that the dopant concentration of the gate region is constant over the entire first surface portion, whereas the dopant concentration of the gate extension is spatially dependent along the second surface portion. Many other configurations are possible and within the scope of the present invention. The gate insulating structure may be a gate insulating layer (i.e. an essentially two-dimensional planar structure) having a constant thickness along the gate structure. This thickness may be less than basically 10 nm, particularly less than basically 5 nm, more particularly less than basically 3 nm. However, the thickness may be even larger with modern high-k gate insulating layers. The gate insulating structure may be configured in such a manner that the field effect is mediated between the gate structure and the well structure via the gate insulating structure.

The field effect transistor may further comprise a (for instance highly-doped) source region adjacent the well region and a (for instance highly-doped) drain region adjacent the well extension. However, the terms source region and drain region may also be exchanged or may be denoted as first and second source/drain regions. The source region and the drain region may both be heavily doped portions at which an electric signal to be conducted through the channel of the field effect transistor is supplied (source) or is guided off (drain).

The field effect transistor may be free of a field oxide structure (FOX) which extends into the well structure. Such a field oxide structure, as a mechanical barrier, may disturb or influence the current path within the well structure. Embodiments of the invention take another approach for accurately adjusting a current path, namely by adjusting a spatial dependence of the dopant concentration within the gate structure, particularly between the gate region and the gate extension. This may allow for a simplified manufacture procedure, since efforts for forming an insulating structure extending vertically into the substrate in a region influencable by the gate may be omitted.

A distance between an upper end portion of the well structure and a lower end portion of the gate structure may be constant over the entire lateral dimension of the gate structure. Therefore, a highly symmetrical and undisturbed, therefore mechanically stable configuration, may be obtained. A deepness of the well region within the substrate and a deepness of the well extension within the substrate may be equal. In other words, along the entire vertical extension of the well region and the well extension, the two well portions may abut to one another.

A thickness of the gate region vertical to the substrate and a thickness of the gate extension vertical to the substrate may be equal or identical. This may allow manufacturing the gate region and the gate extension on the basis of a common deposition (or growth) procedure. Different properties between gate region and gate extension may then be adjusted with different doping procedures for the two gate portions, which may be achieved for example by using implant masks as available in the process flow. A transition from the gate region to the gate extension may be spatially matched to a transition from the well region to the well extension in a direction perpendicular to a surface of the substrate. Thus, the gate region may be vertically aligned with the well region, and the gate extension may be vertically aligned with the well extension.

In the following, further exemplary embodiments of the method will be explained. However, these embodiments also apply to the field effect transistor.

According to an exemplary embodiment, the method may comprise forming the gate structure to have a spatially varying doping profile by forming a mask covering the gate extension but exposing at the same time the gate region, and by subsequently implanting a dopant into the exposed gate region but not into the covered gate extension. A dopant implantation into the covered gate extension may be prevented by the mask, wherein dopant implantation is enabled for the exposed gate region. This allows, with easy measures, to define a different doping profile in the gate extension as compared to the gate region.

Furthermore, the method may comprise forming the gate structure to have a spatially varying doping profile by removing the mask, forming a further mask exposing the gate extension and covering the gate region, and by subsequently implanting a further dopant into the exposed gate extension but not into the covered gate region. By taking this measure, the previously described procedure is inversed, the gate extension is exposed with a further mask and the further mask covers the gate region. Then, another dopant or another dopant concentration may be injected into the exposed gate extension, wherein the covered gate region is protected by the further mask from being treated with the further dopant.

Additionally or alternatively, the gate structure may be formed to have a spatially varying doping profile by diffusion of a part of the dopant implanted into the gate region into the gate extension, for example by annealing. For example a thermal annealing procedure may allow to diffuse dopant atoms which have previously been injected only in one of the gate region and the gate extension, to migrate into the other one of the gate region and the gate extension, thereby generating a graded doping profile between gate region and gate extension.

According to an exemplary embodiment of the invention, a part of the gate may be undoped. The gate may be doped with opposite doping than usually (for instance for n- MOS, p-type doping in normally n-type doped gate) on the section above the p-well/n-well junction. Such a gate configuration may lead to current push deeper to the bulk (away from surface) for an extended-drain MOSFET. In a device that uses STI (shallow trench insulation) in the drain extension, the current may flow into depth by default. Furthermore, a gate configuration according to another exemplary embodiment of the invention has an undoped gate portion above the well/extension junction.

The gate extension can be suicided or unsilicided.

The device may be manufactured in CMOS technology. Any CMOS technology generation may be used. When using CMOS technology, a known and cheap method may be used for manufacturing the transistor.

The substrate may be a semiconductor substrate. The transistor device may be monolithically integrated in the semiconductor substrate, particularly comprising one of the group consisting of a group IV semiconductor (such as silicon or germanium), or of a group Ill-group V semiconductor (such as gallium arsenide). For any method step, any conventional procedure as known from semiconductor technology may be implemented. Forming layers or components may include deposition techniques like CVD (chemical vapour deposition), PECVD (plasma enhanced chemical vapour deposition), ALD (atomic layer deposition), oxidation or sputtering. Removing layers or components may include etching techniques like wet etching, plasma etching, etc., as well as patterning techniques like optical lithography, UV lithography, electron beam lithography, etc.

Embodiments of the invention are not bound to specific materials, so that many different materials may be used. For conductive structures, it may be possible to use metallization structures, suicide structures or polysilicon structures. For semiconductor regions or components, crystalline silicon may be used. For insulating portions, silicon oxide or silicon nitride may be used.

The transistor may be formed on a purely crystalline silicon wafer or on an SOI wafer (Silicon On Insulator).

Any process technologies like CMOS, BIPOLAR, BICMOS may be implemented.

The aspects defined above and further aspects of the invention are apparent from the examples of embodiment to be described hereinafter and are explained with reference to these examples of embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described in more detail hereinafter with reference to examples of embodiment but to which the invention is not limited.

Fig. 1 illustrates a conventional field effect transistor with an implementation of a field plate in a metal layer, wherein a silicon oxide thicker than a gate oxide is used between the metal field plate and a drain extension.

Fig. 2 illustrates a conventional field effect transistor with an extension of a gate over a drain extension acting as field plate, wherein the thin gate oxide separating the gate field plate from the drain extension severely limits this device. Fig. 3 illustrates a field effect transistor with an conventional implementation with an extension of a gate over a LOCOS and a field plate in a metal layer.

Fig. 4 illustrates a field effect transistor with a conventional addition of an extra n-implant to divert a current into a depth.

Fig. 5 illustrates a field effect transistor with a conventional addition of a p-top layer implant to divert a current into a depth.

Fig. 6 illustrates a field effect transistor with a conventional structure involving metal gates, where the gate overlap (field plate) is formed by a different metal material.

Fig. 7 illustrates a field effect transistor according to an exemplary embodiment of the invention having a grading of the doping profile in gate/gate extension. Fig. 8 illustrates a field effect transistor according to an exemplary embodiment of the invention having different doping types in gate and gate extension.

Fig. 9 to Fig. 12 illustrates diagrams relating to different field effect transistors having an extended drain n-MOS with a 100 nm gate overlap of drain extension either doped n-type 10²⁰ cm^"3 (Fig. 9), n-type 10¹² cm^"3 (Fig. 10), p-type 10¹⁸ cm^"3 (Fig. 11), and a vertical cross-section of an electron current density just in the varying doping part (Fig. 12).

Fig. 13 to Fig. 15 illustrate layer sequences involving a mask and an implant for implementing a graded doping in a gate/gate-extension for manufacturing a field effect transistor according to an exemplary embodiment of the invention.

Fig. 16 to Fig. 19 illustrate layer sequences involving masks and implants for implementing an n⁺-doping and a p⁺-doping in a gate/gate-extension for manufacturing a field effect transistor according to an exemplary embodiment of the invention.

Fig. 20 illustrates an experimental example of a reliability improvement due to an undoped gate edge. DESCRIPTION OF EMBODIMENTS

The illustration in the drawing is schematical. In different drawings, similar or identical elements are provided with the same reference signs.

In the following, some basic recognitions of the present inventor regarding conventional field effect transistor structures will be explained based on which exemplary embodiments of the invention have been developed.

In order to enhance the reverse voltage capability of semiconductor devices, the fields at the relevant reverse biased junctions should be properly or optimally shaped. This can be done by proper tuning/shaping doping profiles, or choosing geometries and implementing additional field shaping electrodes or combinations. The latter - extra shaping of the field by electrodes - may be referred to as field plates that are implemented as electrodes in the back-end stack (on top of the active devices, more or less horizontal) or incorporated in the vertical direction (mostly in discrete devices) as trench electrodes. The usage of such field shaping field plates may be implemented in high voltage LDMOS devices. Examples of conventional implementations of an LDMOS with gate field plates are shown in Fig. 1, Fig. 2, Fig. 3.

Fig. 1 illustrates a conventional field effect transistor 100 having a silicon substrate 102 being slightly p-doped, a p-well 104, an n-extension 106, a source region 108, a drain region 110 and an n⁺-doped gate 112. A metal field plate 114 is embedded in a silicon oxide structure 116. The portions of the source 108 and the drain 110 adjacent the channel are n⁺-doped regions.

Fig. 2 shows another conventional field effect transistor 200 having an oblong constantly n⁺-doped gate 112.

Fig. 3 illustrates another conventional field effect transistor 300 having a LOCOS (local oxidation of silicon) region 302.

Examples of dedicated deeper (buried) implants and surface counter doping to improve performance and reliability are shown in Fig. 4, Fig. 5. In both cases, a dedicated implant is needed.

Fig. 4 shows an embodiment in which a buried implant region 402 is provided in the well extension 106 of a field effect transistor 400. By taking this measure, a current path 404 can be influenced in a way as shown in Fig. 4.

In case of a conventional field effect transistor 500, an additional p-top layer implant 502 is provided to manipulate the current path 404.

Another example to shape fields is shown in Fig. 6. This configuration is based on using different gate metal material in the field plate region. Such a solution is however complex from a processing point of view.

Fig. 6 thus shows another conventional field effect transistor 600 having a gate which is formed by a first metal portion 602 and a second metal portion 604 (made of a different metal than the first metal portion 602) embedded in the silicon oxide structure 116, so that members 602 and 604 together form a gate structure.

In standard CMOS, gates are in general formed as polysilicon gates with a high n-type doping in n-MOS and a high p-type doping in p-MOS (which enable comparable threshold voltages for n-MOS and p-MOS). In specific MOS devices, which should withstand higher drain voltages, lower doping levels in the drain extensions are used. In addition, so called field plates or gate extensions may be used shaping the electric fields in such a way that the breakdown voltage is increased and hot carrier reliability is improved. Examples of such drain extensions gate extensions and field plates are shown in Fig. 1, Fig. 2 and Fig. 3.

A challenge in high voltage devices is the phenomenon of degradation of the characteristics caused by Hot Carrier Injection. Strong hot carrier degradation due to charge trapping at the Si/Siθ2 interface or in the Siθ2 may appear if one or a combination of the following events occurs:

- High current flowing through regions with a high electrical field

- Electron current flow near silicon/oxide interface - Poor quality Si/ Siθ2 interface and poor Siθ2 quality

These trapped charges and the induced damage or interface states may degrade the performance. It is possible to reduce the Hot Carrier degradation by reducing the electric field and/or avoid that the current/high field combination is close to the silicon/oxide interface where charges are trapped easily. Doping profile and electrodes such as the gate/field plates can shape both the positions and strength of the high electric field and the current paths. The path of the current in the drain extension can for instance be diverted deeper into the silicon by making the drain extension buried either by adding an extra n-implant or a p-top layer as shown in the Fig. 4 and Fig. 5 before.

According to an exemplary embodiment of the invention, the doping in the gate and/or gate extension is used as a mechanism to shape fields and current path. In devices with thick gate oxides or thick layers between field plate and silicon it does not matter that much whether the material of the field plate/gate extension is n-type poly, p-type poly or metal. With thin gate oxides and shrinking dimensions (and as a consequence lower gate voltages) this is different: the effective voltage can be about 1 Volt different (using n-type or p-type poly). This is quite relevant with gate voltage ranges of 0 to 1 Volt up to 0 to 5 Volt in modern CMOS. This allows using the doping level/doping type to modify the voltage distribution and also the path of the current by introducing lateral doping profiles in gate/gate-extension/fϊeld plates. In the following, referring to Fig. 7, a field effect transistor 700 according to an exemplary embodiment of the invention will be explained. In Fig. 7 a graded doping profile in a gate/gate-extension is sketched.

The field effect transistor 700 is formed on the basis of a semiconductor substrate 702 such as a silicon substrate or wafer. It is also possible that the substrate 702 is an SOI substrate (silicon-on-insulator) or is made from another material than silicon, such as germanium.

In a surface portion of the silicon substrate 702, a well structure is formed which comprises a well region 704 formed in a first surface portion of the substrate 702 and a well extension 706 formed in a second surface portion of the substrate 702 adjacent the first surface portion. The well region 704 is a p-doped region, whereas the well extension 706 is n- doped. The silicon substrate 702 is slightly p-doped.

Furthermore, a gate structure is formed on top of (or more precisely above) the substrate 702 and comprises a gate region 708 formed above the first surface portion of the substrate 702 and a gate extension 710 formed above the second surface portion of the substrate 702.

A gate insulating structure 712 such as a thin silicon oxide layer is sandwiched vertically between the gate structure and the well structure and ohmically decouples the gate structure from the well structure. By the gate insulating layer 712, the field effect is mediated, and a direct ohmic coupling between gate structure and well structure is prevented. As can be taken from Fig. 7, the gate insulating structure 712 is a layer having a constant or uniform thickness, d, of, for instance, 3 nm along the entire horizontal extension of the gate structure.

As will be explained in the following in more detail, the gate structure has a spatially varying doping profile, particularly in a horizontal direction of Fig. 7.

Both the gate region 708 and the gate extension 710 are made of a semiconductor material such as silicon. In the described embodiment of Fig. 7, the gate region 708 is n⁺-doped with a constant doping concentration, whereas the gate extension 710 is also n⁺-doped but having a concentration of n dopant atoms which continuously decreases with increasing horizontal distance from an abutment area 730 between the gate region 708 and the gate extension 710. In other words, the closer a portion of the gate extension 710 is to the abutment area 730, the higher the ^-concentration. Thus, a dopant concentration of the gate extension 710 is graded along the second surface portion.

An n⁺-doped source region 714 is formed within the well region 704. An n⁺- doped drain region 716 is electrically coupled with the well extension 706, more precisely is formed within the well extension 706.

Above the gate structure 708, 710, a thick silicon oxide top layer 740 is formed.

As explained above, the distance, d, between an upper end portion of the well structure 704, 706 and a lower end portion of the gate structure 708, 710 is constant over the entire lateral dimension, L, of the gate structure. This provides for a very homogeneous architecture.

A deepness, D, of the well region 704 within the substrate 702 and a deepness, D, of the well extension 706 within the substrate 702 are equal. Also this contributes to a very homogeneous structure. A thickness, b, of the gate region 708 vertical to the substrate 702 and a thickness, b, of the gate extension 710 vertical to the substrate 702 are equal. This allows to manufacture the gate region 708 and the gate extension 710 by a common deposition or growth procedure.

As can be taken from reference numeral 750, the lateral transition 730 from the gate region 708 to the gate extension 710 is spatially matched with a transition 740 from the well region 704 to the well extension 706.

Fig. 8 illustrates a field effect transistor 800 according to another exemplary embodiment of the invention. In Fig.8, a doping type is shown which is different in gate and gate-extension. The field effect transistor 800 differs from the field effect transistor 700 particularly in that the gate extension 710 having a graded dopant concentration is substituted by a gate extension 710' having a constant dopant concentration. However, the gate extension 710' is p⁺-doped, and therefore has a type of conductivity of the dopant which is opposite to the type of conductivity of the n⁺-doped gate region 708. Profiling the doping in gate, gate extension and field plates can be done by layout of masks, which allows fine details in CMOS and is free of cost.

This doping profiling allows pushing the current path at the edge of a gate/gate extension deeper into the silicon, which may reduce Hot Carrier Effects.

As an example, the simulated current path is shown in diagrams 900, 1000, 1100, 1200 of Fig. 9 to Fig. 12 with three implementations of the gate edge overlapping the drain extension, i.e. doped n-type 10²⁰ cm^"3, doped n-type 10¹² cm^"3 or p-type 10¹⁸ cm^"3.

The current density as simulated shows that the current is pushed into depth by the p-type gate doping which will reduce hot carrier effects. It is clear that it is possible to use the doping profiling in general because it induces a varying effective potential of the gate.

Mask/implants which may be used for manufacturing field effect transistors according to exemplary embodiments of the invention are sketched in Fig. 13 to Fig. 15 for the graded/undoped extension (compare Fig. 7) and in Fig. 16 to Fig. 19 for a structure with a transition from n-type to p-type in the gate/gate-extension (compare Fig. 8) showing that this fits in the standard CMOS flow and no extra process steps are required.

In the following, referring to Fig. 13 to Fig. 15, a method of manufacturing the field effect transistor 700 shown in Fig. 7 will be explained.

Fig. 13 starts from a layer sequence in which a semiconductor 1306 such as silicon has been deposited on the gate insulating layer 712 which is made of silicon oxide. Subsequently, a first mask 1310 is provided to shield the later gate extension portion but expose the later gate region portion of the semiconductor layer 1306.

Subsequently, an n-dopant 1304 is implanted into the exposed portion of the semiconductor structure 1306 but not into the shielded portion of the semiconductor structure 1306. Consequently, a layer sequence 1400 as shown in Fig. 14 is obtained in which the semiconductor layer 1306 has been converted into an n-doped portion 1402, and a remaining portion 1306 is undoped. As can be taken from Fig. 13 and Fig. 14, due to the design of the mask 1302, the first n⁺-doping 1304 simultaneously forms the source region 714 and the drain region 716. This is achieved by the shielding effect of the first mask 1302 as well as of the layer sequence 712, 1306.

As can be taken from Fig. 15, a layer sequence 1500 can be obtained on the basis of the layer sequence 1400 by forming the gate structure to have a spatially varying doping profile by diffusing (see arrow 1502) of a part of the first n⁺-dopant 1304, previously implanted into the gate region 708, into the gate extension 710 by thermal annealing. In the following, referring to Fig. 16 to Fig. 19, a method of forming the field effect transistor 800 shown in Fig. 8 according to another exemplary embodiment of the invention will be explained.

The procedure shown in Fig. 16 equals to the procedure shown in Fig. 13.

However, as an alternative to the procedure of Fig. 15, a further mask 1702 is provided exposing the later gate extension and covering the later gate region. Then, a further dopant 1704, in this embodiment a p⁺-dopant, is implanted into the exposed later gate extension but not into the covered later gate region. The result can be shown in a layer sequence 1800 shown in Fig. 18. To obtain a layer sequence 1900 shown in Fig. 19, annealing may diffuse the dopant.

Fig. 20 shows a diagram 2000 having an abscissa 2002 along which the stress time is plotted in minutes. Along an ordinate 2004, degradation is plotted. As can be taken from the diagram 2000, the reliability of a field effect transistor according to an exemplary embodiment, illustrated as a curve 2006 is improved as compared to a traditional EDMOS configuration, see curve 2008.

An embodiment of the invention has already been implemented in an advanced TSMC 65 nm CMOS technology. Clear improvement in reliability due to this gate edge engineering (sufficiently long and undoped poly overlap) was measured and is shown in Fig. 20.

Finally, it should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims. In the claims, any reference signs placed in parentheses shall not be construed as limiting the claims. The words "comprising" and "comprises", and the like, do not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole. The singular reference of an element does not exclude the plural reference of such elements and vice-versa. In a device claim enumerating several means, several of these means may be embodied by one and the same item of software or hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:

1. A field effect transistor (700), wherein the field effect transistor (700) comprises a substrate (702); a well structure comprising a well region (704) formed in a first surface portion of the substrate (702) and a well extension (706) formed in a second surface portion of the substrate (702) adjacent the first surface portion; a gate structure comprising a gate region (708) formed over the first surface portion of the substrate (702) and a gate extension (710) formed over the second surface portion of the substrate (702); a gate insulating structure (712) for ohmically decoupling the gate structure from the well structure and having a uniform thickness (d) along the gate structure; wherein the gate structure has a spatially varying doping profile.

2. The field effect transistor (700) of claim 1, wherein the well region (704) is doped with a dopant of a first type of conductivity and the well extension (706) is doped with a dopant of a second type of conductivity differing from the first type of conductivity, particularly in such a manner that a pn-junction is formed between the well region (704) and the well extension (706).

3. The field effect transistor (800) of claim 1, wherein the gate region (708) is doped with a dopant of a first type of conductivity and the gate extension (710') is doped with a dopant of a second type of conductivity differing from the first type of conductivity.

4. The field effect transistor (700) of claim 1, wherein a dopant concentration of the gate extension (710) is graded along the second surface portion.

5. The field effect transistor (700) of claim 1, wherein a dopant concentration of the gate region (708) is graded along the first surface portion.

6. The field effect transistor (700) of claim 1, wherein the gate insulating structure (712) is a gate insulating layer having a constant thickness (d) along the entire gate structure, particularly having a constant thickness (d) of less than 10 nm, more particularly having a constant thickness (d) of less than 5 nm, even more particularly having a constant thickness (d) of less than 3 nm.

7. The field effect transistor (700) of claim 1, comprising a first source/drain region, particularly a source region (714), arranged adjacent the well region (704); and a second source/drain region, particularly a drain region (716) ohmically coupled with the well extension (706).

8. The field effect transistor (700) of claim 1 , being free of any field oxide structure extending into the well structure.

9. The field effect transistor (700) of claim 1, wherein a distance (d) between an upper end portion of the well structure and a lower end portion of the gate structure is constant over the entire lateral dimension (L) of the gate structure.

10. The field effect transistor (700) of claim 1, wherein a deepness (D) of the well region (704) within the substrate (702) and a deepness (D) of the well extension (706) within the substrate (702) are equal.

11. The field effect transistor (700) of claim 1 , wherein a thickness (b) of the gate region (708) vertical to the substrate (702) and a thickness (b) of the gate extension (710) vertical to the substrate (702) are equal.

12. The field effect transistor (700) of claim 1, wherein a transition from the gate region (708) to the gate extension (710) is spatially matched with a transition from the well region (704) to the well extension (706) in a direction perpendicular to a surface of the substrate (702).

13. A method of manufacturing a field effect transistor (700), the method comprising forming a well structure comprising a well region (704) in a first surface portion of a substrate (702) and a well extension (706) in a second surface portion of the substrate (702) adjacent the first surface portion; forming a gate structure comprising a gate region (708) over the first surface portion of the substrate (702) and a gate extension (710) over the second surface portion of the substrate (702); forming a gate insulating structure (712) for ohmically decoupling the gate structure from the well structure and having a uniform thickness (d) along the gate structure; wherein the gate structure is formed to have a spatially varying doping profile.

14. The method of claim 13, comprising forming the gate structure to have a spatially varying doping profile by providing a mask (1302) shielding the gate extension (710) and exposing the gate region (708); subsequently implanting a dopant (1304) into the exposed gate region (708) but not into the shielded gate extension (710).

15. The method of claim 14, comprising forming the gate structure to have a spatially varying doping profile by providing a further mask (1702) exposing the gate extension (710) and shielding the gate region (708); subsequently implanting a further dopant (1704) into the exposed gate extension (710) but not into the shielded gate region (708).

16. The method of claim 14, comprising forming the gate structure to have a spatially varying doping profile by diffusing (1502) a part of the dopant (1304) from the gate region (708) into the gate extension (710), particularly by annealing.