CN113270477A - 一种降低主结体电场的积累场效应晶体管及其制作方法 - Google Patents

一种降低主结体电场的积累场效应晶体管及其制作方法 Download PDF

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CN113270477A
CN113270477A CN202110379146.1A CN202110379146A CN113270477A CN 113270477 A CN113270477 A CN 113270477A CN 202110379146 A CN202110379146 A CN 202110379146A CN 113270477 A CN113270477 A CN 113270477A
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段宝兴
王彦东
杨银堂
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Abstract

本发明公开一种降低主结体电场的积累场效应晶体管及其制作方法。该器件中设置积累介质层，覆盖P型基区与N+漏区之间的区域；设置半导体材料的外延层，覆盖所述积累介质层；积累栅极和积累漏极，分别位于外延层的左端侧面、右端侧面；欧姆栅极与积累栅极通过导线连接，整体作为器件的栅极；欧姆漏极与积累漏极通过导线连接，整体作为器件的漏极。积累介质层可在衬底表面引入高浓度电子形成器件的电流通道，降低器件的导通电阻，同时取消传统LDMOS器件中的N型漂移区，在衬底中引入了N型埋层，可降低主结处的体电场(Reduced Bulk Field，REBULF)，从而提升器件的击穿电压。

Description

一种降低主结体电场的积累场效应晶体管及其制作方法
技术领域
本发明涉及半导体功率器件技术领域，具体涉及一种横向双扩散金属氧化物半导体场效应管。
背景技术
横向双扩散金属氧化物半导体场效应管(Lateral Double-diffused MOSFET，简称LDMOS)作为多子导电器件，且源、栅、漏三个电极均位于器件表面，很容易与其他控制电路、保护电路和逻辑电路集成在一起，已广泛应用于功率集成电路领域，。
目前LDMOS的耐压主要由轻掺杂的漂移区承担，一般采用(Reduced SurfaceField，RESURF)降低表面电场。LDMOS导通时，导通电阻由漂移区掺杂浓度直接决定，低的掺杂浓度会导致导通电阻的急剧增加。因此，无法通过简单的降低掺杂浓度来提高击穿电压。器件结构的优化设计过程中，在提高器件耐压的同时，降低器件的比导通电阻，进而实现耐压与比导通电阻特性的良好折中，成为LDMOS器件研究的热点问题。
然而目前常采用的方法都是基于N型掺杂的漂移区作为导电通道，低的电阻需要高的掺杂浓度；通过N型掺杂的漂移区耐压，高的击穿电压需要低的掺杂浓度，从根本上决定了击穿电压和比导通电阻二者存在矛盾的关系。
发明内容
为了解决现有LDMOS器件无法同时兼顾击穿电压和比导通电阻问题，本发明提出了一种降低主结体电场的积累场效应管，通过积累层的电子导电，消除了N型漂移区，通过N型埋层降低主结的电场，可大幅度提高器件的击穿电压。
同时，还提供了该效应管的制作方法。
本发明的技术方案如下：
一种降低主结体电场的积累场效应管，包括：
P型衬底，P型衬底的背面设置有衬底电极；
在P型衬底上部左端区域形成的P型基区，在P型基区中形成相应的沟道以及N+源区和P+源区；
在P型衬底右侧区域形成至少一个N型埋层，所述N型埋层水平方向上与P型基区水平方向上存在间隔，垂直方向上与积累介质层存在间隔；
P型衬底的右上角区域形成N+漏区；
源极，位于P+源区与N+源区上方；
栅极介质层，覆盖N+源区右侧的沟道表面区域；
欧姆栅极，覆盖所述栅极介质层；
欧姆漏极，位于N+漏区表面；
积累介质层，位于P型衬底上表面，且覆盖P型基区与N+漏区之间的区域；
外延层，覆盖在所述积累介质层上方；
积累栅极和积累漏极，分别位于外延层的左端区域、右端区域；
N+阻挡层位于外延层的右侧，且与积累漏极存在间隔；
所述欧姆栅极与积累栅极通过导线连接，整体作为器件的栅极；
所述欧姆漏极与积累漏极通过导线连接，整体作为器件的漏极。
可选地，所述P型衬底的掺杂浓度为1×1013cm-3～1×1015cm-3；
可选地，N型埋层的掺杂浓度为1×1015cm-3～1×1018cm-3；当N型埋层至少为两个时，每个N型埋层互相之间存在垂直方向的间隔，每个N型埋层的水平方向为等长度设置或者不等长度设置；且在水平方向上最上方的N型埋层的左侧不超过外延层的左侧；
每个N型埋层垂直方向上为等间距布置或者不等间距布置；
最上方的N型埋层与积累介质层的间隔为1-8微米。
可选地，上述积累介质层的材料为绝缘材料，所述积累介质层的厚度为0.03-0.2微米。
可选地，上述外延层分为掺杂型外延层和非掺杂型外延层两种，且均采用半导体材料制作，厚度为0.2～5微米；掺杂型外延层的掺杂浓度为1×1013cm-3～1×1015cm-3，其掺杂类型为N型掺杂或P型掺杂；
可选地，所述积累栅极和积累漏极可以为欧姆接触或肖特基接触。若积累栅极和积累漏极为欧姆接触，则第一P型区和第二P型区不可省略，浓度为1×1016cm-3～1×1019cm-3(这两个浓度可以不相等)；若积累栅极和积累漏极为肖特基接触，则第一P型区和第二P型区可以有，但可以省略，势垒均为0.5-1eV(这两个接触势垒可以不相等)。
可选地，所述N+阻挡层与积累漏极之间的距离为0.5-3μm。
可选地，所述N+阻挡层的掺杂浓度为1×1017cm-3～1×1019cm-3。
上述降低主结体电场的积累场效应管的一种制作方法，包括以下步骤：
1)取P型衬底，并形成衬底电极；
2)通过离子注入和扩散形成P型基区、N+源区和P+源区，通过离子注入和扩散形成N型埋层和N+漏区；
3)另选取0.3-5微米的外延层材料，在其底面生长积累氧化层，然后通过键合工艺与P型衬底相连接；在外延层上通过离子注入形成N+区，第一P型区和第二P型区；
4)在沟道上方形成栅介质层，并淀积金属形成欧姆栅极；在N+源区和P+源区上方淀积金属形成源极；在N+漏区上方淀积金属形成欧姆漏极；
5)外延层上方两侧分别淀积金属，形成积累栅极和积累漏极；
6)将欧姆栅极与积累栅极相连，形成栅极；将欧姆漏极与积累漏极相连，形成漏极；
7)在器件表面形成钝化层。
本发明技术方案的有益效果如下：
从矛盾的源头N型漂移区出发，取消了在P型衬底上形成N型漂移区，改变了器件的导通和耐压模式。
器件导通基于积累层结构产生的电子沟道，而不是像传统LDMOS器件采用N型漂移区，没有形成N型漂移区自然消除了RESURF技术对浓度的限制，可以通过降低掺杂浓度来实现高的击穿电压。利用REBULF技术降低主结附近的电场，使得器件的击穿点位于器件的内部，进一步提升了器件的击穿电压。通过积累介质层在源极和漏极之间形成高密度的电子，与通过N型漂移区传输电流的传统LDMOS相比，减小了电流路径上的电阻，使得器件的比导通电阻大幅度下降。
由于在器件开启时，会在积累介质层下方形成电子，但同时会在积累介质层上方形成等量的空穴，设置N+阻挡层可阻断氧化层上方外延层中的空穴电流。
附图说明
图1为本发明的一个实施例的结构示意图。
图2是本发明实施例与普通LDMOS的纵向电场对照示意图。
图3是本发明实施例与普通LDMOS的导通电阻对照示意图。
图4是本发明实施例与普通LDMOS的击穿电压对照示意图。
附图标号说明：
1-P型衬底；2-P型基区；3-P+源区；4-源极；5-N+源区；6-栅介质层；7-欧姆栅极；8-积累栅极；9-第一P型区；10-积累介质层；11-外延层；12-N+阻挡区；13-第二P型区；14-积累漏极；15-欧姆漏极；16-N+漏区；17-N型埋层；18-衬底电极。
具体实施方式
以下结合附图，通过实施例进一步详述本发明。
本实施例提供了降低主结体电场的积累场效应管的具体结构，如图1所示，效应管包括：
P型衬底1；掺杂浓度典型值为1×1013cm-3～1×1015cm-3；
P型衬底底面形成衬底电极18；
在P型衬底上形成的P型基区2，基区的浓度由阈值电压决定，基区中形成相应的沟道以及N+源区5和P+源区3；
在P型衬底上形成的N型埋层17以及N+漏区16，N型埋层17的浓度、个数及位置需要根据器件的耐压决定；N型埋层17的掺杂浓度典型值为1×1015cm-3～1×1018cm-3；当N型埋层17至少为两个时，每个N型埋层17互相之间存在垂直方向的间隔，每个N型埋层的水平方向为等长度设置或者不等长度设置；且在水平方向上最上方的N型埋层17的左侧不超过外延层11的左侧；每个N型埋层垂直方向上为等间距布置或者不等间距布置；最上方的N型埋层17与积累介质层10的间隔为1-8微米。
在P+源区3与N+源区5的表面形成的源极4；
在N+源区(5)右侧的沟道上方形成栅极介质层6；
在P型衬底(1)上表面，且位于P型基区2与N+漏区5之间形成积累介质层10，积累介质层10的厚度由工艺决定，厚度越小导通电阻越低，厚度典型值为0.03-0.2微米；积累介质层材料可选择二氧化硅或高K材料；
在积累介质层10上方设置外延层11，外延层11分为掺杂型外延层和非掺杂型外延层两种，且均采用半导体材料制作，厚度为0.2～5微米；掺杂型外延层的掺杂浓度为1×1013cm-3～1×1015cm-3，其掺杂类型为N型掺杂或P型掺杂；
在外延层中靠近漏端通过离子注入形成N+阻挡区12；N+阻挡区12与积累漏极14之间的间隔为0.5-3μm，N+阻挡区12的掺杂浓度为1×1017cm-3～1×1019cm-3；
积累栅极8和积累漏极14，分别位于外延层左、右两端侧面；
欧姆栅极7，覆盖于栅极氧化层6上方；
欧姆漏极15，位于N+漏区16表面；
欧姆栅极7与积累栅极8相连，作为器件的栅极；
欧姆漏极13与积累漏极14相连，作为器件的漏极。
需要说明的一点是：积累栅极8和积累漏极14为欧姆接触或者肖特基接触。
若积累栅极8和积累漏极14是欧姆接触，则通过离子注入的方式在外延层11的左侧与积累栅极8之间设置第一P型区9，同时以同样的方式在N+阻挡区12和积累漏极14之间设置第二P型区13。
若是积累栅极8和积累漏极14是肖特基接触，则第一P型区9和第二P型区13可以省略，也可保留。
如图2所示，该器件通过N型埋层将现有LDMOS漏端的高电场重新分配，使得击穿位置发生改变。新结构突破了横向器件中弱化表面电场(Reduced Surface Field，简称RESURF)条件的限制，从而可通过利用从衬底较低的浓度获得高的击穿电压。
该器件可按照以下步骤制备：
步骤1：取P型衬底1，并在P型衬底1的底面形成衬底电极18；
步骤2：通过离子注入和扩散的方式在P型衬底1的左上角区域形成P型基区2、N+源区5和P+源区3，通过离子注入和扩散的方式在P型衬底1的右侧区域形成N型埋层17和N+漏区16；
步骤3：另选取外延层11材料，在其底面生长积累介质层10，然后通过键合工艺与P型衬底1相连接；
步骤4：在N+源区5右侧的沟道表面区域形成栅介质层6，并在栅介质层6上方淀积金属形成欧姆栅极7；在N+源区5和P+源区3上方淀积金属形成源极4；在N+漏区16上方淀积金属形成欧姆漏极15；
步骤5：在外延层11上通过离子注入形成N+阻挡区12、N+阻挡区12与积累漏极14保持间距，并外延层11左右两侧分别淀积金属，形成积累栅极8和积累漏极14；
步骤6：将欧姆栅极7与积累栅极8相连，形成栅极；将欧姆漏极15与积累漏极14相连，形成漏极；
步骤7：在器件表面形成钝化层。
经仿真试验，对于N沟道LDMOS，当漂移区长度为15μm时：如图3所示，普通LDMOS的比导通电阻为19.2mΩ.cm2左右，而本实施例的比导通电阻降低到2.6mΩ.cm2，下降了86％。如图4所示，普通LDMOS的击穿电压仅为210V左右，而本实施例可以将器件的击穿电压提高到360V，提高了71％；
当然，本发明中的LDMOS材料可以为硅材料也可以为宽带隙半导体材料，也可以为P沟道，其结构与N沟道LDMOS等同，在此不再赘述。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和替换，这些改进和替换的方案也落入本发明的保护范围。

Claims (10)

1.一种降低主结体电场的积累场效应晶体管，其特征在于，包括：
P型衬底(1)，P型衬底的底面设置有衬底电极(18)；
在P型衬底左上角区域形成的P型基区(2)，在P型基区中形成相应的沟道以及N+源区(5)和P+源区(3)；
在P型衬底右侧区域形成至少一个N型埋层(17)，所述N型埋层(17)水平方向上与P型基区(2)存在间隔，垂直方向上与积累介质层(10)存在间隔；
在P型衬底右上角区域形成N+漏区(16)；
源极(4)，位于P+源区(3)与N+源区(5)上方；
栅极介质层(6)，覆盖N+源区(5)右侧的沟道表面区域；
欧姆栅极(7)，覆盖所述栅极介质层(6)上；
欧姆漏极(15)，位于N+漏区(16)表面；
积累介质层(10)，位于P型衬底(1)上表面，且覆盖P型基区(2)与N+漏区(16)之间的区域；
外延层(11)，覆盖在所述积累介质层(10)上方；
积累栅极(8)和积累漏极(14)，分别位于外延层(11)的左端区域、右端区域；
N+阻挡层(12)位于外延层(11)的右侧，且与积累漏极(14)存在间隔；
所述欧姆栅极(7)与积累栅极(8)通过导线连接，整体作为器件的栅极；
所述欧姆漏极(15)与积累漏极(14)通过导线连接，整体作为器件的漏极。
2.根据权利要求1所述的降低主结体电场的积累场效应管，其特征在于：所述P型衬底(1)的掺杂浓度为1×1013cm-3～1×1015cm-3。
3.根据权利要求1所述的降低主结体电场的积累场效应管，其特征在于：所述N型埋层(17)的掺杂浓度为1×1015cm-3～1×1018cm-3；
当N型埋层(17)至少为两个时，每个N型埋层(17)互相之间存在垂直方向的间隔，每个N型埋层的水平方向为等长度设置或者不等长度设置；且在水平方向上最上方的N型埋层(17)的左侧不超过外延层(11)的左侧；
每个N型埋层垂直方向上为等间距布置或者不等间距布置；
最上方的N型埋层(17)与积累介质层(10)的间隔为1-8微米。
4.根据权利要求1所述的降低主结体电场的积累场效应管，其特征在于：所述积累介质层(10)的材料为绝缘材料；积累介质层(10)的厚度为0.03-0.2微米。
5.根据权利要求1所述的降低主结体电场的积累场效应管，其特征在于：所述外延层(11)分为掺杂型外延层和非掺杂型外延层两种，且均采用半导体材料制作，厚度为0.2～5微米；
掺杂型外延层(11)的掺杂浓度为1×1013cm-3～1×1015cm-3，其掺杂类型为N型掺杂或P型掺杂。
6.根据权利要求1所述的降低主结体电场的积累场效应管，其特征在于：所述积累栅极(8)和积累漏极(14)为欧姆接触或者肖特基接触。
7.根据权利要求1所述的降低主结体电场的积累场效应管，其特征在于：若积累栅极(8)和积累漏极(14)是欧姆接触，则通过离子注入的方式在外延层(11)的左侧与积累栅极(8)之间设置第一P型区(9)，同时以同样的方式在N+阻挡区(12)和积累漏极(14)之间设置第二P型区(13)。
8.根据权利要求1所述的降低主结体电场的积累场效应管，其特征在于：所述N+阻挡层(12)的掺杂浓度为1×1017cm-3～1×1019cm-3。
9.一种如权利要求1所述降低主结体电场的积累场效应管的制作方法，其特征在于，包括以下步骤：
步骤1：取P型衬底(1)，并在P型衬底(1)的底面形成衬底电极(18)；
步骤2：通过离子注入和扩散的方式在P型衬底(1)的左上角区域形成P型基区(2)、N+源区(5)和P+源区(3)，通过离子注入和扩散的方式在P型衬底(1)的右侧区域形成N型埋层(17)和N+漏区(16)；
步骤3：另选取外延层(11)材料，在其底面生长积累介质层(10)(10)，然后通过键合工艺与P型衬底(1)相连接；
步骤4：在N+源区(5)右侧的沟道表面区域形成栅介质层(6)，并在栅介质层(6)上方淀积金属形成欧姆栅极(7)；在N+源区(5)和P+源区(3)上方淀积金属形成源极(4)；在N+漏区(16)上方淀积金属形成欧姆漏极(15)；
步骤5：在外延层(11)上通过离子注入形成N+阻挡区(12)、N+阻挡区(12)与积累漏极(14)保持间距，并外延层(11)左右两侧分别淀积金属，形成积累栅极(8)和积累漏极(14)；
步骤6：将欧姆栅极(7)与积累栅极(8)相连，形成栅极；将欧姆漏极(15)与积累漏极(14)相连，形成漏极；
步骤7：在器件表面形成钝化层。
10.根据权利要求9所述的降低主结体电场的积累场效应管的制作方法，其特征在于：若积累栅极(8)和积累漏极(14)是欧姆接触，则执行步骤5时还需通过离子注入的方式在外延层(11)的左侧与积累栅极(8)之间设置第一P型区(9)，同时以同样的方式在N+阻挡区(12)和积累漏极(14)之间设置第二P型区(13)。
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