CN111725321B - 一种硅基肖特基积累层和缓冲层横向双扩散场效应晶体管及其制作方法 - Google Patents

一种硅基肖特基积累层和缓冲层横向双扩散场效应晶体管及其制作方法 Download PDF

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CN111725321B
CN111725321B CN202010699364.9A CN202010699364A CN111725321B CN 111725321 B CN111725321 B CN 111725321B CN 202010699364 A CN202010699364 A CN 202010699364A CN 111725321 B CN111725321 B CN 111725321B
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段宝兴
王彦东
杨银堂
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Xidian University
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Abstract

本发明公开一种硅基肖特基积累层和缓冲层横向双扩散场效应晶体管及其制作方法。该器件中设置积累介质层，覆盖P型基区与N+漏区之间的区域；设置硅材料的外延层覆盖所述积累介质层；肖特基栅极和肖特基漏极，分别位于外延层的左端侧面、右端侧面；欧姆栅极与肖特基栅极通过导线连接，整体作为器件的栅极；欧姆漏极与肖特基栅极通过导线连接，整体作为器件的漏极。肖特基积累层用于引入高浓度电子，使得导通不依赖掺杂浓度，大幅度降低器件的导通电阻；同时通过缓冲层调制漂移区的电场，使电场分布更均匀，可大幅度提高器件的击穿电压。

Description

一种硅基肖特基积累层和缓冲层横向双扩散场效应晶体管及 其制作方法
技术领域
本发明涉及半导体功率器件技术领域，具体涉及一种横向双扩散金属氧化物半导体场效应管。
背景技术
横向双扩散金属氧化物半导体场效应管(Lateral Double-diffused MOSFET，简称LDMOS)作为压控型多子导电器件，且源、栅、漏三个电极均位于器件表面，具有易驱动、易集成、频率好等优点，得到了广泛的应用。
LDMOS在横向上的耐压主要由轻掺杂的漂移区承担，为了实现更高的耐压，需降低漂移区的掺杂浓度或增加漂移区的横向长度。LDMOS导通时，漂移区电阻由漂移区掺杂浓度直接决定，故降低漂移区掺杂浓度会增加器件的导通电阻，而增加漂移区横向长度则会增加LDMOS器件所占用的芯片面积，两者均会导致比导通电阻的大幅度增加。因此，进行器件结构的优化设计，在提高器件耐压的同时，降低器件的比导通电阻，进而实现耐压与比导通电阻特性的良好折中，成为LDMOS器件研究的热点问题。
普通横向双扩散场效应晶体管中击穿电压和比导通电阻二者呈现矛盾关系，这是由于高的击穿电压需要低的掺杂浓度，而低的掺杂浓度会导致高的导通电阻。
发明内容
本发明提出了一种硅基肖特基积累层和缓冲层横向双扩散场效应晶体管，可获得更好的击穿电压与比导通电阻关系，大幅度提高器件的击穿电压并且降低导通电阻。
本发明的技术方案如下：
一种硅基肖特基积累层和缓冲层横向双扩散场效应晶体管，包括：
P型硅衬底，P型硅衬底的背面设置有衬底电极；
在P型硅衬底上部左端区域形成的P型基区，在P型基区中形成相应的沟道以及N+源区和P+源区；
在P型硅衬底上部右端区域形成的N型缓冲层，所述N型缓冲层与P型基区存在间隔；N型缓冲层的上部右端区域形成N+漏区；
源极，位于P+源区与N+源区上方；
栅极介质层，覆盖N+源区右侧的沟道表面区域；
欧姆栅极，覆盖所述栅极介质层；
欧姆漏极，位于N+漏区表面；
积累介质层，覆盖P型基区与N+漏区之间的区域；
外延层，覆盖所述积累介质层；
肖特基栅极和肖特基漏极，分别位于外延层的上表面左端区域、右端区域；
所述欧姆栅极与肖特基栅极通过导线连接，整体作为器件的栅极；
所述欧姆漏极与肖特基栅极通过导线连接，整体作为器件的漏极。
所述外延层中靠近肖特基漏极的区域通过离子注入形成N+区，所述N+区与肖特基漏极保持间距，积累介质层高于欧姆栅极和欧姆漏极。
上述外延层可以为N型，也可以为P型，可以轻掺杂或者不掺杂，其浓度低于N+区的掺杂浓度。外延层的材料可以是硅材料或多晶硅。
可选地，所述P型硅衬底的掺杂浓度为1×1014cm-3～1×1015cm-3，所述N型缓冲层的掺杂浓度为5×1014cm-3～5×1015cm-3。
可选地，所述N型缓冲层的长度为整个器件的1/2～1/3,深度为3-20微米。
可选地，所述积累介质层的材料为二氧化硅或高K材料。
可选地，所述积累介质层的厚度为0.05-0.2微米。
可选地，所述外延层的掺杂浓度为1×1014cm-3～1×1015cm-3，厚度为1～3微米。
可选地，所述肖特基栅极和肖特基漏极的接触势垒均为0.5-1eV(这两个接触势垒可以不相等)。
可选地，所述N+区与肖特基漏极之间的距离为0.5-2μm，N+区的左端不超出N型缓冲层左侧边界。
可选地，所述N+区的掺杂浓度为1×1017cm-3～1×1019cm-3。
上述硅基肖特基积累层和缓冲层横向双扩散场效应晶体管的一种制作方法，包括以下步骤：
1)取P型硅衬底，并形成衬底电极；
2)通过离子注入和扩散形成P型基区、N+源区和P+源区，通过离子注入和扩散形成N型缓冲层和N+漏区；
3)另选取1-3微米的外延层材料，在其底面生长积累氧化层，然后通过键合工艺与P型硅衬底以及N型缓冲层相连接；在外延层上通过离子注入形成N+区；
4)在沟道上方形成栅介质层，并淀积金属形成欧姆栅极；在N+源区和P+源区上方淀积金属形成源极；在N+漏区上方淀积金属形成欧姆漏极；
5)外延层上方两侧分别淀积金属，形成肖特基栅极和肖特基漏极；
6)将欧姆栅极与肖特基栅极相连，形成栅极；将欧姆漏极与肖特基漏极相连，形成漏极；
7)在器件表面形成钝化层。
本发明技术方案的有益效果如下：
从矛盾源头出发，提出将耐压区域与导通区域分离的思想，通过消除导通电阻对掺杂浓度的依赖关系，可获得更好的击穿电压与比导通电阻关系，大幅度提高器件的击穿电压并且降低导通电阻。
通过缓冲层调制漂移区的电场，使电场分布更均匀，提高器件的击穿电压；同时通过肖特基积累层结构产生的电子可调制电导率，消除了导通对掺杂浓度的依赖关系，可大幅度降低器件的比导通电阻。新结构突破了横向器件中弱化表面电场(Reduced SurfaceField，简称RESURF)条件的限制，从而可通过降低栅极和漏极之间的掺杂浓度而大幅度提高器件的击穿电压。
由于在器件开启时，会在氧化层下方形成电子，但同时会在氧化层上方形成等量的空穴，设置N+区可阻断氧化层上方外延层中的空穴电流。
附图说明
图1为本发明的一个实施例的结构示意图。
图2是本发明的工作原理示意图。
图3是本发明实施例与普通LDMOS的击穿电压的对照示意图。
图4是本发明实施例与普通LDMOS的比导通电阻的对照示意图。
附图标号说明：
1-P型硅衬底；2-P型基区；3-P+源区；4-源极；5-N+源区；6-栅介质层；7-欧姆栅极；8-肖特基栅极；9-积累介质层；10-外延层；11-N+区；12-肖特基漏极；13-欧姆漏极；14-N+漏区；15-N型缓冲层；16-衬底电极。
具体实施方式
以下结合附图，通过实施例进一步详述本发明。
如图1所示，该硅基肖特基积累层和缓冲层横向双扩散场效应晶体管，主要包括：
P型硅衬底1；掺杂浓度典型值为1×1014cm-3～1×1015cm-3；
P型硅衬底背面形成的衬底电极16；
在P型衬底上形成的P型基区2，基区的浓度由阈值电压决定，基区中形成相应的沟道以及N+源区5和P+源区3；
在P型衬底上形成的N型缓冲层15以及N+漏区14，缓冲层的掺杂浓度及深度由器件的耐压决定；掺杂浓度的典型值为5×1014cm-3～5×1015cm-3；N型缓冲层的长度为整个器件的1/2～1/3,深度为3-20微米；
在P+源区与N+源区的表面形成的源极；
在沟道上方形成的栅极介质层；
在P型基区与N+漏区之间形成的积累介质层，介质层的厚度由工艺决定，厚度越小导通电阻越低，厚度典型值为0.05-0.2微米；介质层材料可选择二氧化硅或高K材料；
在积累介质层上方形成的外延层10，外延层的厚度在1～3微米，掺杂浓度为1×1014cm-3～1×1015cm-3；
在外延层中靠近漏端通过离子注入形成N+区域11；N+区与肖特基漏极之间的距离为0.5-2μm，N+区的掺杂浓度为1×1017cm-3～1×1019cm-3；
肖特基栅极8和肖特基漏极12，分别位于外延层左、右两端侧面；肖特基栅极8和肖特基漏极12的接触势垒均为0.5-1eV；
欧姆栅极7，覆盖栅极氧化层；
欧姆漏极13，位于漏区上方；
欧姆栅极7与肖特基栅极8相连，作为器件的栅极；
欧姆漏极13与肖特基漏极12相连，作为器件的漏极。
如图2所示，该器件通过肖特基积累层结构引入高浓度电子可调制电导率，消除了导通对掺杂浓度的依赖关系，可大幅度降低器件的比导通电阻；缓冲层用于调制漂移区的电场，使电场分布更均匀，从而提高器件的击穿电压。新结构突破了横向器件中弱化表面电场(Reduced Surface Field，简称RESURF)条件的限制，从而可通过降低浓度而大幅度提高器件的击穿电压。
该器件可按照以下步骤制备：
1)取P型硅衬底，并形成衬底电极；
2)通过离子注入和扩散形成P型基区、N+源区和P+源区，通过离子注入和扩散形成N型缓冲层和N+漏区；
3)另选取1-3微米的外延层材料，在其底面生长积累氧化层，然后通过键合工艺与P型硅衬底以及N型缓冲层相连接；在外延层上通过离子注入形成N+区；
4)在沟道上方形成栅介质层，并淀积金属形成欧姆栅极；在N+源区和P+源区上方淀积金属形成源极；在N+漏区上方淀积金属形成欧姆漏极；
5)外延层左右两侧分别电淀积金属，形成肖特基栅极和肖特基漏极；
6)将欧姆栅极与肖特基栅极相连，形成栅极；将欧姆漏极与肖特基漏极相连，形成漏极；
7)在器件表面形成钝化层。
经仿真试验，对于N沟道LDMOS，当漂移区长度为20μm时：如图3所示，普通LDMOS的击穿电压仅为230V左右，而本实施例可以将器件的击穿电压提高到460V，提高了98％；如图4所示，普通LDMOS的比导通电阻为30mΩ.cm2左右，而本实施例的比导通电阻降低到5mΩ.cm2，下降了83％。
当然，本发明中的LDMOS也可以为P沟道，其结构与N沟道LDMOS等同，在此不再赘述。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和替换，这些改进和替换的方案也落入本发明的保护范围。

Claims (10)

1.一种硅基肖特基积累层和缓冲层横向双扩散场效应晶体管，其特征在于，包括：
P型硅衬底（1），P型硅衬底的背面设置有衬底电极（16）；
在P型硅衬底上部左端区域形成的P型基区（2），在P型基区中形成相应的沟道以及N+源区（5）和P+源区（3）；
在P型硅衬底上部右端区域形成的N型缓冲层（15），所述N型缓冲层（15）与P型基区（2）存在间隔；N型缓冲层（15）的上部右端区域形成N+漏区（14）；
源极（4），位于P+源区与N+源区上方；
栅极介质层（6），覆盖N+源区（5）右侧的沟道表面区域；
欧姆栅极（7），覆盖所述栅极介质层（6）；
欧姆漏极（13），位于N+漏区（14）表面；
积累介质层（9），覆盖P型基区（2）与N+漏区（14）之间的区域；
外延层（10），覆盖所述积累介质层（9）；
肖特基栅极（8）和肖特基漏极（12），分别位于外延层（10）的上表面左端区域、右端区域；
所述欧姆栅极（7）与肖特基栅极（8）通过导线连接，整体作为器件的栅极；
所述欧姆漏极（13）与肖特基漏极（12）通过导线连接，整体作为器件的漏极；
所述外延层（10）中靠近肖特基漏极（12）的区域通过离子注入形成N+区（11），所述N+区（11）与肖特基漏极（12）保持间距，积累介质层（9）高于欧姆栅极（7）和欧姆漏极（13）。
2.根据权利要求1所述的硅基肖特基积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述P型硅衬底（1）的掺杂浓度为1×1014cm-3~1×1015cm-3，所述N型缓冲层（15）的掺杂浓度为5×1014cm-3~5×1015cm-3。
3.根据权利要求1所述的硅基肖特基积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述N型缓冲层（15）的长度为整个器件的1/2~1/3, 深度为3-20微米。
4.根据权利要求1所述的硅基肖特基积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述积累介质层（9）的材料为二氧化硅或高K材料。
5.根据权利要求1所述的硅基肖特基积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述积累介质层（9）的厚度为0.05-0.2微米。
6.根据权利要求1所述的硅基肖特基积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述外延层（10）的掺杂浓度为1×1014cm-3~1×1015cm-3，厚度为1~3微米。
7.根据权利要求1所述的硅基肖特基积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述肖特基栅极（8）和肖特基漏极（12）的接触势垒均为0.5-1eV。
8.根据权利要求1所述的硅基肖特基积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述N+区（11）与肖特基漏极（12）之间的距离为0.5-2μm，N+区（11）的左端不超出N型缓冲层（15）左侧边界。
9.根据权利要求6所述的硅基肖特基积累层和缓冲层横向双扩散场效应晶体管，其特征在于：所述N+区（11）的掺杂浓度为1×1017cm-3~1×1019cm-3。
10.权利要求1所述硅基肖特基积累层和缓冲层横向双扩散场效应晶体管的制作方法，其特征在于，包括以下步骤：
1）取P型硅衬底，并形成衬底电极；
2）通过离子注入和扩散形成P型基区、N+源区和P+源区，通过离子注入和扩散形成N型缓冲层和N+漏区；
3）另选取1-3微米的外延层材料，在其底面生长积累氧化层，然后通过键合工艺与P型硅衬底以及N型缓冲层相连接；在外延层上通过离子注入形成N+区；
4）在沟道上方形成栅介质层，并淀积金属形成欧姆栅极；在N+源区和P+源区上方淀积金属形成源极；在N+漏区上方淀积金属形成欧姆漏极；
5）外延层上方两侧分别淀积金属，形成肖特基栅极和肖特基漏极；
6）将欧姆栅极与肖特基栅极相连，形成栅极；将欧姆漏极与肖特基漏极相连，形成漏极；
7）在器件表面形成钝化层。
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