CN1208949A - 用牺牲可流动氧化物双嵌埋形成多共面金属/绝缘膜的方法 - Google Patents
用牺牲可流动氧化物双嵌埋形成多共面金属/绝缘膜的方法 Download PDFInfo
- Publication number
- CN1208949A CN1208949A CN98115627A CN98115627A CN1208949A CN 1208949 A CN1208949 A CN 1208949A CN 98115627 A CN98115627 A CN 98115627A CN 98115627 A CN98115627 A CN 98115627A CN 1208949 A CN1208949 A CN 1208949A
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- China
- Prior art keywords
- corrosion
- flowable oxide
- groove
- break
- insulating material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 title claims abstract description 61
- 238000000034 method Methods 0.000 title claims abstract description 57
- 230000009977 dual effect Effects 0.000 title claims abstract description 19
- 239000002184 metal Substances 0.000 title description 41
- 239000012212 insulator Substances 0.000 title description 7
- 239000011810 insulating material Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 230000004888 barrier function Effects 0.000 claims description 72
- 238000005260 corrosion Methods 0.000 claims description 48
- 230000007797 corrosion Effects 0.000 claims description 48
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 239000003518 caustics Substances 0.000 claims description 8
- 238000003475 lamination Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000001020 plasma etching Methods 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- 238000004528 spin coating Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 abstract description 6
- 238000005516 engineering process Methods 0.000 description 20
- 239000004065 semiconductor Substances 0.000 description 18
- 239000007789 gas Substances 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 238000011017 operating method Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 239000003292 glue Substances 0.000 description 3
- 230000001788 irregular Effects 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
Abstract
Description
Claims (25)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US884,861 | 1997-06-30 | ||
US08/884,861 US6300235B1 (en) | 1997-06-30 | 1997-06-30 | Method of forming multi-level coplanar metal/insulator films using dual damascene with sacrificial flowable oxide |
US884861 | 1997-06-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1208949A true CN1208949A (zh) | 1999-02-24 |
CN1146956C CN1146956C (zh) | 2004-04-21 |
Family
ID=25385585
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB981156274A Expired - Fee Related CN1146956C (zh) | 1997-06-30 | 1998-06-30 | 用牺牲可流动氧化物双嵌埋形成多共面金属/绝缘膜的方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US6300235B1 (zh) |
EP (1) | EP0895283B1 (zh) |
JP (1) | JPH1187352A (zh) |
KR (1) | KR100494955B1 (zh) |
CN (1) | CN1146956C (zh) |
DE (1) | DE69837313T2 (zh) |
TW (1) | TW462112B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100463075C (zh) * | 2004-02-25 | 2009-02-18 | 国际商业机器公司 | 制作磁移位寄存器式存储器装置中使用的数据磁道的方法 |
CN102592989A (zh) * | 2011-01-07 | 2012-07-18 | 中国科学院微电子研究所 | 层间电介质的近界面平坦化回刻方法 |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6982475B1 (en) | 1998-03-20 | 2006-01-03 | Mcsp, Llc | Hermetic wafer scale integrated circuit structure |
US7205181B1 (en) | 1998-03-20 | 2007-04-17 | Mcsp, Llc | Method of forming hermetic wafer scale integrated circuit structure |
US7215025B1 (en) * | 1998-03-20 | 2007-05-08 | Mcsp, Llc | Wafer scale semiconductor structure |
JP3214475B2 (ja) * | 1998-12-21 | 2001-10-02 | 日本電気株式会社 | デュアルダマシン配線の形成方法 |
US6965165B2 (en) | 1998-12-21 | 2005-11-15 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
US6727143B1 (en) * | 1999-11-30 | 2004-04-27 | Advanced Micro Devices, Inc. | Method and system for reducing charge gain and charge loss when using an ARC layer in interlayer dielectric formation |
JP2001332621A (ja) * | 2000-03-13 | 2001-11-30 | Toshiba Corp | 半導体装置及びその製造方法 |
US6521542B1 (en) * | 2000-06-14 | 2003-02-18 | International Business Machines Corp. | Method for forming dual damascene structure |
US6576550B1 (en) * | 2000-06-30 | 2003-06-10 | Infineon, Ag | ‘Via first’ dual damascene process for copper metallization |
JP3704030B2 (ja) * | 2000-07-24 | 2005-10-05 | シャープ株式会社 | 半導体装置の製造方法 |
US6465358B1 (en) * | 2000-10-06 | 2002-10-15 | Intel Corporation | Post etch clean sequence for making a semiconductor device |
US6514860B1 (en) * | 2001-01-31 | 2003-02-04 | Advanced Micro Devices, Inc. | Integration of organic fill for dual damascene process |
US6372635B1 (en) | 2001-02-06 | 2002-04-16 | Advanced Micro Devices, Inc. | Method for making a slot via filled dual damascene low k interconnect structure without middle stop layer |
TW478133B (en) * | 2001-02-27 | 2002-03-01 | Nanya Technology Corp | Manufacturing method of the bit line contact plug of semiconductor memory cell |
KR100405934B1 (ko) * | 2001-12-26 | 2003-11-14 | 주식회사 하이닉스반도체 | 반도체 소자의 콘택홀 제조 방법 |
KR100428791B1 (ko) * | 2002-04-17 | 2004-04-28 | 삼성전자주식회사 | 저유전율 절연막을 이용한 듀얼 다마신 배선 형성방법 |
TW546771B (en) * | 2002-05-13 | 2003-08-11 | Nanya Technology Corp | Manufacturing method of dual damascene structure |
KR100454130B1 (ko) * | 2002-05-28 | 2004-10-26 | 삼성전자주식회사 | 저유전율 절연막을 이용한 듀얼 다마신 배선 형성방법 |
TW544857B (en) * | 2002-07-30 | 2003-08-01 | Promos Technologies Inc | Manufacturing method of dual damascene structure |
KR100442147B1 (ko) * | 2002-08-09 | 2004-07-27 | 동부전자 주식회사 | 이중 다마신 패턴 형성 방법 |
US7538025B2 (en) * | 2003-11-14 | 2009-05-26 | Taiwan Semiconductor Manufacturing Company | Dual damascene process flow for porous low-k materials |
KR100624098B1 (ko) | 2005-06-16 | 2006-09-15 | 삼성전자주식회사 | 박막 구조물 및 이의 형성 방법 |
KR100703560B1 (ko) * | 2005-12-28 | 2007-04-03 | 동부일렉트로닉스 주식회사 | 반도체 소자의 금속 배선 형성 방법 |
US8062971B2 (en) | 2008-03-19 | 2011-11-22 | Infineon Technologies Ag | Dual damascene process |
US7618874B1 (en) * | 2008-05-02 | 2009-11-17 | Micron Technology, Inc. | Methods of forming capacitors |
US7696056B2 (en) * | 2008-05-02 | 2010-04-13 | Micron Technology, Inc. | Methods of forming capacitors |
US8629037B2 (en) * | 2011-09-24 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming a protective film on a back side of a silicon wafer in a III-V family fabrication process |
CN108538839B (zh) * | 2017-03-01 | 2019-08-23 | 联华电子股份有限公司 | 半导体结构、用于存储器元件的半导体结构及其制作方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR940010197A (ko) | 1992-10-13 | 1994-05-24 | 김광호 | 반도체 장치의 제조방법 |
US5449644A (en) * | 1994-01-13 | 1995-09-12 | United Microelectronics Corporation | Process for contact hole formation using a sacrificial SOG layer |
JP3778299B2 (ja) | 1995-02-07 | 2006-05-24 | 東京エレクトロン株式会社 | プラズマエッチング方法 |
TW388083B (en) * | 1995-02-20 | 2000-04-21 | Hitachi Ltd | Resist pattern-forming method using anti-reflective layer, resist pattern formed, and method of etching using resist pattern and product formed |
US5614765A (en) * | 1995-06-07 | 1997-03-25 | Advanced Micro Devices, Inc. | Self aligned via dual damascene |
US5935877A (en) | 1995-09-01 | 1999-08-10 | Applied Materials, Inc. | Etch process for forming contacts over titanium silicide |
WO2000037086A1 (en) * | 1998-12-18 | 2000-06-29 | Scios Inc. | Agonists and antagonists of peripheral-type benzodiazepine receptors |
-
1997
- 1997-06-30 US US08/884,861 patent/US6300235B1/en not_active Expired - Lifetime
-
1998
- 1998-06-05 DE DE69837313T patent/DE69837313T2/de not_active Expired - Lifetime
- 1998-06-05 EP EP98110307A patent/EP0895283B1/en not_active Expired - Lifetime
- 1998-06-17 TW TW087109645A patent/TW462112B/zh not_active IP Right Cessation
- 1998-06-22 KR KR10-1998-0023337A patent/KR100494955B1/ko not_active IP Right Cessation
- 1998-06-30 CN CNB981156274A patent/CN1146956C/zh not_active Expired - Fee Related
- 1998-06-30 JP JP10184376A patent/JPH1187352A/ja active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100463075C (zh) * | 2004-02-25 | 2009-02-18 | 国际商业机器公司 | 制作磁移位寄存器式存储器装置中使用的数据磁道的方法 |
CN102592989A (zh) * | 2011-01-07 | 2012-07-18 | 中国科学院微电子研究所 | 层间电介质的近界面平坦化回刻方法 |
CN102592989B (zh) * | 2011-01-07 | 2015-04-08 | 中国科学院微电子研究所 | 层间电介质的近界面平坦化回刻方法 |
Also Published As
Publication number | Publication date |
---|---|
KR100494955B1 (ko) | 2005-09-09 |
EP0895283A2 (en) | 1999-02-03 |
EP0895283B1 (en) | 2007-03-14 |
JPH1187352A (ja) | 1999-03-30 |
DE69837313D1 (de) | 2007-04-26 |
KR19990007191A (ko) | 1999-01-25 |
EP0895283A3 (en) | 2000-05-03 |
CN1146956C (zh) | 2004-04-21 |
TW462112B (en) | 2001-11-01 |
US6300235B1 (en) | 2001-10-09 |
DE69837313T2 (de) | 2007-12-20 |
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Legal Events
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: INFINEON TECHNOLOGIES AG Free format text: FORMER OWNER: SIEMENS AKTIENGESELLSCHAFT Effective date: 20130225 |
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TR01 | Transfer of patent right |
Effective date of registration: 20130225 Address after: German Neubiberg Patentee after: Infineon Technologies AG Address before: Munich, Germany Patentee before: Siemens AG Effective date of registration: 20130225 Address after: Munich, Germany Patentee after: QIMONDA AG Address before: German Neubiberg Patentee before: Infineon Technologies AG |
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C41 | Transfer of patent application or patent right or utility model | ||
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Effective date of registration: 20151223 Address after: German Berg, Laura Ibiza Patentee after: Infineon Technologies AG Address before: Munich, Germany Patentee before: QIMONDA AG |
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