DE69837313D1 - Verfahren zur Herstellung von koplanaren Metal/isolierenden mehrlagigen Schichten unter Verwendung eines damaszenen Prozesses mit fliesfähiger Opferoxyd - Google Patents

Verfahren zur Herstellung von koplanaren Metal/isolierenden mehrlagigen Schichten unter Verwendung eines damaszenen Prozesses mit fliesfähiger Opferoxyd

Info

Publication number
DE69837313D1
DE69837313D1 DE69837313T DE69837313T DE69837313D1 DE 69837313 D1 DE69837313 D1 DE 69837313D1 DE 69837313 T DE69837313 T DE 69837313T DE 69837313 T DE69837313 T DE 69837313T DE 69837313 D1 DE69837313 D1 DE 69837313D1
Authority
DE
Germany
Prior art keywords
damascene
flow process
multilayer films
sacrificial oxide
oxide flow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69837313T
Other languages
English (en)
Other versions
DE69837313T2 (de
Inventor
Klaus Feldner
Virinder Grewal
Bernd Vollmer
Rainer Florian Schnabel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE69837313D1 publication Critical patent/DE69837313D1/de
Application granted granted Critical
Publication of DE69837313T2 publication Critical patent/DE69837313T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
DE69837313T 1997-06-30 1998-06-05 Verfahren zur Herstellung von koplanaren Metal/isolierenden mehrlagigen Schichten unter Verwendung eines damaszenen Prozesses mit fliesfähiger Opferoxyd Expired - Lifetime DE69837313T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/884,861 US6300235B1 (en) 1997-06-30 1997-06-30 Method of forming multi-level coplanar metal/insulator films using dual damascene with sacrificial flowable oxide
US884861 1997-06-30

Publications (2)

Publication Number Publication Date
DE69837313D1 true DE69837313D1 (de) 2007-04-26
DE69837313T2 DE69837313T2 (de) 2007-12-20

Family

ID=25385585

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69837313T Expired - Lifetime DE69837313T2 (de) 1997-06-30 1998-06-05 Verfahren zur Herstellung von koplanaren Metal/isolierenden mehrlagigen Schichten unter Verwendung eines damaszenen Prozesses mit fliesfähiger Opferoxyd

Country Status (7)

Country Link
US (1) US6300235B1 (de)
EP (1) EP0895283B1 (de)
JP (1) JPH1187352A (de)
KR (1) KR100494955B1 (de)
CN (1) CN1146956C (de)
DE (1) DE69837313T2 (de)
TW (1) TW462112B (de)

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US6982475B1 (en) 1998-03-20 2006-01-03 Mcsp, Llc Hermetic wafer scale integrated circuit structure
US7205181B1 (en) 1998-03-20 2007-04-17 Mcsp, Llc Method of forming hermetic wafer scale integrated circuit structure
US7215025B1 (en) * 1998-03-20 2007-05-08 Mcsp, Llc Wafer scale semiconductor structure
JP3214475B2 (ja) * 1998-12-21 2001-10-02 日本電気株式会社 デュアルダマシン配線の形成方法
US6965165B2 (en) 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US6727143B1 (en) * 1999-11-30 2004-04-27 Advanced Micro Devices, Inc. Method and system for reducing charge gain and charge loss when using an ARC layer in interlayer dielectric formation
JP2001332621A (ja) * 2000-03-13 2001-11-30 Toshiba Corp 半導体装置及びその製造方法
US6521542B1 (en) * 2000-06-14 2003-02-18 International Business Machines Corp. Method for forming dual damascene structure
US6576550B1 (en) * 2000-06-30 2003-06-10 Infineon, Ag ‘Via first’ dual damascene process for copper metallization
JP3704030B2 (ja) * 2000-07-24 2005-10-05 シャープ株式会社 半導体装置の製造方法
US6465358B1 (en) * 2000-10-06 2002-10-15 Intel Corporation Post etch clean sequence for making a semiconductor device
US6514860B1 (en) * 2001-01-31 2003-02-04 Advanced Micro Devices, Inc. Integration of organic fill for dual damascene process
US6372635B1 (en) 2001-02-06 2002-04-16 Advanced Micro Devices, Inc. Method for making a slot via filled dual damascene low k interconnect structure without middle stop layer
TW478133B (en) * 2001-02-27 2002-03-01 Nanya Technology Corp Manufacturing method of the bit line contact plug of semiconductor memory cell
KR100405934B1 (ko) * 2001-12-26 2003-11-14 주식회사 하이닉스반도체 반도체 소자의 콘택홀 제조 방법
KR100428791B1 (ko) * 2002-04-17 2004-04-28 삼성전자주식회사 저유전율 절연막을 이용한 듀얼 다마신 배선 형성방법
TW546771B (en) * 2002-05-13 2003-08-11 Nanya Technology Corp Manufacturing method of dual damascene structure
KR100454130B1 (ko) * 2002-05-28 2004-10-26 삼성전자주식회사 저유전율 절연막을 이용한 듀얼 다마신 배선 형성방법
TW544857B (en) * 2002-07-30 2003-08-01 Promos Technologies Inc Manufacturing method of dual damascene structure
KR100442147B1 (ko) * 2002-08-09 2004-07-27 동부전자 주식회사 이중 다마신 패턴 형성 방법
US7538025B2 (en) * 2003-11-14 2009-05-26 Taiwan Semiconductor Manufacturing Company Dual damascene process flow for porous low-k materials
US6955926B2 (en) * 2004-02-25 2005-10-18 International Business Machines Corporation Method of fabricating data tracks for use in a magnetic shift register memory device
KR100624098B1 (ko) 2005-06-16 2006-09-15 삼성전자주식회사 박막 구조물 및 이의 형성 방법
KR100703560B1 (ko) * 2005-12-28 2007-04-03 동부일렉트로닉스 주식회사 반도체 소자의 금속 배선 형성 방법
US8062971B2 (en) 2008-03-19 2011-11-22 Infineon Technologies Ag Dual damascene process
US7618874B1 (en) * 2008-05-02 2009-11-17 Micron Technology, Inc. Methods of forming capacitors
US7696056B2 (en) * 2008-05-02 2010-04-13 Micron Technology, Inc. Methods of forming capacitors
CN102592989B (zh) * 2011-01-07 2015-04-08 中国科学院微电子研究所 层间电介质的近界面平坦化回刻方法
US8629037B2 (en) * 2011-09-24 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Forming a protective film on a back side of a silicon wafer in a III-V family fabrication process
CN108538839B (zh) * 2017-03-01 2019-08-23 联华电子股份有限公司 半导体结构、用于存储器元件的半导体结构及其制作方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940010197A (ko) 1992-10-13 1994-05-24 김광호 반도체 장치의 제조방법
US5449644A (en) * 1994-01-13 1995-09-12 United Microelectronics Corporation Process for contact hole formation using a sacrificial SOG layer
JP3778299B2 (ja) 1995-02-07 2006-05-24 東京エレクトロン株式会社 プラズマエッチング方法
TW388083B (en) * 1995-02-20 2000-04-21 Hitachi Ltd Resist pattern-forming method using anti-reflective layer, resist pattern formed, and method of etching using resist pattern and product formed
US5614765A (en) * 1995-06-07 1997-03-25 Advanced Micro Devices, Inc. Self aligned via dual damascene
US5935877A (en) 1995-09-01 1999-08-10 Applied Materials, Inc. Etch process for forming contacts over titanium silicide
WO2000037086A1 (en) * 1998-12-18 2000-06-29 Scios Inc. Agonists and antagonists of peripheral-type benzodiazepine receptors

Also Published As

Publication number Publication date
KR100494955B1 (ko) 2005-09-09
EP0895283A2 (de) 1999-02-03
EP0895283B1 (de) 2007-03-14
JPH1187352A (ja) 1999-03-30
CN1208949A (zh) 1999-02-24
KR19990007191A (ko) 1999-01-25
EP0895283A3 (de) 2000-05-03
CN1146956C (zh) 2004-04-21
TW462112B (en) 2001-11-01
US6300235B1 (en) 2001-10-09
DE69837313T2 (de) 2007-12-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE