CN1198013A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN1198013A CN1198013A CN98106629A CN98106629A CN1198013A CN 1198013 A CN1198013 A CN 1198013A CN 98106629 A CN98106629 A CN 98106629A CN 98106629 A CN98106629 A CN 98106629A CN 1198013 A CN1198013 A CN 1198013A
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- electrode
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 142
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229920005989 resin Polymers 0.000 claims abstract description 47
- 239000011347 resin Substances 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims description 24
- 241000218202 Coptis Species 0.000 claims description 19
- 235000002991 Coptis groenlandica Nutrition 0.000 claims description 19
- 238000010438 heat treatment Methods 0.000 claims description 11
- 239000007769 metal material Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 6
- 230000009477 glass transition Effects 0.000 claims description 4
- 238000009434 installation Methods 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000008188 pellet Substances 0.000 abstract 3
- 235000012431 wafers Nutrition 0.000 description 61
- 239000000758 substrate Substances 0.000 description 14
- 229910052737 gold Inorganic materials 0.000 description 12
- 239000010931 gold Substances 0.000 description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 239000011889 copper foil Substances 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 5
- 230000003321 amplification Effects 0.000 description 4
- 230000008602 contraction Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000007747 plating Methods 0.000 description 3
- 229910000906 Bronze Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000010974 bronze Substances 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 150000002343 gold Chemical class 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000013138 pruning Methods 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
- 230000014616 translation Effects 0.000 description 1
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Abstract
本发明提供了一种半导体器件,它包括:一个在其表面具有若干个突出电极的半导体晶片;一个在其表面具有若干焊盘电极的布线板,当布线板与半导体晶片连接时每一个焊盘电极与相应的一个突出电极啮合;和一个夹在半导体晶片与布线板之间的使其相互连接的树脂层,每个突出电极与突出部和突出部能够装入的凹槽的一个一同形成,每个焊盘电极和另一个一同形成。这样,即使树脂层断裂使突出和焊盘电极之间的啮合减弱,也能确保两个电极之间的良好的电连接。
Description
本发明涉及一种具有倒装晶片的半导体器件,一种制造该器件的方法,一种用于该器件的布线板。
为了制造更小尺寸的电子器件,电子元件被制造得越来越小,而且保持了其高性能和高集成度。
半导体器件(电子器件的一种)通常用树脂封装。然而,目前,一种裸芯片(未用树脂封装的芯片)被直接加入布线板中,以便制造更小尺寸的半导体芯片。
使用裸芯片的半导体器件的实例之一在图1中示出。所示的半导体器件包括一个半导体晶片1,一个连接半导体晶片1的布线板5,和一个夹在半导体晶片1与布线板5之间以加强其结合的树脂层8。
半导体晶片1包括:一个半导体基片2,它包含若干个互连的(从而)构成电子线路的半导体元件(未示出);一个在半导体基片2的主表面形成的绝缘膜(未示出);在绝缘膜被部分清除的区域形成的并与半导体元件电连接的底电极3;和在底电极3上形成的突出电极4。底电极3通常由铝制成。突出电极4采用电镀、蒸发等手段通过金粉层的淀积形成;或者通过球焊方法形成。这种球焊方法是:金线在电极的端点处熔化以形成金球,该金球在具有表面张力的端点的电极上被压扁,然后削去金线,使被压扁的金球留在该电极上。
布线板5包括:一个由绝缘材料(如树脂和陶瓷)制成的绝缘基片6;和一个在绝缘基片6上形成的焊盘电极7,该电极7面向在半导体基片2上形成的突出电极4。焊盘电极7与导电图案(未示出)电连接。所述的导电图案用保护膜(未示出)覆盖以便向外暴露所需的区段,并与其它电子元件和/或外部连接端电连接以构成电子线路。导电图案通常通过蚀刻绝缘基片6上淀积的铜箔来形成。焊盘电极7用镍电镀以防止铜箔腐蚀,然后再用金粉电镀以增强与导电图案的电连接。
半导体晶片1和布线板5经树脂层8相互连接。首先,把半导体晶片1和布线板5重叠在一起,使突出电极4和焊盘电极7相互啮合。然后,对半导体晶片1和布线板5加压,使突出电极4塑性变形。随后把树脂灌入半导体晶片1与布线板5之间的空隙中。因此半导体晶片1和布线板5处在树脂凝固时出现树脂层8的收缩造成的压力下。树脂层8可以在半导体晶片1和布线板5重叠前在布线板5上形成,或者可以在半导体晶片1和布线板5重叠后通过在它们之间灌入树脂来形成。在半导体晶片1和布线板5处在压力的条件下,半导体晶片1或布线板5以约200℃的温度加热几分钟,以促使树脂层8凝固。
在所述的半导体器件中,由于半导体晶片1是裸露的(即,未用树脂完全封装),因此,从绝缘基片6表面到半导体晶片1上表面的高度可以保持在100μm以内,从而满足了制造更小尺寸的半导体器件的要求。
日本待审专利公报第5-166881提出了一种与上述器件相似的半导体器件。在该半导体器件中,在半导体晶片上用金球焊接方法形成突出电极,焊盘电极经低熔点的焊料与突出电极连接。即,半导体晶片与布线板机械或电连接,而且不需要像图1所示的树脂层8那样的树脂层。
日本待审专利公报第7-153796提出了一种半导体器件,该器件包含一个在半导体基片上用金球焊接方法形成的突出电极;和一个在布线板上形成的焊盘电极,焊盘电极用具有向开口方向减小其直径的接触孔形成。突出电极部分插入焊盘电极之后,突出电极变形,从而使突出电极固定在孔中。
在图1所示的和上述日本待审专利公报提出的半导体器件中,由于在半导体器件工作时半导体器件产生的热量和/或外部传递的热,因而使半导体晶片和布线板热膨胀。因此,如果在半导体晶片与布线板之间存在很大的热膨胀系数差值,则在相互紧密联接的突出和焊盘电极中产生应力。
在上述第一个日本未审查专利公报中提出的半导体器件中,突出和焊盘电极借助低熔点的焊料被牢固地相互联接在一起。因此,如果因半导体晶片与布线板间的热膨胀系数的差值产生的应力集中在半导体晶片和布线板的接触部位上,则焊料可能断裂,从而导致这两个电极之间电接触性能的降低。
在上述第二个日本待审专利公报中提出的半导体器件中,突出电极被部分地插入焊盘电极的‘倒锥形’的接触孔中,然后使突出电极变形,从而用突出电极填充接触孔,这样就能保证半导体晶片与布线板间的电和机械牢固连接。然而,即使突出电极与焊盘电极被牢固连接,但如果因半导体晶片与布线板间的热膨胀系数的差值产生的应力集中在半导体晶片的接触部位上,则突出电极也许会从半导体基片上脱落。因而,它不能完全防止半导体晶片与布线板之间电接触性能的降低。
上述的热膨胀和热收缩发生在每次半导体器件开始和结束其工作。因此,由半导体晶片与布线板之间热膨胀系数差值造成的上述问题是频繁重复开始和停止工作的电子器件的严重问题。
反之,在图1所示的半导体器件中,树脂层8使半导体晶片1的整个表面与布线板5连接,所以,半导体晶片1与布线板5之间热膨胀系数差值造成的应力被分散,从而能够避免应力集中在突出电极4与焊盘电极7之间的接触部位上。此外,由于突出电极4和焊盘电极7在压力下相互电连接,因此即使产生上述应力,突出电极4和焊盘电极7也处在压力下,使电极4和7的接触部位与半导体晶片2和绝缘基片6平行位移,从而减轻了应力。因而,半导体晶片1与布线板5之间的电连接性能不会降低。
然而,图1所示的半导体器件存在以下问题:如果树脂层8从基片2和6上脱落,或因基片2和6的热膨胀和收缩产生的应力使树脂层8断裂,则电极4和7在(借助树脂层8保持的)压力下使相互联结的条件破坏,因而电极4和7之间的压力明显减小,从而电极4和7之间的电连接不可靠。
本发明的目的是提供一种半导体器件和其制造方法,即使保持半导体晶片与布线板受压连接的树脂层已经断裂,它们也能够保持半导体晶片与布线板之间充分的电连接。
一个方面,本发明提供了一种半导体器件,该器件包含:一个在其表面上具有若干个突出电极的半导体晶片;一个在其表面上具有若干焊盘电极的布线板,当布线板与半导体晶片连接时每一个焊盘电极与相应的一个突出电极啮合;和一个夹在半导体晶片与布线板之间的使其相互连接的树脂层,其特征在于每个突出电极与突出部和适于突出部安装或插入的凹槽或通孔的一个一同形成,焊盘电极与另一个一同形成。
例如,突出电极可以通过把金线端部形成的熔化球挤压在半导体晶片上形成,当突出部在突出电极上形成时,突出部可以用当金线被切割时留在突出电极上的金线端部和从金线端部伸出的一小段线形成。
凹槽或通孔具有一个用于加强突出部与凹槽或通孔之间啮合的变形部分。该变形部分在突出部装入凹槽或插入通孔后形成。
半导体器件可以进一步包含一个在凹槽或通孔的内表面上形成的加强层。加强层最好由比制造突出电极或焊盘电极的材料硬的金属材料制成,该加强层和凹槽或通孔一起形成。加强层可以由若干个层组成,在这种情况下,最好若干层中的至少最内层由比制造突出电极或焊盘电极的材料硬的金属材料制成,其若干层的一个与凹槽或通孔一同形成。
所有突出电极或焊盘电极中的突出部最好具有相同高度。
另一方面,本发明提供了制造半导体器件的方法,该方法包括以下步骤:在半导体晶片的表面上形成若干个突出电极,每个突出电极与突出部和适于突出部安装或插入的凹槽或通孔的一个一同形成;在布线板上形成若干个焊盘电极,当布线板与半导体晶片啮合时每个焊盘电极与相关的一个突出电极啮合,每个焊盘电极与突出部和凹槽或通孔的另一个一起形成,连接半导体晶片和布线板以使突出部装入或插入凹槽或通孔中;和在半导体晶片与布线板之间形成树脂层。
上述方法最好进一步包括挤压已相互啮合的突出部和凹槽或通孔以加强两者间连接的步骤。上述方法最好进一步包括加热树脂层的步骤,以凝固树脂层和进一步轴向热扩展突出部,在这种情况下,最好以比布线板的玻璃转换(glass-transition)温度高的温度加热树脂层。
例如,凹槽或通孔可以通过发射激光束形成。另一方面,凹槽或通孔可以通过用保护膜覆盖突出或焊盘电极,并穿过保护膜发射激光束来形成。还可以通过蚀刻形成凹槽或通孔。
上述方法可以进一步包括在凹槽或通孔的内表面上形成加强层的步骤。加强层最好用比制造突出电极或焊盘电极的材料硬的金属材料制成,该加强层和凹槽或通孔一起形成。加强层可以由若干个层组成,在这种情况下,若干个层中的至少最内层用金属材料制成。
再一方面,本发明提供一种用夹在其间的树脂层连接半导体晶片的布线板,该布线板具有若干个在其表面上的焊盘电极,当布线板与半导体晶片连接时焊盘电极的每一个与相应的一个在半导体晶片表面上形成的突出电极啮合,其特征在于每个焊盘电极与适于每个突出电极上形成的突出部装入的凹槽和通孔中的一个一同形成。
凹槽或通孔最好具有一个变形部,以增强突出部与凹槽或通孔之间的啮合。变形部在突出部装入凹槽或通孔后形成。
根据上述的半导体器件或方法,即使(用于保持半导体晶片与布线板相互连接和用于保持突出电极和焊盘电极受压相互啮合的)树脂层破裂从而削弱突出电极与焊盘电极之间的啮合,也能确保两个电极之间良好的电连接。这样,提供了高可靠性的半导体器件。
图1是现有半导体器件的剖视图;
图2是根据本发明第一实施例的半导体器件的剖视图;
图3是图2所示的半导体器件使用的布线板的局部放大剖视图;
图4是图2所示的半导体器件的局部放大剖视图;
图5是根据本发明第二实施例的半导体器件的剖视图;
图6是图5所示的半导体器件使用的布线板的局部放大剖视图;
图7是图5所示的半导体器件的局部放大剖视图。
(第一实施例)
图2至图4示出了本发明第一实施例的半导体器件。参见图2,所示的半导体器件包括:一个半导体晶片9,一个与半导体晶片9联结的布线板13,和一个夹在半导体晶片9与布线板13之间的用于增强其啮合的树脂层18。
半导体晶片9由半导体基片10;一个在半导体基片10的主表面上形成的绝缘膜(未示出);在绝缘膜部分被清除的区域形成的底电极11,该区域与半导体元件实现电连接;和在底电极11上形成的突出电极12组成,基片10含有若干个互连的半导体元件(未示出)以构成电子电路。所述的底电极由铝制成。
在本实施例中,每个突出电极12由塌陷球或电极本体12a和从塌陷球12a伸出的突出部12b组成。突出电极12的塌陷球12a和突出部12b是这样形成的:熔化金线的端部以形成金球,再把形成的金球挤压到底电极11上以压扁金球,然后切除金线,使压扁的金球和从压扁的金球延伸的金线的一小段留在底电极11上。
如果使用的金线的直径为25μm,则塌陷球12a应该具有约80μm的直径和约25μm的高度,突出部12b应该是具有约25μm直径和距底电极11约为70μm高度的旋转抛物体。
布线板13由一个环氧树脂制成的多层绝缘基片14,和一个在绝缘基片14上形成的导电图案(未示出)组成。导电图案的一部分面向突出电极12设置,从而构成焊盘电极15。导电图案通过蚀刻(例如)18μm厚的铜箔来形成,然后用保护膜覆盖,该保护膜被部分去除(清除)以向外暴露焊盘电极15。
如图3所示,每一个焊盘电极15与贯穿其深度的通孔15a一起形成。通孔15a被设计成恰好能容纳突出电极12的突出部12b。通孔15a按如下方式形成:首先,铜箔被粘附到绝缘基片14的表面。然后,在铜箔上形成第一光刻胶膜,再以预定图案暴光。然后,蚀刻已经暴光的铜箔部分(以便去除),从而形成预定的铜图案。然后清除第一光刻胶膜。再在构图铜箔上形成第二光刻胶膜,其图案是使要形成焊盘电极15的区域被暴光的图案。然后暴光第二光刻胶膜,以进行处理。再向上述区域发射激光束,从而形成了通孔15a。形成的通孔15a具有约30μm的直径和约22μm的深度,并延伸到整个焊盘电极15。当焊盘电极15a用镍和金层16a和16b电镀后(如下所述),通孔15a的直径降到约24μm。
如图3所示,焊盘电极15包括通孔15a内表面的整个表面被约3μm厚的镍层16a和约0.05μm厚的金层16b覆盖。由于镍比制造焊盘电极15的铜硬,因此,镍层16a作为加强层17以加强通孔15a。
树脂18被注入焊盘电极15周围的区域,然后面向布线板13设置半导体晶片9,再把突出电极12的突出部12b插入焊盘电极15的通孔15a中。然后,挤压半导体晶片9和布线板13,使它们更牢固地联接。
接着,以约200℃的温度加热半导体器件,以便凝固树脂18。所以,具有旋转抛物体的突出部12b沿通孔15a膨胀,使突出部12b在底端穿入加热软化的绝缘基片14。突出部12b的中间部分被轴向挤压而膨胀,从而使突出部12b的外表面与通孔15a的内表面紧密接触。
由于通孔15a的内表面被加强层17覆盖,因此通孔15a的内表面不随突出部12b的热膨胀而膨胀。因此,突出部12b和通孔15a相互处于塑性变形状态此时位于焊盘电极15的塌陷球12a可靠联结。当这种状态保持时,树脂18凝固。因此,突出电极12和焊盘电极15处在树脂18收缩的压力下。从而得到了图2所示的半导体器件。
根据上述的半导体器件,突出部12b与通孔15a啮合,突出部12b与通孔15a的啮合保证了塌陷球12a与焊盘电极15的更可靠电连接。此外,当为加速树脂层18凝固而加热半导体晶片9时,热从半导体基片10传递给突出电极12,并被集中在电极12与15之间的接触部位上和突出部12b与通孔15a之间的接触部位上。
加热半导体晶片9的温度是这样分配的:使加热树脂18的温度高于布线板13的绝缘基片14的玻璃转换温度。制造绝缘基片14的环氧树脂具有120℃至170℃的玻璃转换温度。这样,在本实施例中,加热半导体晶片9的温度为200℃。由于以200℃的温度加热半导体晶片9和挤压半导体晶片120秒钟,因此焊盘电极15被局部软化,因而在通孔15a的周围使焊盘电极15下陷几微米至20微米并从而造成变形(如图4所示)。
如果半导体晶片9被加热和挤压一定的时间,那么即使停止加热和挤压半导体晶片9后焊盘电极15也会保留其变形。如图4所示,焊盘电极15的变形导致通孔15a的开口直径变窄,因此通孔15a内表面的拐角渗入突出部12b。所以,突出部12b和通孔15a更紧密地啮合。因此,即使突出电极15与塌陷球12a的电连接(由半导体晶片9对布线板13的挤压导致的)因树脂层18断裂而变坏,但是由于突出部12b与通孔15a紧密啮合,因而维持了电极12与15之间良好的电连接。
因此,第一实施例的半导体器件适用于起动和停止频繁重复的电子器件,或者适用于在周围温度变化大,导致半导体器件的元件明显热膨胀和收缩的环境中使用的电子器件。
本发明的范围不限于上述的实施例。例如,切除金线形成的突出部12b后,借助平面平板夹具修平使突出部12b的高度一致,可将其修平。
此外,突出电极12可通过电镀或蒸发以及球焊等方法形成,在这种情况下突出部12b可以被设计成具有预期的截面和/或预期的外形(sidesilhouette)。另外,通孔15a可以通过蚀刻以及发射激光束形成,因而可以被设计成具有与突出部12b的截面相配合(一致)的预期截面。
在第一实施例中,本发明适用于所有的突出电极12,然而,应该注意的是:由于半导体器件的热膨胀和收缩,因此本发明仅适用于承受极大应力的突出电极和相关的焊盘电极。
用于树脂18凝固的时间直接取决于树脂18被加热的温度。因此,可以使用在较短时间凝固的树脂。另一方面,还可以使用由紫外线凝固的树脂,以节省凝固树脂的时间。还能够在较短的时间里以高于200℃的温度加热树脂18。第二实施例
图5至图7示出了根据第二实施例的半导体器件。参见图5,所示的半导体器件包括一个半导体晶片9,一个要与半导体晶片9联结的布线板13,和一个夹在半导体晶片9与布线板13之间用于加强其啮合的树脂层18。
第二实施例的半导体器件几乎与图2至图4所示的第一实施例的器件相同,它与第一实施例的区别仅在于第二实施例的每个焊盘电极15与替代第一实施例通孔15a的凹槽15b一起形成。凹槽15b被设计成具有比焊盘电极15的厚度小的深度。凹槽15b提供了与由通孔15a得到的优点相同的优点。
Claims (25)
1.一种半导体器件,包括:(a)一个在其表面上具有若干个突出电极的半导体晶片;(b)一个在其表面上具有若干焊盘电极的布线板,当所述的布线板与所述的半导体晶片连接时每一个所述的焊盘电极与相应的一个所述的突出电极啮合;和(c)一个夹在所述的半导体晶片与所述的布线板之间的使其相互连接的树脂层,其特征在于
每个所述的突出电极与突出部和适于突出部安装的凹槽或通孔的一个一同形成,所述的焊盘电极和另一个一同形成。
2.根据权利要求1所述的半导体器件,其特征在于所述的突出电极通过把金线端部形成的熔化球挤压在所述的半导体晶片上形成,所述的突出部在所述的突出电极上形成,所述的突出部包括所述的金线被切割时留在所述的突出电极上的所述金线的端部和从所术金线的所述端部伸出的一小段线。
3.根据权利要求1所述的半导体器件,其特征在于所述的凹槽或通孔具有一个用于加强所述的突出部与所述的凹槽或通孔之间啮合的变形部分,所述的变形部分在所述的突出部装入所述的凹槽或通孔后形成。
4.根据权利要求1至3任一项所述的半导体器件,进一步包括一个在所述的凹槽或通孔的内表面上形成的加强层。
5.根据权利要求4所述的半导体器件,其特征在于所述的加强层由比制造所述的突出电极或所述的焊盘电极的材料硬的金属材料制成,所述的加强层和凹槽或通孔一起形成。
6.根据权利要求4所述的半导体器件,其特征在于所述的加强层由若干个层组成。
7.根据权利要求6所述的半导体器件,其特征在于至少所述的若干层的最内层由比制造所述的突出电极或所述的焊盘电极的材料硬的金属材料制成,其若干层的一个与凹槽或通孔一同形成。
8.一种制造半导体器件的方法,包括以下步骤:
(a)在半导体晶片的表面上形成若干个突出电极,每个所述的突出电极与突出部和突出部能够装入的凹槽或通孔的一个一同形成;
(b)在布线板上形成若干个焊盘电极,当所述的布线板与所述的半导体晶片啮合时每个所述的焊盘电极与相关的一个所述的突出电极啮合,每个所述的焊盘电极与突出部和凹槽或通孔的另一个一起形成;
(c)连接所述的半导体晶片和所述的布线板以使所述的突出部装入所述的凹槽或通孔中;和
(d)在所述的半导体晶片与所述的布线板之间形成树脂层。
9.根据权利要求8所述的方法,其特征在于在所述步骤(a)中通过把在金线端部形成的熔化球挤压到所述的半导体晶片上形成突出电极,通过切割所述的金线,使所述的金线的端部和从金线端部伸出的一小段线留在所述的突出电极上在所述的突出电极上形成所述的突出部。
10.根据权利要求8所述的方法,进一步包括挤压相互啮合的所述的突出部和所述的凹槽或通孔以加强其啮合的步骤。
11.根据权利要求8至10的任一项所述的方法,进一步包括用于凝固所述的树脂层从而轴向热膨胀所述的突出部的加热所述的树脂层的步骤。
12.根据权利要求11所述的方法,其特征在于以比所述的布线板的玻璃转换(glass-transition)温度高的温度加热所述的树脂层。
13.根据权利要求8至10的任一项所述的方法,其特征在于所述的凹槽或通孔通过发射激光束形成。
14.根据权利要求8至10的任一项所述的方法,其特征在于所述的凹槽或通孔通过用保护膜覆盖所述的突出或焊盘电极并发射穿过所述的保护膜的激光束来形成。
15.根据权利要求8至10的任一项所述的方法,其特征在于所述的凹槽或通孔通过蚀刻形成。
16.根据权利要求8至10的任一项所述的方法,进一步包括在所述的凹槽或通孔的内表面上形成加强层的步骤。
17.根据权利要求16所述的方法,其特征在于所述的加强层用比制造所述的突出电极或所述的焊盘电极的材料硬的金属材料制成,所述的加强层与所述的凹槽或通孔一起形成。
18.根据权利要求16所述的方法,其特征在于所述的加强层由若干个层组成。
19.根据权利要求18所述的方法,其特征在于至少所述若干层的最内层用比制造所述的突出电极或所述的焊盘电极的材料硬的金属材料制成,所述的最内层与所述的凹槽或通孔一起形成。
20.一种用夹在其间的树脂层与半导体晶片连接的布线板,所述的布线板具有若干个在其表面上的焊盘电极,当所述的布线板与所述的半导体晶片连接时每个所述的焊盘电极与在所述的半导体晶片的表面上形成的相关的一个突出电极啮合,其特征在于
每个所述的焊盘电极与每个突出电极上形成的突出部能够装入的凹槽和通孔的一个一同形成。
21.根据权利要求20所述的布线板,其特征在于所述的凹槽或通孔具有一个用于加强所述的突出部与所述的凹槽或通孔之间啮合的变形部分,所述的变形部分在所述的突出部装入所述的凹槽或通孔后形成。
22.根据权利要求20或21所述的布线板,进一步包括一个在所述的凹槽或通孔的内表面上形成的加强层。
23.根据权利要求22所述的布线板,其特征在于所述的加强层由比制造所述的焊盘电极的材料硬的金属材料制成。
24.根据权利要求22所述的布线板,其特征在于所述的加强层由若干个层组成。
25.根据权利要求24所述的半导体器件,其特征在于至少所述的若干层的最内层由比制造所述的焊盘电极的材料硬的金属材料制成。
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JPH08236654A (ja) * | 1995-02-23 | 1996-09-13 | Matsushita Electric Ind Co Ltd | チップキャリアとその製造方法 |
US5742100A (en) * | 1995-03-27 | 1998-04-21 | Motorola, Inc. | Structure having flip-chip connected substrates |
-
1997
- 1997-02-21 JP JP9037476A patent/JPH10233413A/ja active Pending
-
1998
- 1998-02-13 US US09/023,432 patent/US6194781B1/en not_active Expired - Fee Related
- 1998-02-21 CN CN98106629A patent/CN1100349C/zh not_active Expired - Fee Related
-
2000
- 2000-09-18 US US09/663,776 patent/US6433426B1/en not_active Expired - Fee Related
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
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CN101131983B (zh) * | 2006-08-24 | 2010-12-01 | 日立电线株式会社 | 连接体和光发送接收模块 |
US8027553B2 (en) | 2006-08-24 | 2011-09-27 | Hitachi Cable, Ltd. | Connected body and optical transceiver module |
CN101261972B (zh) * | 2007-02-16 | 2011-04-20 | 泰科电子公司 | 具有触点定位特性的焊盘栅格阵列模块 |
CN101628705B (zh) * | 2008-07-14 | 2012-10-31 | 欧姆龙株式会社 | 基板接合方法和电子部件 |
CN102364650A (zh) * | 2010-06-15 | 2012-02-29 | 富士通株式会社 | 固体电解电容器及电源电路 |
CN102332435A (zh) * | 2010-07-13 | 2012-01-25 | 台湾积体电路制造股份有限公司 | 电子元件及其制作方法 |
CN102332435B (zh) * | 2010-07-13 | 2013-09-18 | 台湾积体电路制造股份有限公司 | 电子元件及其制作方法 |
CN104401929A (zh) * | 2014-11-20 | 2015-03-11 | 上海华虹宏力半导体制造有限公司 | 用于融合键合晶片的键合结构及锚点结构 |
CN104401929B (zh) * | 2014-11-20 | 2016-05-11 | 上海华虹宏力半导体制造有限公司 | 用于融合键合晶片的键合结构及锚点结构 |
Also Published As
Publication number | Publication date |
---|---|
CN1100349C (zh) | 2003-01-29 |
US6433426B1 (en) | 2002-08-13 |
JPH10233413A (ja) | 1998-09-02 |
US6194781B1 (en) | 2001-02-27 |
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