CN1159077A - 通过容纳焊膏堆积使衬底隆起的方法 - Google Patents

通过容纳焊膏堆积使衬底隆起的方法 Download PDF

Info

Publication number
CN1159077A
CN1159077A CN95116346A CN95116346A CN1159077A CN 1159077 A CN1159077 A CN 1159077A CN 95116346 A CN95116346 A CN 95116346A CN 95116346 A CN95116346 A CN 95116346A CN 1159077 A CN1159077 A CN 1159077A
Authority
CN
China
Prior art keywords
mask
substrate
soldering paste
metal
bulge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN95116346A
Other languages
English (en)
Other versions
CN1083155C (zh
Inventor
M·K·施韦伯特
D·T·坎贝尔
M·海丁格
R·E·克拉夫特
H·A·范德普拉斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of CN1159077A publication Critical patent/CN1159077A/zh
Application granted granted Critical
Publication of CN1083155C publication Critical patent/CN1083155C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3485—Applying solder paste, slurry or powder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11005—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for aligning the bump connector, e.g. marks, spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11332—Manufacturing methods by local deposition of the material of the bump connector in solid form using a powder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705—Shape
    • H01L2224/17051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/742—Apparatus for manufacturing bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00015—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10568—Integral adaptations of a component or an auxiliary PCB for mounting, e.g. integral spacer element
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2036—Permanent spacer or stand-off in a printed circuit or printed circuit assembly
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0568—Resist used for applying paste, ink or powder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0756—Uses of liquids, e.g. rinsing, coating, dissolving
    • H05K2203/0769—Dissolving insulating materials, e.g. coatings, not used for developing resist after exposure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1216—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by screen printing or stencil printing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

把焊料隆起物通过模版印刷到衬底上，提供间距小于400微米的隆起的衬底。通过模版/掩摸和焊膏法施加焊料，但在回流时掩模仍附着于衬底。通过本发明也可获得大于400微米的间距。本发明还提供了生产体积均匀且可控制的金属球的方法。

Description

通过容纳焊膏堆积使衬底隆起的方法
本发明涉及把导电物质附着于衬底的方法和工艺，更具体地，涉及把焊料隆起物附着于衬底的工艺，在要求间距小于400微米的应用中具有特殊的优点。
对于以低成本大批量地制造和组装集成电路或“芯片”的方法，在世界范围内的持久研究，花费了大量的研究和开发资源。芯片组装的集成片要制成电气互连。焊料隆起的倒装式技术已成为非常流行的了，这是因为它提供了所有的接线端均在一侧(以焊盘或隆起物的形式)的超小型半导体管芯，对芯片表面处理之后，可把其翻转并附着于装配衬底。为了构成连接，倒装式技术包括使导电材料的隆起物固定于包括电路板、封壳和芯片的衬底上的技术。倒装芯片隆起技术还被证实适用于带自动压焊(TAB)。焊料隆起物的其它应用包括光—电子和硅—硅互连。
倒装片技术具有多种优点，使其成为电子互连的优选形式。倒装改善了电性能。对于高频应用例如主机和机算机工作站，倒装式互连是最有效的电互连。除了在功能的效率之外，倒装在形式上也是有效的，因为其尺寸小。随着功率不断增大的器件的尺寸的减小，倒装提供了最小的互连选择。其它优点包括对热量易于处理、降低了电磁干扰(EMI)发射和降低了射频干扰(RFI)敏感度。
焊料隆起倒装式组装可与实在的表面安装技术(SMT)兼容(对SMT详细的介绍，请参看《(表面安装技术手册)》，Stephen W.Hinch，Longman Scientific&Technical，UK，1988)。对焊料隆起物冶金学性质的适当选择可使SMT组装生产线在产品通过生产线时，同时装配倒装组件和表面安装组件。这种兼容性提供了SMT组装线的安装基础的利用，以及把倒装片引入较大SMT组件的设计封装的灵活性。优于其它组装技术的倒装片的最显著的优点也许是其低的成本。倒装片消除了互连的整个高度—组件高度(见图2中的步骤B-E)。通过对消组件高度，系统成本显著降下。在IC行业，通常潜在的成本节约证明了以几百万美元对倒装片技术研究的投资是合算的。
制造倒装片互连的主要方式是采用焊料隆起物。施加焊料隆起物可通过蒸发、电镀、模版印刷和系列方法。但是，这些方法中的每一种具有具体的限制，并已经和正在进行着许多研究，以克服这些方法的限制。
在过去的三十年中，许多公司例如IBM已经利用蒸发来形成高铅(Pb)隆起物，用于倒装晶片。蒸发的一个主要缺点是高成本：至少需要价值千万美元的基本设备。加工成本也很高，因为工具和掩模成本、加工延迟、低生产量、低产出率、必须频繁地手工去除有毒的铅废料。然后，合金组成受到限制，因为许多金属不适合蒸发。特别的限制是锡(Sn)的淀积速率使得其不容易被蒸发。高锡合金(63Sn-37Pb，即“低共熔点”)被高度期望作为隆起物材料，因为低共熔点锡的熔点(Tm＝183℃)与现行SMT材料和工艺(通常在200-210℃进行)是兼容的。与此相反，铅的熔点是327℃，此温度将使SMT所用的许多有机材料(例如环氧树脂电路板，其最高承受温度是230℃，还有其它元件)熔化。
在蒸发工艺的改进上不乏已公布的专利。由于蒸发工艺涉及汽化的铅以及使铅淀积在所有被掩盖和未被掩盖的表面，所以金属荫罩的清洗是脏的而且有毒害。金属掩模在不能再清洗之前仅能重复利用三或四次，然后必须废弃。废料铅包括被铅包壳的掩模，造成了环境和工作者的安全问题，以及提高了制造费用。近来的专利、美国专利No.5152878着重提到掩模清洗的问题并提出了某些节省清洗技术的方法。但是，尽管改进可以加快隆起降低工作成本至一定程度，但蒸发所需的设备仍旧很贵，废料铅的毒害仍旧存在。
与伴随着汽化铅的毒害的蒸发技术不同，电镀是一种湿法技术，采用化学液作为介质，在其中淀积隆起物。化学电镀液含有铅和其它有害材料，这造成了操纵和放置上的问题。此外，电镀在效率上受到限制，因为它是分批作业。因此，大批量生产面对设备紧张的系列工艺的伴随的困难，作为IC的生产者都敏锐地知道，成本受生产批量和容量限制的影响。电镀的其它缺点包括对合金组成的控制困难，以小的隆起物间距一致地达到满意的隆起高度的问题，以及难于消除表面杂质。
如图2A所示，模版印刷(也称为丝网印刷)至少在概念上是最为简单的方式，但是在隆起物尺寸和间距上存在看起来是不可克服的限制(通常可参见《表面安装技术手册》，第245-260页)。
如图2A所示，模版印刷包括：把掩模10或丝网置于衬底12上，使用刮板16来刮压焊膏，在掩模上面厚厚地涂一层焊膏，用力使焊膏进入掩模的所有开孔，刮去多余的焊膏，在对焊膏进行回流之前移走掩模。回流是基本上可控的熔化，以使构成焊膏的金属小球凝聚形成电互连。
在较小芯片上组装更多的互连，要求有小的隆起物且有小的间距(间距是两个相邻隆起物中心距)。传统的模版印刷方法具有低的间距极限，为400微米，这主要是由于实在的模版在开孔宽度与掩模厚度的比(约2.5∶1)上受到的限制。此种限制是来源于模版中各孔的空隙与模版厚度之间相互作用，以及焊膏的物理和化学性能。众所周知的间距限制使得IC的制造者确信，模版印刷在大多数的倒装式隆起应用上是没有前途的，因为后者要求小于400微米的间距。
AT&T已经采用模版印刷来制造硅—硅组合器件。该工艺包括安装掩模，通过在硅元件之间由模版印刷的焊膏使硅与硅接合再回流，从而产生硅与硅的附着。掩模开孔受高宽比限制。
已经提出了一系列的方法，但只是在理论上引起兴趣，还没有一种能形成商业化。已提出的方法包括带有丝焊装置的(也称为“丝焊隆起物”)“焊柱—隆起”、移画印花法和焊料喷射法。为简化系列工艺所提出的方法仍要求多步骤。授予Kumar等人的美国专利No，5156997披露了简化的工艺，其组成为：淀积阻挡和扩散层，利用聚焦的液态金属离子源由金属形成隆起物，利用腐蚀去除裸露的阻挡/附着层。该工艺需要用13个多小时隆起200个管芯晶片。所以，即使简化的系列工艺也存在工艺缺点，例如缓慢的产率。
引人注目和显著的改进，应是简单的、低成本的，大批量的，对环境有利的(或环境中性的)、无害的工艺，用来把各种合金的隆起物施于衬底，而且隆起物的高度是均匀的，间距小，而且，从理想角度来说，这种方法将提供与现行表面安装技术组装线兼容的隆起物合金。
本发明提供了一种无害的，对环境无影响的用来使用于电互连的衬底(包括硅片在内)隆起的工艺。本发明的工艺提供了在回流期间在被附着的掩模所掩盖的衬底上的容纳焊膏堆积(CPD)。本发明的工艺提供了适用于间距小于400微米的倒装片或应用的隆起物。通过本发明的方案降低了工艺成本，这包括在一个实施例中的可重复使用的金属掩模，在另一实施例中的可光致成象的聚合物涂层，可移走或可不移走。
另外，本方法采用的制造技术具有显著的特征并适合于批量生产。
CPD把隆起物的组成控制与隆起物的体积控制分离开。例如，在蒸发和电镀中，体积和组成同时决定于单一的工艺步骤。对于CPD，金属的组成取决于焊膏制造，而形成隆起物的工艺决定了金属隆起物的体积。
实际上根据本发明可以用任何合金组成来隆起晶片。完全克服了蒸发方法的限制，因为CPD可以选用任何合金，而许多合金不能有效地蒸发。当期望与SMT兼容时，在合金的选择上，基本上仅有对熔点特性的限制。本发明的方法对合金组成的控制，比现行在合金和元素电镀方法中可达到的更为精确。本发明的方法提供了解决与蒸发施加铅(Pb)的现行方法或者由电镀液产生的化学废料相关的对环境和工作者安全的影响的方法。可达到一致的隆起高度、体积和间距。
图1包括1A和1B，展示了本发明的掩模/焊膏/衬底和掩模/隆起物/衬底组合的截面图。
图2包括2A-2I，展示了传统模板法，传统的表面安装技术装配，和表面安装技术组合工艺中所用的传统模板法。
图3A-3H展示了本发明的倒装式隆起物形成和倒装式组成。
图4是根据本发明的陲起物形成法的流程图。
图5展示了在优选实施例中掩模在衬底上的组合。
图6A-6C展示了提供附装的支座隆起物的本发明。
图7展示了提供体积可控的焊球形成的容纳焊膏淀积。
如图4所概述，本发明的方法包括以下步骤：衬底、掩模和焊膏的选择410；衬底和掩模的组合412；衬底—掩模的对准414，焊膏的堆积416；衬底—掩模—焊膏的回流422，掩模的去除424；掩模的清洗430；在另一处理循环中重复使用掩模。另一实施例中删除了掩模去除步骤424；其余还包括了中间检测418、426和修整420、428步骤，以此保证焊膏堆积厚度的均匀和焊球的布置。如果使用不可浸润的衬底，则不是隆起的衬底，而是采用产生体积可控的焊球的方法。
图3A-3H，展示本发明的工艺。图3A-3E展示了倒装式隆起物的形成，图3F-3H展示了倒装式组合，被选择的衬底320具有表面321或激活侧，用于形成电互连，其上已附着了可浸润或可焊接区322或者可焊接的隆起物限定金属(BLM)区。在优选实施例中，所选的衬底是具有可被堆积的合金浸润的BLM的硅片。具有锌酸盐焊盘(由无电Zn、Ni处理的Al焊盘，然后镀Au)并由SiN(氮化硅)钝化的硅片是优选实施例的衬底/BLM组合。制备具有间距在400微米以下的可焊接(或可浸润的)BLM的晶片是简易有效的。每个可浸润BLM的中心与中心的距离对应于隆起物的间距；优选实施例提供的间距在150-350微米的范围。这种最小间距界限通常是掩模技术的功效，以在掩模制造技术上改进的本发明，可实现甚至更小的间距。
衬底表面321的其余区域必须是不可浸润的区324(例如由不可浸润的材料如聚酰亚胺、氮化硅或二氧化硅覆盖的衬底区域)。在对于63Sn-37Pb隆起物的优选实施例中，硅片具有Ni-Au可浸润区和氮化硅的不可浸润区。
图1A和1B中分别展示了掩模/衬底/焊膏和掩模/衬底/隆起物一对组合的截面。开孔的设计(切割成为掩模的孔或槽，用于容纳焊膏)决定了作为可浸润隆起物限定金属的直径(d)、开孔尺寸(L)、焊膏堆积因子(PF)和掩模厚度(t)的函数的最终焊膏隆起物高度(h)和隆起物与掩模之间的间隙(c)。
回流的隆起物的期望体积(V隆起物)可表示为h和d的函数的截顶球体的体积：
焊膏开口体积(已被堆积的焊膏体积V焊剂)通过焊膏堆积因子(PF)与最终隆起物的球体体积相关，该因子(PF)定义为隆起物体积与焊膏体积的比例：
等直径球最有效的堆积是六角密堆积(HCP)或者面心立方堆积，其结果PF＝0.74。但实际上，堆积因子多少低于此值。
开孔(L)和掩模厚度(t)确定为所需开孔体积(V焊剂)、隆起物间距(P)、可允许的最小腹板宽度(W)和可允许的隆起物与掩模的最小间隙(c)的函数。
隆起物与掩模的间距(C)是： C = ( L - D ) 2
其中，焊球直径(D)是 D = h + d 2 4 h
开孔之间的腹板宽度W是
W＝P-L
实际中，针对适当的模板脱模，对可允许的最小腹板宽度(W)、以及可允许的最小隆起物与掩模的间隙(C)有所限制。
优选实施例中，开孔是圆筒形，这样：
Figure A9511634600141
优选实施例中，掩模/衬底/隆起物的参数是：
    p(μm)     d[μm]     h[μm]     L[μm ]     t[μm]   V焊膏[×10°μm3]  V隆起物[×10°μm3]  PF  D[μm]     w[μm]     c[μm]
  356   200   118   225   100     4.0     2.7   0.65   203     131     11
  250   150   118   190   100     2.8     1.9   0.65   166     60     13
  175   100   90   125   85     1.0     0.74   0.70   117     50     4
其它的掩模变型包括非圆筒形开孔，用于较大的体积和较大的腹板，还有非垂直侧壁，例如锥形开孔，用于改善脱模。
可以包括多焊道印刷/回流循环，用以提供增大的隆起物体积，而且如果需要还可提供非均匀隆起物。
掩模
如图3B所示，掩模326置于衬底320的表面321上。在优选实施例中，掩模326由金属制成，具体是75-100微米厚的应力均匀的压片合金42。掩模材料可以包括可光致成象的聚酰亚胺 干膜光掩模、液态可光致成象的光掩模、硅和陶瓷。掩模开孔330的布置及定位对应于衬底320的可浸润322区的布置及定位。如图5所示，衬底表面546和掩模544均具有一对孔或精调图形540、542。这些可用做对准导向，当掩模置于衬底上时，使待定位的掩模开孔330对应于衬底表面的可浸润区。
掩模具有两个用途。第一是提供储槽，控制待堆积的焊膏体积。第二是直至或在回流工艺期间起容纳焊膏的堤坝或其它作用。第二种用途是本工艺与标准的SMT工艺的差别所在。
由于用于间距小于400微米的开孔的高宽比不允许从衬底移去掩模(不移去具有掩模的焊膏)，在回流处理时掩模必须留在原位置。为了起焊膏储槽和堤坝的作用，必须解决在SMT工艺中不会遇到的问题。
(1)掩模的热膨胀系数(CTE)必须与衬底的紧密匹配，以使在回流工艺中不会因热应变失配而产生对准失调。在优选实施例中，要求使用合金42作为掩模材料，以便与硅衬底的CTE紧密匹配(硅的CTE＝2.5E-6吋/吋/℃，合金42的CTE＝4.4E-6吋/吋/℃)。
(2)把掩模保持在衬底的适当位置的支承结构，必须不向掩模或衬底施加应力。在SMT模板印刷中，掩模绷紧在框架上。为了能使用标准的框架安装技术，框架材料必须与掩模的CTE相同，而且在回流期间，框架的热量必须降至最小，以此消除掩模的变形或者破裂(由于加热及冷却步骤中的偏移及导致的应力)。在优选实施例中，采用高温磁体(AlNiCo)使掩模附着于衬底，从而无需框架。由于掩模材料是铁类的，所以磁体可以置于衬底与掩模对置的一侧。如果需要更大的附着力，则可把磁体置于掩模/衬底夹层的两侧。另外的实施例包括把衬底机械地夹持在掩模上，以及使用与掩模的CTE匹配的框架使掩模绷紧。
(3)模板表面必须是不能被所选金属焊膏所浸润的。如果掩模表面是可浸润的，则在回流期间金属焊剂将粘着(或浸润)于掩模，而不是与掩模分离并仅与焊盘粘着。为了消除这一问题，对掩模镀铬，因为铬(和氧化铬)不会被所用的低熔点Sn-Pb焊膏所浸润。
掩模—替换的实施例
其它的替换实施例包括为与衬底CIE匹配所设计的，并且对所选用的金属焊膏不浸润的不同金属或非金属可分离掩模。
用于完成两个所提到的掩模功能的另一方法是利用对衬底表面可移动的掩模，其上具有适当的开孔尺寸，以获得所期望的隆起物尺寸。在此实施例中，聚合物掩模应施于衬底表面，具有的开孔是通过在位于可浸润焊盘之上的掩模上利用化学、机械、等离子腐蚀或激光烧蚀所形成的。工艺的其余部分应是相同的，但清洁处理除外，这要求使用能在流动(或两个清洁步骤)中去除临时掩模及剩余物的溶剂。
此外，替换的实施例包括其它可由化学腐蚀或清洗剥蚀除去的掩模材料(液态可光致成象光掩模、干膜光掩模、剥落/剥蚀聚酰胺、陶瓷或硅)。
对准
图5展示了掩模544和衬底546的组合，利用磁体548通过的磁吸引把掩模从下面保持在衬底上，并使掩模开孔与衬底BLM焊盘对准。对应的掩模开孔330与表面321的可浸润区322对准，以此接收隆起物。可采用显微镜手动完成此种对准，并且相对掩模放入晶片，同时对准开口和焊盘。另外，也可采用工具销钉和对应的孔来完成对准。也可采用工具销钉或基准或目测系统来完成自动对准。
掩模开孔330尺寸通常(但并不要求)稍大于可浸润区的尺寸。开孔尺寸由所需的隆起物尺寸所决定。并不要求开孔具有与可焊焊盘相同的形状。为了增大隆起物的尺寸同时还保持小间距，掩模开孔可以是长方形和BLM圆形或者八角形。通过回流，焊料在BLM圆形焊盘上变为球形。
掩模开孔也可设计成对非常细的间距(小于175μm)覆盖多于一个焊盘。
焊膏堆积
如图3B所示，对准之后，把含有球形金属粉末和焊药的膏状组合物334堆积在掩模表面336并铺开，以使其充入每个掩模开孔330。此工艺通常称为“补缝”。
把一大团金属焊膏置于掩模表面。然后推刮焊膏通过所有开孔并再推到来清除掩模表面。这使焊膏仅留存于开孔内。然后检查焊膏淀积物，保证所有开孔均被填充。如果查出有任何未填充或部分填充的开孔，则再次推刮焊膏团通过开孔，然后再次推刮从清除掩模表面。如果检查表明所有开孔均已填充，则从掩模上除去剩余的焊膏团，如果仍未填充，则重复推刮/检查工艺。
可以全自动化地进行焊膏堆积。
焊膏：在标准的SMT模板印刷工艺中，原始的实施例使用为低熔点Pb-Sn焊料用途所配制的标准焊膏。焊药载体SMQ51AC由美国的铟公司(36 Robinson Road，Clinton，New York 13323)提供。仅仅颗粒尺寸分布改善至“-400+500”目分布，以满足CPD的要求。
焊膏是金属粉末均匀、稳定的分散在助剂载体中。助剂载体不仅含有助剂，而且还有其它成分，这些成分决定了在模板印刷、定位和回流工艺中焊膏的性能。头一个实施例使用为用低熔点Pb-Sn焊料的标准表面安装模板印刷所设计的焊膏。由以下方法可确定获得一致的金属隆起物形成的最佳能力：
1.金属粉末尺寸分布：金属粉末中颗粒尺寸范围是对所堆积的焊膏中金属成分最大化与金属氧化物成分最小化之间的综合平衡。尺寸分布的上限由掩模厚度设定。最大可允许的颗粒直径应小于掩模厚度的40％。对于100微米厚的掩模，给出的最大颗粒直径约为40微米。尺寸分布的下限取决于使金属氧化物成分最小的需要。对于Pb-Sn基焊料，焊料的氧化物成分在颗粒直径小于25微米时显著增多。因此，就此观点的原始证明来说，最小颗粒直径为25微米。此尺寸分布通常称为“-400，+500”。颗粒尺寸分布的优化是使此观点得以改进的一部分。在本发明的使用其它冶金术方法的其它实施例中，不同的颗粒尺寸分布可能是必需的。
2.焊膏助剂载体：“焊膏助剂载体”一词是用表述焊膏中的所有非金属成分。为用于标准SMT模板工艺所设计的焊膏含有多种CPD所不需要的成分。
a.流变剂：这些成分添加在焊膏助剂载体中，用来在标准模版印刷操作的推刮和模版脱模部分过程中控制焊膏的性能(常常添加各种高沸点溶剂作为流变剂)。此外，添加这些成分，用以在回流处理时防止孤立的焊膏块坍塌，并引起焊桥。这些成分中的一些对于推刮操作是必不可少的，必须存在于焊膏中。但是，这些对CPD来说不一定是必需的。
b.增粘剂：此成分是在布局和回流工艺中把表面安装元件保持在衬底或印刷电路板上所需要的。由于在容纳焊膏堆积时来布置元件，这种成分也许可以从焊膏中去掉。去掉这种成分将有助于在回流之后从焊膏隆起物上卸下掩模。
c.催化剂：这些成分对存在于金属粉末表面和隆起物下金属化表面上的氧化膜化学腐蚀是需要的。在CPD工艺中对催化剂的需要与在容纳焊膏堆积中对催化剂的需要是相同的，并且比其它的形成金属隆起物的方法具有明显的优点。这些催化剂为在隆起物形成期间从隆起物下金属化去除氧化物提供了一种方法。其它技术中每一种均要求在隆起处理开始之前，隆起物下金属化上无氧化物。
配制焊膏助剂载体，以满足对每种应用所选择的特定冶金学方法的要求。例如，在具有重量百分比大于90％的Pb的Pb-Sn焊膏中的助剂必须承受比低熔点Sn-Sb焊膏更高温度。低温焊料例如低熔点Sn-Bi焊料要求比低熔点Pb-Sn焊料更低温度的活化系统。为了满足每种所选金属的特定冶金术和温度的需要，无论何种改进均是必需的，据此，CPD为助剂载体成分的选择提供了灵活性。
3.金属粉末组分：CPD的主要优点在于能够使用可制成金属粉末并能熔化从而凝聚成单个、大的金属隆起物的任何金属。
金属粉末与助剂载体混合形成“焊膏”；金属粉末的冶金学组分变成金属隆起物组分。因此，在容纳焊膏堆积中，金属隆起物的冶金术被一种与现行的金属隆起物形成工艺相比，存在差异且更好控制的工艺决定。例如，在蒸发工艺中，在隆起物形成工艺期间，必须对两种不同的蒸发源进行控制，以此产生对金属隆起物的组分和体积的控制。一般对蒸发的或电镀的隆起物在组成上的控制为+/-5％，由于Pb和Sn在蒸发速率上存在较大差异，所以通常以蒸发工艺不易获得低熔点Sn-Pb焊料隆起物。对金属粉末在组分上的控制一般为+/-0.5％，比替换方式高出整整一个量级。此外，低熔点Sn-Pb焊料可以做到与高Pb焊料相同的组分控制。对其它金属的组分控制将取决于处理技术。如果采用雾化技术，则组分控制一般为+/-0.5％。
回流
接着，对衬底320、掩模326和焊料334的整个组合加热，以使焊料334回流(见图3C)。这就是说，对其加热直至焊膏金属球334熔化并凝聚成为单个球形或焊料隆起物338，每个掩模开孔330有一个隆起物338。
在容纳焊膏堆积中的回流工艺几乎与用于标准表面安装工艺(SMT)的相同。为了促进金属粉末凝聚成金属隆起物，在回流模式中必须含有三个众所周知的时间-温度区间：
1.溶剂蒸发：在焊膏中添加溶剂，用以控制工艺中的推刮部分。在回流过程(金属熔化之前)中必须使这些溶剂蒸发。在具有低熔点Sn-Pb焊料和铟公司的SMQ51AC焊膏的头一个实施例中，必须使衬底和焊膏的温度保持在90和110℃至少达50秒。其它的焊膏配方将要求不同的温度和时间。
2.助剂活化：为了使金属粉末凝聚成为单个金属隆起物，以及形成对隆起物下金属化的冶金粘合，必须使焊膏和衬底在预定温度保持一定的时间，以使焊膏中的活化剂从隆起物下金属化和各金属颗粒的每个表面除去金属氧化物。在具有低熔点Sn-Pb焊料和铟公司的SMQ51AC焊膏的头一个实施例中，衬底和焊膏的温度在150和170℃之间最少保持50秒。其它的焊膏配方要求不同的温度和时间。
最高温度：一般回流焊实际上采用的最高焊料温度应高于焊料粉末熔点30-50℃。对于头一个实施例中所用的低熔点Sn-Pb焊料，回流的最高温度在210-230℃之间。其它金属合金具有不同的熔点，要求采用不同的最高温度。
与通常的表面安装组合工艺相比，最高温度变化率稍有不同。在通常的表面安装回流工艺中，最高温度变化率取决于一定的表面安装元件经受快速温度变化的能力。在容纳焊膏堆积中，最高温度变化率取决于掩模和衬底以相同速率改变温度的要求。
清洗：回流工艺中形成了隆起物和组合件冷却之后，焊膏助剂载体部分仍残留着，并且可能会使掩模326粘到衬底320上。通过在适当的溶剂中清洗掩模和衬底来溶解这些残余物。在头一个实施例中，用于50％异丙醇和50％水的混合物来溶解残余物，并使掩模从衬底上卸下。分离之后，对衬底和掩模彻底清洗。清洗之后，把掩模送回至工艺起点，在另一衬底上重复使用。
可重复使用的掩模是本工艺的新的和有创造性的特征。在堆积和回流过程中，掩模留在原位。这消除传统模版印刷所固有的工艺限制。此外，本发明为细间距的较小隆起物的堆积提供了可重复的体积。
与现行的方式相比，本工艺是简单的，所以成本降低了。由于较好地确立了制造焊接所用金属粉末的技术，所以可以控制合金组分。合金组分可以控制在+/-0.5％之内，并与隆起物尺寸、晶片尺寸、隆起物在晶片上的布置无关。
由于本发明的实施几乎不需要专用设备，而且由于适用于模版印刷、回流和清洗的大多数设备是市售商品且性能良好，所以保证了本发明的制造能力。在不考虑适当改进和开发成本的情况下，可实际地保证大批量生产。大多数主要工艺步骤均可自动化。无需过高温度(对于低熔点焊料)，也无需化学罐或真空条件。本工艺可在两处进行检查及返工：焊膏堆积后的修整，掩模去除后的隆起物修整/置换(图4-418、420、426、428)。
图3F-3H展示了由倒装式组合工艺实现的两个衬底的组合。已隆起的衬底342被倒置，隆起物338布置得与接收衬底350接触。对于倒装式组合的实施是周知的回流352和下充354步骤，产生了完整的衬底与衬底的互连(图3H)。
这里给出的方法提供了大批量生产，以每15分钟20000个隆起物为基础，其数量级为每小时80000-100000个隆起物。
无需苛刻的电镀化学物，也避免了处置有毒害的电镀液。由于Pb金属合金是以膏状存在的，被良好地包容，从而不会给操作造成危害，浪费问题也很小。
其它的工艺选择
在衬底上形成了金属隆起物之后，可能需要一定的处理，即用不同组分的金属涂覆金属隆起物。上述CPD所用工艺可用来涂覆金属隆起物。
某些应用要求设置支座设定及控制两个衬底之间的高度。参看图6A。采用CPD，可在衬底上形成支座隆起物610和用于互连的金属隆起物612。通常，支座的材料在期望的处理温度下不会熔化。因此，必须首先在衬底上形成支座。如图6所示，通过采用CPD工艺，在衬底的适当位置上淀积支座材料，可实现此目的。
完成第一步骤时，衬底在适当位置含有金属支座隆起物。然后对衬底做第二次的容纳焊膏堆积处理，在互连位置形成低温隆起物，如图6B所示。
在互连隆起物处理期间，把低温金属焊膏堆积在所有适当的位置。在支座位置，存在两种选择。
选择1：部分蚀刻模版的衬底一侧，提供支座金属所用空隙，而不淀积低温金属焊膏。
选择2：在支座隆起物顶部堆积低温金属焊膏，并应在支座上形成覆盖层。
球的产生
本发明工艺的另一实施倒是产生不附着的金属球，而不是金属隆起物。
如图7所示，CPD步骤的产物是球体或球形710，与图3E类似，但有几点重要不同。在形成球的CPD中，第一步骤的材料选择相对于焊膏选择是相同的。但是，衬底712可能没有可浸润表面，而掩模714可以构成有开孔，以便使产生的球710的数量增至最大。由于衬底没有可浸润表面，所以无需对准步骤且可取消。焊膏堆积和回流是相同的。如果掩模是金属的则可去除，或者在用于球的收集和重复使用前的掩模—衬底组合的清洗的实施例中，不去除掩模。对于任何实施例来说，均收集球710并清洗衬底和掩模以重复使用。
可光致成象掩模方法还可用于制造球，只要衬底是不可浸润的。可以期望，在衬底—掩模组合多次使用后，从衬底去除本方法中的掩模。组合可以重复使用，而不去除掩模，只要能进行仔细的适当清洗即可。衬底可以重复使用，而与掩模是否重复使用无关。
由CPD产生的球，可以用做独立的基础，来修整由CPD隆起的衬底。CPD产生的球还可以用于OMPAC、BGA或者其它隆起或堆积方法。CPD代替了球产生的方法，例如把熔融金属吹入油中。正如这里所述的，CPD产生了所需数量精确形成体积球的良好控制方法。

Claims (17)

1.一种用来使电子器件附着于衬底的焊料隆起物的形成方法，其中的器件包含金属隆起接触点，衬底包含隆起物限制金属焊盘(反之亦然)，包括以下步骤：
把焊膏施于衬底-掩模组合的掩模侧，以使焊膏充入掩模开孔；
在足以使焊膏熔化并在每个掩模开孔内凝聚成金属球的温度，对衬底—掩模—焊膏组合加热，从而形成衬底—掩模—金属球组合；
冷却衬底—掩模—金属球组合，以使金属球固化，从而形成隆起物。
2.根据权利要求1的方法，其中施加焊膏的步骤还包括选择在助剂载体中包括金属粉末的焊剂的步骤。
3.根据权利要求1的方法，还包括把掩模附着于衬底的步骤，其中掩模的热膨胀系数，使得在加热和冷却期间由热量诱发的应力，在球体、掩模开孔和衬底之间引起的失调，小于会超过球体边缘与掩模开孔之间的间隙的失调。
4.根据权利要求3的方法，其中附着掩模的步骤还包括选择金属掩模的步骤。
5.根据权利要求3的方法，其中附着掩模的步骤还包括选择起掩模作用的聚合物组分的步骤，其中附加的步骤包括把聚合物施于衬底，在聚合物中蚀刻出孔，孔的位置对应于隆起物限定金属的位置。
6.根据权利要求5的方法，还包括在金属焊膏凝聚之后移走聚合物的步骤。
7.根据权利要求4的方法，其中附着金属掩模的步骤还包括用磁体把掩模附着于衬底。
8.根据权利要求4的方法，其中掩模附着于衬底的方式，允许加热和冷却期间掩模与衬底之间存在横向偏移，从而保持掩模孔与隆起物限定金属之间对准。
9.根据权利要求7的方法，其中磁体附着于衬底的步骤还包括选择由能承受加热步骤的材料构成的磁体的步骤。
10.根据权利要求9的方法，其中选择磁体的步骤还包括选择由AlNiCo构成的磁体。
11.根据权利要求1的方法，还包括选择焊膏的步骤，其中焊膏由能制成粉末的至少一种金属的合金和用于所述粉末的助剂载体组成。
12.根据权利要求11的方法，还包括选择焊膏的步骤，其中焊膏含有63Sn37Pb合金。
13.一种电气互连组合，包括：
互连衬底，具有第一主表面，其上预限定有可浸润和不可浸润的区；
互连介质，由附着于构成隆起的衬底的衬底可浸润区的焊料隆起物组成；
接收衬底，接收隆起的衬底的隆起物，并在加热和冷却条件下，附着于隆起物表面，该隆起物足以形成互连衬底与接收衬底之间的电气互连。
14.一种电气互连的衬底的组合方法，包括以下步骤：
采用包括以下步骤的方法在衬底上形成导电的隆起物：
把焊膏施于衬底—掩模组合的掩模侧，以使焊膏充入掩模开口；
在足以使焊膏在每个掩模开孔内凝聚成为金属球的温度下，对衬底—掩模—焊膏组合加热，从而形成衬底—掩模—金属球组合；
冷却衬底—掩模—金属球组合，以使金属球固化；
把衬底—掩模—球与第二衬底组合，形成一个组合，以使球表面靠在第二衬底；
对该组合加热，以使球熔化并浸润第二衬底表面；
冷却该组合，使熔化的球固化，以使第一和第二衬底在球的相对侧接合，并构成电气互连。
15.根据权利要求14的方法，还包括在加热之前对衬底/焊膏/掩模组合检查之后，通过添加额外的焊膏来返工的步骤。
16.根据权利要求15的方法，还包括返工步骤，即通过使隆起物定位在靠近衬底可浸润区的载体介质上，在球形成之后，添加额外的隆起物，以使隆起物被引导和移至可浸润区，并从载体介质上卸下。
17.一种产生焊球的方法，包括以下步骤：
选择掩模；
选择焊膏；
选择不可由所选择的焊膏浸润的衬底；
使掩模定位在衬底，从而形成衬底—掩模组合；
在衬底—掩模组合的掩模侧施加焊膏，以使掩模开孔被焊膏充满；
在足以使焊膏在每个掩模开孔内熔化并凝聚成为金属的温度下，对掩模—衬底—焊膏组合加热，从而形成掩模—衬底—球组合；
冷却掩模—衬底—球组合，以使金属球固化；
从衬底去除固化的金属球。
CN95116346A 1994-08-08 1995-08-07 通过容纳焊膏堆积使衬底隆起的方法 Expired - Fee Related CN1083155C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US287,453 1994-08-08
US08/287,453 US5539153A (en) 1994-08-08 1994-08-08 Method of bumping substrates by contained paste deposition

Publications (2)

Publication Number Publication Date
CN1159077A true CN1159077A (zh) 1997-09-10
CN1083155C CN1083155C (zh) 2002-04-17

Family

ID=23102980

Family Applications (1)

Application Number Title Priority Date Filing Date
CN95116346A Expired - Fee Related CN1083155C (zh) 1994-08-08 1995-08-07 通过容纳焊膏堆积使衬底隆起的方法

Country Status (5)

Country Link
US (4) US5539153A (zh)
EP (1) EP0697727A3 (zh)
JP (1) JPH08172259A (zh)
CN (1) CN1083155C (zh)
TW (1) TW360963B (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1327501C (zh) * 2004-07-22 2007-07-18 上海交通大学 倒装芯片凸点的选择性激光回流制备方法
CN100433316C (zh) * 2003-04-24 2008-11-12 国际商业机器公司 用于柱/球栅阵列的无铅合金、有机插入物和无源元件组件
CN101937858A (zh) * 2010-08-03 2011-01-05 清华大学 一种倒装芯片凸点结构的圆片级制造方法
CN110931363A (zh) * 2019-07-26 2020-03-27 上海兆芯集成电路有限公司 电子结构的制造方法
CN111326419A (zh) * 2018-12-17 2020-06-23 北京梦之墨科技有限公司 一种电路的制作方法

Families Citing this family (240)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2135508C (en) * 1994-11-09 1998-11-03 Robert J. Lyn Method for forming solder balls on a semiconductor substrate
US5915170A (en) * 1994-09-20 1999-06-22 Tessera, Inc. Multiple part compliant interface for packaging of a semiconductor chip and method therefor
JP3353508B2 (ja) * 1994-12-20 2002-12-03 ソニー株式会社 プリント配線板とこれを用いた電子装置
TW267265B (en) * 1995-06-12 1996-01-01 Connector Systems Tech Nv Low cross talk and impedance controlled electrical connector
US6939173B1 (en) 1995-06-12 2005-09-06 Fci Americas Technology, Inc. Low cross talk and impedance controlled electrical connector with solder masses
KR100192766B1 (ko) * 1995-07-05 1999-06-15 황인길 솔더볼을 입출력 단자로 사용하는 볼그리드 어레이 반도체 패키지의 솔더볼 평탄화 방법 및 그 기판구조
US5872051A (en) * 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
US6099935A (en) * 1995-12-15 2000-08-08 International Business Machines Corporation Apparatus for providing solder interconnections to semiconductor and electronic packaging devices
US6448169B1 (en) * 1995-12-21 2002-09-10 International Business Machines Corporation Apparatus and method for use in manufacturing semiconductor devices
JPH09214117A (ja) * 1996-01-30 1997-08-15 Nec Corp 半田バンプの形成方法
US5882720A (en) * 1996-02-01 1999-03-16 Mpm Corporation Monitoring deposited pads
US5973931A (en) * 1996-03-29 1999-10-26 Sony Corporation Printed wiring board and electronic device using same
JP3401391B2 (ja) * 1996-04-16 2003-04-28 日本特殊陶業株式会社 半田バンプを有する基板の製造方法
US5828031A (en) * 1996-06-27 1998-10-27 International Business Machines Corporation Head transducer to suspension lead termination by solder ball place/reflow
US6024584A (en) 1996-10-10 2000-02-15 Berg Technology, Inc. High density connector
US6093035A (en) * 1996-06-28 2000-07-25 Berg Technology, Inc. Contact for use in an electrical connector
DE69605658T2 (de) * 1996-07-05 2000-04-20 Hewlett-Packard Co. Herstellungsverfahren für Höcker
US6046882A (en) * 1996-07-11 2000-04-04 International Business Machines Corporation Solder balltape and method for making electrical connection between a head transducer and an electrical lead
US6113216A (en) 1996-08-09 2000-09-05 Hewlett-Packard Company Wide array thermal ink-jet print head
DE19634646A1 (de) * 1996-08-27 1998-03-05 Pac Tech Gmbh Verfahren zur selektiven Belotung
JP3409598B2 (ja) * 1996-08-29 2003-05-26 ソニー株式会社 半導体装置の製造方法
US5829668A (en) * 1996-09-03 1998-11-03 Motorola Corporation Method for forming solder bumps on bond pads
US6083768A (en) * 1996-09-06 2000-07-04 Micron Technology, Inc. Gravitationally-assisted control of spread of viscous material applied to semiconductor assembly components
US5759737A (en) * 1996-09-06 1998-06-02 International Business Machines Corporation Method of making a component carrier
US5854512A (en) * 1996-09-20 1998-12-29 Vlsi Technology, Inc. High density leaded ball-grid array package
US6241535B1 (en) 1996-10-10 2001-06-05 Berg Technology, Inc. Low profile connector
US6042389A (en) * 1996-10-10 2000-03-28 Berg Technology, Inc. Low profile connector
TW406454B (en) 1996-10-10 2000-09-21 Berg Tech Inc High density connector and method of manufacture
DE19646476C2 (de) * 1996-11-11 2002-03-14 Fraunhofer Ges Forschung Verbindungsstruktur
US6139336A (en) 1996-11-14 2000-10-31 Berg Technology, Inc. High density connector having a ball type of contact surface
US5909634A (en) * 1996-12-20 1999-06-01 Texas Instruments Method and apparatus for forming solder on a substrate
US5759910A (en) * 1996-12-23 1998-06-02 Motorola, Inc. Process for fabricating a solder bump for a flip chip integrated circuit
US5727461A (en) * 1997-02-06 1998-03-17 Amtx, Inc. Method of forming fiducials, and stencils containing such fiducials
US6036084A (en) * 1997-02-06 2000-03-14 Tdk Corporation Screen printing method and apparatus therefor, and electronic component soldering method using screen printing and apparatus therefor
FR2762715B1 (fr) * 1997-04-28 2000-07-21 Novatec Procede de realisation et de brasage de billes de connexion electrique sur des plages d'accueil de raccordement electrique de circuits ou de composants electroniques et dispositif de mise en oeuvre
US7842599B2 (en) * 1997-05-27 2010-11-30 Wstp, Llc Bumping electronic components using transfer substrates
US7288471B2 (en) * 1997-05-27 2007-10-30 Mackay John Bumping electronic components using transfer substrates
US6293456B1 (en) 1997-05-27 2001-09-25 Spheretek, Llc Methods for forming solder balls on substrates
US7819301B2 (en) 1997-05-27 2010-10-26 Wstp, Llc Bumping electronic components using transfer substrates
US7007833B2 (en) * 1997-05-27 2006-03-07 Mackay John Forming solder balls on substrates
US5988487A (en) * 1997-05-27 1999-11-23 Fujitsu Limited Captured-cell solder printing and reflow methods
US7654432B2 (en) * 1997-05-27 2010-02-02 Wstp, Llc Forming solder balls on substrates
US6609652B2 (en) 1997-05-27 2003-08-26 Spheretek, Llc Ball bumping substrates, particuarly wafers
US6059172A (en) * 1997-06-25 2000-05-09 International Business Machines Corporation Method for establishing electrical communication between a first object having a solder ball and a second object
US6050481A (en) * 1997-06-25 2000-04-18 International Business Machines Corporation Method of making a high melting point solder ball coated with a low melting point solder
TW453137B (en) 1997-08-25 2001-09-01 Showa Denko Kk Electrode structure of silicon semiconductor device and the manufacturing method of silicon device using it
US6441487B2 (en) 1997-10-20 2002-08-27 Flip Chip Technologies, L.L.C. Chip scale package using large ductile solder balls
US6324069B1 (en) 1997-10-29 2001-11-27 Hestia Technologies, Inc. Chip package with molded underfill
US6495083B2 (en) 1997-10-29 2002-12-17 Hestia Technologies, Inc. Method of underfilling an integrated circuit chip
JPH11145176A (ja) * 1997-11-11 1999-05-28 Fujitsu Ltd ハンダバンプの形成方法及び予備ハンダの形成方法
US6225205B1 (en) * 1998-01-22 2001-05-01 Ricoh Microelectronics Company, Ltd. Method of forming bump electrodes
US6110760A (en) * 1998-02-12 2000-08-29 Micron Technology, Inc. Methods of forming electrically conductive interconnections and electrically interconnected substrates
US6089151A (en) * 1998-02-24 2000-07-18 Micron Technology, Inc. Method and stencil for extruding material on a substrate
US6239385B1 (en) 1998-02-27 2001-05-29 Agilent Technologies, Inc. Surface mountable coaxial solder interconnect and method
US6059173A (en) * 1998-03-05 2000-05-09 International Business Machines Corporation Micro grid array solder interconnection structure for second level packaging joining a module and printed circuit board
JP4311774B2 (ja) * 1998-03-11 2009-08-12 富士通株式会社 電子部品パッケージおよびプリント配線板
US6253992B1 (en) * 1998-03-18 2001-07-03 Tessera, Inc. Solder ball placement fixtures and methods
US5933713A (en) 1998-04-06 1999-08-03 Micron Technology, Inc. Method of forming overmolded chip scale package and resulting product
JP4255161B2 (ja) * 1998-04-10 2009-04-15 株式会社野田スクリーン 半田バンプ形成装置
US6406988B1 (en) 1998-04-24 2002-06-18 Amerasia International Technology, Inc. Method of forming fine pitch interconnections employing magnetic masks
US6580035B1 (en) 1998-04-24 2003-06-17 Amerasia International Technology, Inc. Flexible adhesive membrane and electronic device employing same
US6297564B1 (en) 1998-04-24 2001-10-02 Amerasia International Technology, Inc. Electronic devices employing adhesive interconnections including plated particles
US6153505A (en) * 1998-04-27 2000-11-28 International Business Machines Corporation Plastic solder array using injection molded solder
FR2778308B1 (fr) 1998-04-30 2006-05-26 Schlumberger Systems & Service Procede de realisation d'un composant electronique et composant electronique
US6136128A (en) 1998-06-23 2000-10-24 Amerasia International Technology, Inc. Method of making an adhesive preform lid for electronic devices
US6428650B1 (en) 1998-06-23 2002-08-06 Amerasia International Technology, Inc. Cover for an optical device and method for making same
US6409859B1 (en) 1998-06-30 2002-06-25 Amerasia International Technology, Inc. Method of making a laminated adhesive lid, as for an Electronic device
US6182883B1 (en) * 1998-07-08 2001-02-06 Lucent Technologies Inc. Method and apparatus for precisely registering solder paste in a printed circuit board repair operation
DE19832706C2 (de) * 1998-07-14 2000-08-03 Siemens Ag Halbleiterbauelement im Chip-Format und Verfahren zu seiner Herstellung
US6399178B1 (en) 1998-07-20 2002-06-04 Amerasia International Technology, Inc. Rigid adhesive underfill preform, as for a flip-chip device
US6137693A (en) * 1998-07-31 2000-10-24 Agilent Technologies Inc. High-frequency electronic package with arbitrarily-shaped interconnects and integral shielding
US6461953B1 (en) * 1998-08-10 2002-10-08 Fujitsu Limited Solder bump forming method, electronic component mounting method, and electronic component mounting structure
US6100175A (en) 1998-08-28 2000-08-08 Micron Technology, Inc. Method and apparatus for aligning and attaching balls to a substrate
DE19839760A1 (de) * 1998-09-01 2000-03-02 Bosch Gmbh Robert Verfahren zur Verbindung von elektronischen Bauelementen mit einem Trägersubstrat sowie Verfahren zur Überprüfung einer derartigen Verbindung
US6145735A (en) * 1998-09-10 2000-11-14 Lockheed Martin Corporation Thin film solder paste deposition method and tools
DE19845665C2 (de) * 1998-10-05 2000-08-17 Orga Kartensysteme Gmbh Verfahren zur Herstellung eines Trägerelements für einen IC-Baustein zum Einbau in Chipkarten
US6595408B1 (en) * 1998-10-07 2003-07-22 Micron Technology, Inc. Method of attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux prior to placement
US6268275B1 (en) 1998-10-08 2001-07-31 Micron Technology, Inc. Method of locating conductive spheres utilizing screen and hopper of solder balls
US6139972A (en) * 1998-10-26 2000-10-31 Agilent Technologies Inc. Solder paste containment device
US6316289B1 (en) 1998-11-12 2001-11-13 Amerasia International Technology Inc. Method of forming fine-pitch interconnections employing a standoff mask
US6163957A (en) * 1998-11-13 2000-12-26 Fujitsu Limited Multilayer laminated substrates with high density interconnects and methods of making the same
JP4119024B2 (ja) * 1998-11-26 2008-07-16 株式会社Ｎｅｏｍａｘマテリアル 金属ボールの製造方法
US6523736B1 (en) * 1998-12-11 2003-02-25 Micron Technology, Inc. Methods and apparatus for forming solder balls
US6085968A (en) * 1999-01-22 2000-07-11 Hewlett-Packard Company Solder retention ring for improved solder bump formation
FR2789541B1 (fr) * 1999-02-05 2001-03-16 Novatec Sa Soc Procede de realisation de modules electroniques a connecteur a billes ou a preformes integre brasables sur circuit imprime et dispositif de mise en oeuvre
US6426564B1 (en) * 1999-02-24 2002-07-30 Micron Technology, Inc. Recessed tape and method for forming a BGA assembly
US6326555B1 (en) 1999-02-26 2001-12-04 Fujitsu Limited Method and structure of z-connected laminated substrate for high density electronic packaging
US6528345B1 (en) 1999-03-03 2003-03-04 Intel Corporation Process line for underfilling a controlled collapse
US6331446B1 (en) 1999-03-03 2001-12-18 Intel Corporation Process for underfilling a controlled collapse chip connection (C4) integrated circuit package with an underfill material that is heated to a partial gel state
US20020014688A1 (en) 1999-03-03 2002-02-07 Suresh Ramalingam Controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials
US6492251B1 (en) * 1999-03-10 2002-12-10 Tessera, Inc. Microelectronic joining processes with bonding material application
CA2367318C (en) 1999-03-17 2008-09-09 Novatec Sa Filling device and method for filling balls in the apertures of a ball-receiving element
FR2791046B1 (fr) * 1999-03-17 2001-05-11 Novatec Sa Soc Procede et dispositif de distribution unitaire de billes solides et identiques sur un substrat par serigraphie
US6271107B1 (en) 1999-03-31 2001-08-07 Fujitsu Limited Semiconductor with polymeric layer
JP3726998B2 (ja) * 1999-04-01 2005-12-14 株式会社村田製作所 表面波装置
US6390439B1 (en) * 1999-04-07 2002-05-21 International Business Machines Corporation Hybrid molds for molten solder screening process
US6656750B1 (en) * 1999-04-29 2003-12-02 International Business Machines Corporation Method for testing chips on flat solder bumps
US6173887B1 (en) 1999-06-24 2001-01-16 International Business Machines Corporation Method of making electrically conductive contacts on substrates
US6513701B2 (en) 1999-06-24 2003-02-04 International Business Machines Corporation Method of making electrically conductive contacts on substrates
JP2001044607A (ja) * 1999-07-30 2001-02-16 Fuji Mach Mfg Co Ltd 半田バンプ形成方法および装置
US6861345B2 (en) * 1999-08-27 2005-03-01 Micron Technology, Inc. Method of disposing conductive bumps onto a semiconductor device
US6570251B1 (en) * 1999-09-02 2003-05-27 Micron Technology, Inc. Under bump metalization pad and solder bump connections
JP3403677B2 (ja) * 1999-09-06 2003-05-06 マイクロ・テック株式会社 半田ボール形成方法
CA2313551A1 (en) * 1999-10-21 2001-04-21 International Business Machines Corporation Wafer integrated rigid support ring
US6274474B1 (en) * 1999-10-25 2001-08-14 International Business Machines Corporation Method of forming BGA interconnections having mixed solder profiles
US6491204B1 (en) * 1999-11-30 2002-12-10 Gunter Erdmann Stencil wiping device
US6388335B1 (en) * 1999-12-14 2002-05-14 Atmel Corporation Integrated circuit package formed at a wafer level
JP3423930B2 (ja) * 1999-12-27 2003-07-07 富士通株式会社 バンプ形成方法、電子部品、および半田ペースト
US6186392B1 (en) * 2000-01-21 2001-02-13 Micron Technology, Inc. Method and system for forming contacts on a semiconductor component by aligning and attaching ferromagnetic balls
US6395995B1 (en) * 2000-03-15 2002-05-28 Intel Corporation Apparatus for coupling integrated circuit packages to bonding pads having vias
TW444258B (en) * 2000-05-04 2001-07-01 Orient Semiconductor Elect Ltd Manufacturing method of printed bump on semiconductor wafer or substrate
CN1278402C (zh) * 2000-06-16 2006-10-04 松下电器产业株式会社 电子器件的封装方法及电子器件封装体
US6540129B2 (en) * 2000-07-14 2003-04-01 Spraytech, Ltd. Apparatus and method for manufacturing solder balls
JP2002033346A (ja) * 2000-07-18 2002-01-31 Showa Denko Kk ハンダバンプ電極の形成に用いるハンダペースト
TW459362B (en) * 2000-08-01 2001-10-11 Siliconware Precision Industries Co Ltd Bump structure to improve the smoothness
TW445612B (en) * 2000-08-03 2001-07-11 Siliconware Precision Industries Co Ltd Solder ball array structure to control the degree of collapsing
US6444561B1 (en) * 2000-10-02 2002-09-03 Industrial Technology Research Institute Method for forming solder bumps for flip-chip bonding by using perpendicularly laid masking strips
US6638363B2 (en) * 2000-11-22 2003-10-28 Gunter Erdmann Method of cleaning solder paste
JP2002184802A (ja) * 2000-12-15 2002-06-28 Pioneer Electronic Corp 微小バンプの製造方法
JP4748889B2 (ja) * 2000-12-26 2011-08-17 イビデン株式会社 多層プリント配線板の製造方法
JP4707273B2 (ja) * 2000-12-26 2011-06-22 イビデン株式会社 多層プリント配線板の製造方法
US6419148B1 (en) 2001-01-23 2002-07-16 Orbotech Ltd. System for forming bumps on wafers
JP2002270611A (ja) * 2001-03-14 2002-09-20 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6889429B2 (en) * 2001-03-26 2005-05-10 Semiconductor Components Industries, L.L.C. Method of making a lead-free integrated circuit package
KR100384834B1 (ko) * 2001-03-30 2003-05-23 주식회사 하이닉스반도체 다중 기판 상에 형성되는 반도체 장치 및 그 제조 방법
JP3556922B2 (ja) * 2001-05-07 2004-08-25 富士通株式会社 バンプ形成方法
US6759319B2 (en) 2001-05-17 2004-07-06 Institute Of Microelectronics Residue-free solder bumping process
US20030009878A1 (en) * 2001-07-12 2003-01-16 John Gregory Method for attaching an electronic component to a substrate
US6747298B2 (en) * 2001-07-23 2004-06-08 Cree, Inc. Collets for bonding of light emitting diodes having shaped substrates
US6888167B2 (en) * 2001-07-23 2005-05-03 Cree, Inc. Flip-chip bonding of light emitting devices and light emitting devices suitable for flip-chip bonding
US7518223B2 (en) * 2001-08-24 2009-04-14 Micron Technology, Inc. Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer
US6528417B1 (en) 2001-09-17 2003-03-04 Taiwan Semiconductor Manufacturing Company Metal patterned structure for SiN surface adhesion enhancement
JP3615206B2 (ja) 2001-11-15 2005-02-02 富士通株式会社 半導体装置の製造方法
US6854633B1 (en) 2002-02-05 2005-02-15 Micron Technology, Inc. System with polymer masking flux for fabricating external contacts on semiconductor components
US6606251B1 (en) * 2002-02-07 2003-08-12 Cooligy Inc. Power conditioning module
US6821348B2 (en) * 2002-02-14 2004-11-23 3M Innovative Properties Company In-line deposition processes for circuit fabrication
TWI284973B (en) * 2002-04-03 2007-08-01 Advanced Semiconductor Eng Flip-chip joint structure, and fabricating process thereof
US7309269B2 (en) * 2002-04-15 2007-12-18 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating light-emitting device and apparatus for manufacturing light-emitting device
US6710369B1 (en) * 2002-04-18 2004-03-23 Applied Microcircuits Corporation Liquid metal socket system and method
JP2003332360A (ja) * 2002-05-17 2003-11-21 Denso Corp 半導体装置
US6845901B2 (en) * 2002-08-22 2005-01-25 Micron Technology, Inc. Apparatus and method for depositing and reflowing solder paste on a microelectronic workpiece
JP4120324B2 (ja) * 2002-09-12 2008-07-16 沖電気工業株式会社 ボール電極形成方法
US6892925B2 (en) * 2002-09-18 2005-05-17 International Business Machines Corporation Solder hierarchy for lead free solder joint
US7250330B2 (en) * 2002-10-29 2007-07-31 International Business Machines Corporation Method of making an electronic package
US20050211427A1 (en) * 2002-11-01 2005-09-29 Cooligy, Inc. Method and apparatus for flexible fluid delivery for cooling desired hot spots in a heat producing device
AU2003286821A1 (en) 2002-11-01 2004-06-07 Cooligy, Inc. Optimal spreader system, device and method for fluid cooled micro-scaled heat exchange
US20050211417A1 (en) * 2002-11-01 2005-09-29 Cooligy,Inc. Interwoven manifolds for pressure drop reduction in microchannel heat exchangers
TWI295726B (en) * 2002-11-01 2008-04-11 Cooligy Inc Method and apparatus for achieving temperature uniformity and hot spot cooling in a heat producing device
US6986382B2 (en) * 2002-11-01 2006-01-17 Cooligy Inc. Interwoven manifolds for pressure drop reduction in microchannel heat exchangers
JP3631230B2 (ja) * 2002-11-21 2005-03-23 富士通株式会社 予備ハンダの形成方法
US6854636B2 (en) * 2002-12-06 2005-02-15 International Business Machines Corporation Structure and method for lead free solder electronic package interconnections
EP1569503B1 (en) * 2002-12-06 2010-11-24 Tamura Corporation Method for supplying solder
US6906598B2 (en) 2002-12-31 2005-06-14 Mcnc Three dimensional multimode and optical coupling devices
US7044196B2 (en) * 2003-01-31 2006-05-16 Cooligy,Inc Decoupled spring-loaded mounting apparatus and method of manufacturing thereof
US20090044928A1 (en) * 2003-01-31 2009-02-19 Girish Upadhya Method and apparatus for preventing cracking in a liquid cooling system
US6893799B2 (en) * 2003-03-06 2005-05-17 International Business Machines Corporation Dual-solder flip-chip solder bump
US6764937B1 (en) * 2003-03-12 2004-07-20 Hewlett-Packard Development Company, L.P. Solder on a sloped surface
TWI232569B (en) * 2003-03-21 2005-05-11 Comchip Technology Co Ltd Metal bonding method for semiconductor circuit components employing prescribed feeds of metal balls
JP2004349361A (ja) * 2003-05-21 2004-12-09 Casio Comput Co Ltd 半導体装置およびその製造方法
US20040232560A1 (en) * 2003-05-22 2004-11-25 Chao-Yuan Su Flip chip assembly process and substrate used therewith
US7171897B2 (en) * 2003-06-05 2007-02-06 Georgia Tech Research Corporation System and methods for data-driven control of manufacturing processes
US7297003B2 (en) * 2003-07-16 2007-11-20 Gryphics, Inc. Fine pitch electrical interconnect assembly
WO2005011060A2 (en) * 2003-07-16 2005-02-03 Gryphics, Inc. Electrical interconnect assembly with interlocking contact system
US7537461B2 (en) * 2003-07-16 2009-05-26 Gryphics, Inc. Fine pitch electrical interconnect assembly
US7021369B2 (en) * 2003-07-23 2006-04-04 Cooligy, Inc. Hermetic closed loop fluid system
US7591302B1 (en) 2003-07-23 2009-09-22 Cooligy Inc. Pump and fan control concepts in a cooling system
US7307222B2 (en) * 2003-09-24 2007-12-11 Agilent Technologies, Inc. Printed circuit board test access point structures and method for making the same
US8390126B2 (en) * 2003-10-03 2013-03-05 Motorola Mobility Llc Method and arrangement for reduced thermal stress between substrates
US7121647B2 (en) * 2003-10-03 2006-10-17 Lexmark International, Inc. Method of applying an encapsulant material to an ink jet printhead
US8641913B2 (en) * 2003-10-06 2014-02-04 Tessera, Inc. Fine pitch microcontacts and method for forming thereof
US6933171B2 (en) * 2003-10-21 2005-08-23 Intel Corporation Large bumps for optical flip chips
US7084500B2 (en) * 2003-10-29 2006-08-01 Texas Instruments Incorporated Semiconductor circuit with multiple contact sizes
US7895247B2 (en) 2003-10-29 2011-02-22 Oracle International Corporation Tracking space usage in a database
JP2005175128A (ja) * 2003-12-10 2005-06-30 Fujitsu Ltd 半導体装置及びその製造方法
TWI254995B (en) * 2004-01-30 2006-05-11 Phoenix Prec Technology Corp Presolder structure formed on semiconductor package substrate and method for fabricating the same
JP4006409B2 (ja) * 2004-03-17 2007-11-14 新光電気工業株式会社 配線基板の製造方法
US20050230821A1 (en) 2004-04-15 2005-10-20 Kheng Lee T Semiconductor packages, and methods of forming semiconductor packages
JP2005311112A (ja) * 2004-04-22 2005-11-04 Umc Japan バンプ付け方法およびバンプ付け装置
US7404613B2 (en) * 2004-06-30 2008-07-29 Lexmark International, Inc. Inkjet print cartridge having an adhesive with improved dimensional control
US20060042785A1 (en) * 2004-08-27 2006-03-02 Cooligy, Inc. Pumped fluid cooling system and method
US7743963B1 (en) 2005-03-01 2010-06-29 Amerasia International Technology, Inc. Solderable lid or cover for an electronic circuit
US20060226117A1 (en) * 2005-03-29 2006-10-12 Bertram Ronald T Phase change based heating element system and method
US7436114B2 (en) * 2005-06-03 2008-10-14 E.I. Du Pont De Nemours And Company Electronic device including a first workpiece, a second workpiece, and a conductive member substantially directly bonded to the first and second workpieces
US7279409B2 (en) * 2005-10-31 2007-10-09 Freescale Semiconductor, Inc Method for forming multi-layer bumps on a substrate
JP4650220B2 (ja) * 2005-11-10 2011-03-16 パナソニック株式会社 電子部品の半田付け方法および電子部品の半田付け構造
US20070145104A1 (en) * 2005-12-28 2007-06-28 Mengzhi Pang System and method for advanced solder bumping using a disposable mask
US7517788B2 (en) * 2005-12-29 2009-04-14 Intel Corporation System, apparatus, and method for advanced solder bumping
US7422973B2 (en) * 2006-01-27 2008-09-09 Freescale Semiconductor, Inc. Method for forming multi-layer bumps on a substrate
US7913719B2 (en) * 2006-01-30 2011-03-29 Cooligy Inc. Tape-wrapped multilayer tubing and methods for making the same
WO2007109608A2 (en) 2006-03-20 2007-09-27 Gryphics, Inc. Composite contact for fine pitch electrical interconnect assembly
US8157001B2 (en) * 2006-03-30 2012-04-17 Cooligy Inc. Integrated liquid to air conduction module
US7715194B2 (en) * 2006-04-11 2010-05-11 Cooligy Inc. Methodology of cooling multiple heat sources in a personal computer through the use of multiple fluid-based heat exchanging loops coupled via modular bus-type heat exchangers
US20070256825A1 (en) * 2006-05-04 2007-11-08 Conway Bruce R Methodology for the liquid cooling of heat generating components mounted on a daughter card/expansion card in a personal computer through the use of a remote drive bay heat exchanger with a flexible fluid interconnect
JP4882502B2 (ja) * 2006-05-15 2012-02-22 株式会社日立プラントテクノロジー シート印刷システム
TWI296184B (en) 2006-06-06 2008-04-21 Phoenix Prec Technology Corp Method for fabricating electrical connecting structure of circuit board
US20070284420A1 (en) * 2006-06-13 2007-12-13 Advanpack Solutions Pte Ltd Integrated circuit chip formed on substrate
US7615865B2 (en) * 2007-05-21 2009-11-10 Stats Chippac, Ltd. Standoff height improvement for bumping technology using solder resist
US20090111299A1 (en) * 2007-10-31 2009-04-30 International Business Machines Corporation Surface Mount Array Connector Leads Planarization Using Solder Reflow Method
US8250877B2 (en) * 2008-03-10 2012-08-28 Cooligy Inc. Device and methodology for the removal of heat from an equipment rack by means of heat exchangers mounted to a door
US9297571B1 (en) 2008-03-10 2016-03-29 Liebert Corporation Device and methodology for the removal of heat from an equipment rack by means of heat exchangers mounted to a door
KR100969441B1 (ko) * 2008-06-05 2010-07-14 삼성전기주식회사 반도체칩이 실장된 인쇄회로기판 및 그 제조방법
US7824935B2 (en) * 2008-07-02 2010-11-02 Intermolecular, Inc. Methods of combinatorial processing for screening multiple samples on a semiconductor substrate
US20100025862A1 (en) * 2008-07-29 2010-02-04 Peter Alfred Gruber Integrated Circuit Interconnect Method and Apparatus
WO2010017321A1 (en) * 2008-08-05 2010-02-11 Cooligy Inc. Bonded metal and ceramic plates for thermal management of optical and electronic devices
US20100147928A1 (en) * 2008-12-10 2010-06-17 Business Electronics Soldering Technologies, Inc. Method for the manual placement of bottom terminated leadless device electronic packages using a mated stencil pair
US7982311B2 (en) * 2008-12-19 2011-07-19 Intel Corporation Solder limiting layer for integrated circuit die copper bumps
US8366485B2 (en) 2009-03-19 2013-02-05 Fci Americas Technology Llc Electrical connector having ribbed ground plate
US8178970B2 (en) * 2009-09-18 2012-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Strong interconnection post geometry
US8163644B2 (en) 2009-10-01 2012-04-24 United States Of America As Represented By The Secretary Of The Army Template process for small pitch flip-chip interconnect hybridization
US8244384B2 (en) * 2009-11-12 2012-08-14 Honeywell International Inc. System identification in automated process control
US8424748B2 (en) 2009-12-21 2013-04-23 Intel Corporation Solder in cavity interconnection technology
US20110169157A1 (en) * 2010-01-13 2011-07-14 Wen-Jeng Fan Substrate and flip chip package with gradational pad pitches
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US8936967B2 (en) 2011-03-23 2015-01-20 Intel Corporation Solder in cavity interconnection structures
NL2007372C2 (en) * 2011-09-08 2013-03-11 Univ Delft Tech A process for the manufacture of a semiconductor device.
EP2624034A1 (en) 2012-01-31 2013-08-07 Fci Dismountable optical coupling device
US20130199831A1 (en) * 2012-02-06 2013-08-08 Christopher Morris Electromagnetic field assisted self-assembly with formation of electrical contacts
US8944831B2 (en) 2012-04-13 2015-02-03 Fci Americas Technology Llc Electrical connector having ribbed ground plate with engagement members
US9257778B2 (en) 2012-04-13 2016-02-09 Fci Americas Technology High speed electrical connector
USD727268S1 (en) 2012-04-13 2015-04-21 Fci Americas Technology Llc Vertical electrical connector
USD727852S1 (en) 2012-04-13 2015-04-28 Fci Americas Technology Llc Ground shield for a right angle electrical connector
USD718253S1 (en) 2012-04-13 2014-11-25 Fci Americas Technology Llc Electrical cable connector
US9543703B2 (en) 2012-07-11 2017-01-10 Fci Americas Technology Llc Electrical connector with reduced stack height
USD751507S1 (en) 2012-07-11 2016-03-15 Fci Americas Technology Llc Electrical connector
US9237659B2 (en) * 2012-09-28 2016-01-12 Intel Corporation BGA structure using CTF balls in high stress regions
US9960105B2 (en) * 2012-09-29 2018-05-01 Intel Corporation Controlled solder height packages and assembly processes
US8802556B2 (en) * 2012-11-14 2014-08-12 Qualcomm Incorporated Barrier layer on bump and non-wettable coating on trace
USD745852S1 (en) 2013-01-25 2015-12-22 Fci Americas Technology Llc Electrical connector
USD720698S1 (en) 2013-03-15 2015-01-06 Fci Americas Technology Llc Electrical cable connector
EP2886244A1 (de) 2013-12-17 2015-06-24 Heraeus Deutschland GmbH & Co. KG Verfahren zur Befestigung eines Bauteils auf einem Substrat
US20170016745A1 (en) * 2014-03-24 2017-01-19 Panasonic Intellectual Property Management Co., Ltd. Magnetic sensor
WO2016056179A1 (ja) 2014-10-09 2016-04-14 パナソニックＩｐマネジメント株式会社 磁気センサ
US9633971B2 (en) 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
TWI822659B (zh) 2016-10-27 2023-11-21 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
US10261123B2 (en) * 2017-08-24 2019-04-16 Micron Technology, Inc. Semiconductor device structures for burn-in testing and methods thereof
JP7201461B2 (ja) * 2019-01-30 2023-01-10 デクセリアルズ株式会社 微小粒子配列用マスク
US11916003B2 (en) * 2019-09-18 2024-02-27 Intel Corporation Varied ball ball-grid-array (BGA) packages
US12021048B2 (en) * 2021-08-30 2024-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1067415A (en) * 1911-05-11 1913-07-15 Carl Emil Egner Soldering-body for joining electric conduits or the like.
US3002847A (en) * 1958-09-11 1961-10-03 Robert A Shaffer Process for producing a fine mesh pattern on a substrate
US3458925A (en) * 1966-01-20 1969-08-05 Ibm Method of forming solder mounds on substrates
US3569607A (en) * 1969-08-01 1971-03-09 Ibm Resolderable connector
US3719981A (en) * 1971-11-24 1973-03-13 Rca Corp Method of joining solder balls to solder bumps
DE3001820C2 (de) * 1980-01-18 1982-09-16 Siemens AG, 1000 Berlin und 8000 München Verfahren zum Herstellen einer Magnetschranke
US4489923A (en) * 1983-08-05 1984-12-25 Rca Corporation Fixture for solder tinning chip carriers
US4545610A (en) * 1983-11-25 1985-10-08 International Business Machines Corporation Method for forming elongated solder connections between a semiconductor device and a supporting substrate
US4759490A (en) * 1986-10-23 1988-07-26 Fujitsu Limited Method for soldering electronic components onto a printed wiring board using a solder paste
JPS63304636A (ja) * 1987-06-05 1988-12-12 Hitachi Ltd はんだキヤリア及びその製法並びにこれを用いた半導体装置の実装方法
JPH01214141A (ja) * 1988-02-23 1989-08-28 Nec Corp フリップチップ型半導体装置
US5022580A (en) * 1988-03-16 1991-06-11 Plessey Overseas Limited Vernier structure for flip chip bonded devices
US4893403A (en) * 1988-04-15 1990-01-16 Hewlett-Packard Company Chip alignment method
US4832255A (en) * 1988-07-25 1989-05-23 International Business Machines Corporation Precision solder transfer method and means
GB2249428A (en) * 1988-08-11 1992-05-06 Plessey Co Plc Connections for led arrays
US4898320A (en) * 1988-11-21 1990-02-06 Honeywell, Inc. Method of manufacturing a high-yield solder bumped semiconductor wafer
US5024372A (en) * 1989-01-03 1991-06-18 Motorola, Inc. Method of making high density solder bumps and a substrate socket for high density solder bumps
US5139610A (en) * 1989-04-20 1992-08-18 Honeywell Inc. Method of making a surface etched shadow mask
EP0398485B1 (en) * 1989-05-16 1995-08-09 Gec-Marconi Limited A method of making a Flip Chip Solder bond structure for devices with gold based metallisation
US5118029A (en) * 1989-11-30 1992-06-02 The Furukawa Electric Co., Ltd. Method of forming a solder layer on pads of a circuit board and method of mounting an electronic part on a circuit board
EP0469216B1 (en) * 1990-07-31 1994-12-07 International Business Machines Corporation Method of forming metal contact pads and terminals on semiconductor chips
US5105537A (en) * 1990-10-12 1992-04-21 International Business Machines Corporation Method for making a detachable electrical contact
US5156997A (en) 1991-02-11 1992-10-20 Microelectronics And Computer Technology Corporation Method of making semiconductor bonding bumps using metal cluster ion deposition
US5217597A (en) * 1991-04-01 1993-06-08 Motorola, Inc. Solder bump transfer method
US5118027A (en) * 1991-04-24 1992-06-02 International Business Machines Corporation Method of aligning and mounting solder balls to a substrate
US5133495A (en) * 1991-08-12 1992-07-28 International Business Machines Corporation Method of bonding flexible circuit to circuitized substrate to provide electrical connection therebetween
DE4126913A1 (de) * 1991-08-14 1993-02-18 Siemens Ag Verfahren zum beloten und montieren von leiterplatten mit bauelementen
JP3035021B2 (ja) * 1991-08-29 2000-04-17 株式会社リコー 液晶表示素子およびその製造方法
US5162257A (en) * 1991-09-13 1992-11-10 Mcnc Solder bump fabrication method
US5219117A (en) * 1991-11-01 1993-06-15 Motorola, Inc. Method of transferring solder balls onto a semiconductor device
US5152878A (en) 1991-12-31 1992-10-06 International Business Machines Corporation Method for electrochemical cleaning of metal residue on molybdenum masks
US5261593A (en) * 1992-08-19 1993-11-16 Sheldahl, Inc. Direct application of unpackaged integrated circuit to flexible printed circuit
KR0179404B1 (ko) * 1993-02-02 1999-05-15 모리시타 요이찌 세라믹기판과 그 제조방법
JPH06296060A (ja) * 1993-04-08 1994-10-21 Mitsubishi Electric Corp 半導体可視光レーザダイオードの製造方法
WO1994024699A1 (en) * 1993-04-08 1994-10-27 Citizen Watch Co., Ltd. Semiconductor device
US5307983A (en) * 1993-04-27 1994-05-03 At&T Bell Laboratories Method of making an article comprising solder bump bonding
US5323947A (en) * 1993-05-03 1994-06-28 Motorola, Inc. Method and apparatus for use in forming pre-positioned solder bumps on a pad arrangement
US5397921A (en) * 1993-09-03 1995-03-14 Advanced Semiconductor Assembly Technology Tab grid array
US5346118A (en) * 1993-09-28 1994-09-13 At&T Bell Laboratories Surface mount solder assembly of leadless integrated circuit packages to substrates
US5491364A (en) * 1994-08-31 1996-02-13 Delco Electronics Corporation Reduced stress terminal pattern for integrated circuit devices and packages
US5505367A (en) * 1994-11-02 1996-04-09 At&T Corp. Method for bumping silicon devices

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100433316C (zh) * 2003-04-24 2008-11-12 国际商业机器公司 用于柱/球栅阵列的无铅合金、有机插入物和无源元件组件
CN1327501C (zh) * 2004-07-22 2007-07-18 上海交通大学 倒装芯片凸点的选择性激光回流制备方法
CN101937858A (zh) * 2010-08-03 2011-01-05 清华大学 一种倒装芯片凸点结构的圆片级制造方法
CN111326419A (zh) * 2018-12-17 2020-06-23 北京梦之墨科技有限公司 一种电路的制作方法
CN110931363A (zh) * 2019-07-26 2020-03-27 上海兆芯集成电路有限公司 电子结构的制造方法
CN110931362A (zh) * 2019-07-26 2020-03-27 上海兆芯集成电路有限公司 电子结构的制造方法
CN110931444A (zh) * 2019-07-26 2020-03-27 上海兆芯集成电路有限公司 电子结构
CN110931444B (zh) * 2019-07-26 2022-09-27 上海兆芯集成电路有限公司 电子结构
CN110931362B (zh) * 2019-07-26 2022-09-27 上海兆芯集成电路有限公司 电子结构的制造方法
CN110931363B (zh) * 2019-07-26 2022-09-27 上海兆芯集成电路有限公司 电子结构的制造方法

Also Published As

Publication number Publication date
US5586715A (en) 1996-12-24
CN1083155C (zh) 2002-04-17
US5672542A (en) 1997-09-30
JPH08172259A (ja) 1996-07-02
US5539153A (en) 1996-07-23
EP0697727A3 (en) 1997-04-09
US5880017A (en) 1999-03-09
EP0697727A2 (en) 1996-02-21
TW360963B (en) 1999-06-11

Similar Documents

Publication Publication Date Title
CN1083155C (zh) 通过容纳焊膏堆积使衬底隆起的方法
US6873056B2 (en) Electrode-to-electrode bond structure
US6165885A (en) Method of making components with solder balls
TWI612591B (zh) 迴焊薄膜、焊料凸塊形成方法、焊料接合的形成方法及半導體裝置
KR100615870B1 (ko) 기능성 합금 입자
CN1084917C (zh) 导电胶体材料及其应用
US7781232B2 (en) Method to recover underfilled modules by selective removal of discrete components
US20110096507A1 (en) Microelectronic thermal interface
US20050133572A1 (en) Methods of forming solder areas on electronic components and electronic components having solder areas
US7279409B2 (en) Method for forming multi-layer bumps on a substrate
CN1301173C (zh) 回流钎焊方法
US20090041990A1 (en) Method for attachment of solder powder to electronic circuit board and soldered electronic circuit board
WO2021131620A1 (ja) 接続構造体及び接続構造体の製造方法
US7159758B1 (en) Circuit board processing techniques using solder fusing
JP3893100B2 (ja) 配線基板への電子部品搭載方法
KR100567103B1 (ko) 플립칩 범프 형성 방법
KR20220122663A (ko) 땜납 범프 형성용 부재, 땜납 범프 형성용 부재의 제조 방법, 및 땜납 범프 부착 전극 기판의 제조 방법
Baynham et al. Flip chip with lead-free solders on halogen-free microvia substrates
Wu et al. Board-level reliability of lead-free SnAgCu solder joint
Gonzalez Porosity in collapsible Ball Grid Array solder joints
Laine et al. C4NP-data for fine pitch to CSP flip chip solder bumping
Kulkarni Wafer-applied underfill for flip chip-on-laminate assembly
VIANCO Solder Mounting Technologies for Electronic Packaging
WO2008114465A1 (en) Method of forming solder bumps and solder bump-forming assembly

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C56 Change in the name or address of the patentee

Owner name: ANJELEN SCI. & TECH. INC.

Free format text: FORMER NAME OR ADDRESS: AGARLENT TECHNOLOGIES INC.

CP01 Change in the name or title of a patent holder

Address after: American California

Patentee after: Anjelen Sci. & Tech. Inc.

Address before: American California

Patentee before: Agarlent Technologies Inc.

C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee