CN113169170B - 用于形成多层水平nor型薄膜存储器串的方法 - Google Patents
用于形成多层水平nor型薄膜存储器串的方法 Download PDFInfo
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- CN113169170B CN113169170B CN201980080340.0A CN201980080340A CN113169170B CN 113169170 B CN113169170 B CN 113169170B CN 201980080340 A CN201980080340 A CN 201980080340A CN 113169170 B CN113169170 B CN 113169170B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
- H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201862775310P | 2018-12-04 | 2018-12-04 | |
| US62/775,310 | 2018-12-04 | ||
| PCT/US2019/064538 WO2020117978A1 (en) | 2018-12-04 | 2019-12-04 | Methods for forming multilayer horizontal nor-type thin-film memory strings |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113169170A CN113169170A (zh) | 2021-07-23 |
| CN113169170B true CN113169170B (zh) | 2024-08-13 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201980080340.0A Active CN113169170B (zh) | 2018-12-04 | 2019-12-04 | 用于形成多层水平nor型薄膜存储器串的方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (3) | US11404431B2 (enExample) |
| EP (1) | EP3891801A4 (enExample) |
| JP (1) | JP7526180B2 (enExample) |
| KR (1) | KR102761835B1 (enExample) |
| CN (1) | CN113169170B (enExample) |
| WO (1) | WO2020117978A1 (enExample) |
Families Citing this family (53)
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| US11120884B2 (en) | 2015-09-30 | 2021-09-14 | Sunrise Memory Corporation | Implementing logic function and generating analog signals using NOR memory strings |
| US9842651B2 (en) | 2015-11-25 | 2017-12-12 | Sunrise Memory Corporation | Three-dimensional vertical NOR flash thin film transistor strings |
| US10121553B2 (en) | 2015-09-30 | 2018-11-06 | Sunrise Memory Corporation | Capacitive-coupled non-volatile thin-film transistor NOR strings in three-dimensional arrays |
| US9892800B2 (en) | 2015-09-30 | 2018-02-13 | Sunrise Memory Corporation | Multi-gate NOR flash thin-film transistor strings arranged in stacked horizontal active strips with vertical control gates |
| US12537057B2 (en) | 2015-09-30 | 2026-01-27 | Sunrise Memory Corporation | Three-dimensional vertical nor flash thin film transistor strings |
| US10692874B2 (en) | 2017-06-20 | 2020-06-23 | Sunrise Memory Corporation | 3-dimensional NOR string arrays in segmented stacks |
| US10608011B2 (en) * | 2017-06-20 | 2020-03-31 | Sunrise Memory Corporation | 3-dimensional NOR memory array architecture and methods for fabrication thereof |
| US10608008B2 (en) | 2017-06-20 | 2020-03-31 | Sunrise Memory Corporation | 3-dimensional nor strings with segmented shared source regions |
| US10896916B2 (en) | 2017-11-17 | 2021-01-19 | Sunrise Memory Corporation | Reverse memory cell |
| CN111742368B (zh) | 2017-12-28 | 2022-09-13 | 日升存储公司 | 具有很细节距的三维nor存储器阵列：装置和方法 |
| US10475812B2 (en) | 2018-02-02 | 2019-11-12 | Sunrise Memory Corporation | Three-dimensional vertical NOR flash thin-film transistor strings |
| US11751391B2 (en) | 2018-07-12 | 2023-09-05 | Sunrise Memory Corporation | Methods for fabricating a 3-dimensional memory structure of nor memory strings |
| US10741581B2 (en) | 2018-07-12 | 2020-08-11 | Sunrise Memory Corporation | Fabrication method for a 3-dimensional NOR memory array |
| TWI713195B (zh) | 2018-09-24 | 2020-12-11 | 美商森恩萊斯記憶體公司 | 三維ｎｏｒ記憶電路製程中之晶圓接合及其形成之積體電路 |
| CN113169041B (zh) | 2018-12-07 | 2024-04-09 | 日升存储公司 | 形成多层垂直nor型存储器串阵列的方法 |
| JP7425069B2 (ja) | 2019-01-30 | 2024-01-30 | サンライズ メモリー コーポレイション | 基板接合を用いた高帯域幅・大容量メモリ組み込み型電子デバイス |
| JP7655853B2 (ja) | 2019-02-11 | 2025-04-02 | サンライズ メモリー コーポレイション | 垂直型薄膜トランジスタ、及び、垂直型薄膜トランジスタの、３次元メモリアレイのためのビット線コネクタとしての応用メモリ回路方法 |
| US11217600B2 (en) | 2019-07-09 | 2022-01-04 | Sunrise Memory Corporation | Process for a 3-dimensional array of horizontal NOR-type memory strings |
| US11917821B2 (en) | 2019-07-09 | 2024-02-27 | Sunrise Memory Corporation | Process for a 3-dimensional array of horizontal nor-type memory strings |
| WO2021127218A1 (en) | 2019-12-19 | 2021-06-24 | Sunrise Memory Corporation | Process for preparing a channel region of a thin-film transistor |
| TWI767512B (zh) | 2020-01-22 | 2022-06-11 | 美商森恩萊斯記憶體公司 | 薄膜儲存電晶體中冷電子抹除 |
| US12550382B2 (en) | 2020-01-22 | 2026-02-10 | Sunrise Memory Corporation | Thin-film storage transistor with ferroelectric storage layer |
| TWI836184B (zh) | 2020-02-07 | 2024-03-21 | 美商森恩萊斯記憶體公司 | 具有低延遲的高容量記憶體電路 |
| CN115362436A (zh) * | 2020-02-07 | 2022-11-18 | 日升存储公司 | 准易失性系统级存储器 |
| US11507301B2 (en) | 2020-02-24 | 2022-11-22 | Sunrise Memory Corporation | Memory module implementing memory centric architecture |
| WO2021173572A1 (en) | 2020-02-24 | 2021-09-02 | Sunrise Memory Corporation | Channel controller for shared memory access |
| WO2021173209A1 (en) | 2020-02-24 | 2021-09-02 | Sunrise Memory Corporation | High capacity memory module including wafer-section memory circuit |
| WO2021207050A1 (en) | 2020-04-08 | 2021-10-14 | Sunrise Memory Corporation | Charge-trapping layer with optimized number of charge-trapping sites for fast program and erase of a memory cell in a 3-dimensional nor memory string array |
| DE102020123746B4 (de) | 2020-05-29 | 2023-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dreidimensionale nichtflüchtige Speichervorrichtung und Verfahren zu deren Herstellung |
| US11482411B2 (en) * | 2020-06-30 | 2022-10-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method |
| US11640974B2 (en) | 2020-06-30 | 2023-05-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory array isolation structures |
| US11355516B2 (en) | 2020-07-16 | 2022-06-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional memory device and method |
| US11647634B2 (en) | 2020-07-16 | 2023-05-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional memory device and method |
| TW202220191A (zh) | 2020-07-21 | 2022-05-16 | 美商日升存儲公司 | 用於製造nor記憶體串之3維記憶體結構之方法 |
| US11423966B2 (en) | 2020-07-30 | 2022-08-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory array staircase structure |
| US11937424B2 (en) | 2020-08-31 | 2024-03-19 | Sunrise Memory Corporation | Thin-film storage transistors in a 3-dimensional array of nor memory strings and process for fabricating the same |
| CN112018121B (zh) * | 2020-09-01 | 2023-10-24 | 长江存储科技有限责任公司 | 半导体器件及其制作方法 |
| JP7491815B2 (ja) * | 2020-11-12 | 2024-05-28 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US11842777B2 (en) | 2020-11-17 | 2023-12-12 | Sunrise Memory Corporation | Methods for reducing disturb errors by refreshing data alongside programming or erase operations |
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| WO2022140084A1 (en) * | 2020-12-21 | 2022-06-30 | Sunrise Memory Corporation | Bit line and source line connections for a 3-dimensional array of memory circuits |
| CN116547796A (zh) | 2021-01-20 | 2023-08-04 | 日升存储公司 | 垂直nor闪存薄膜晶体管串及其制造 |
| CN112909011B (zh) * | 2021-03-08 | 2023-05-12 | 中国科学院微电子研究所 | Nor型存储器件及其制造方法及包括存储器件的电子设备 |
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| WO2023287908A1 (en) | 2021-07-16 | 2023-01-19 | Sunrise Memory Corporation | 3-dimensional memory string array of thin-film ferroelectric transistors |
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-
2019
- 2019-12-04 KR KR1020217021013A patent/KR102761835B1/ko active Active
- 2019-12-04 WO PCT/US2019/064538 patent/WO2020117978A1/en not_active Ceased
- 2019-12-04 US US16/703,663 patent/US11404431B2/en active Active
- 2019-12-04 CN CN201980080340.0A patent/CN113169170B/zh active Active
- 2019-12-04 JP JP2021531502A patent/JP7526180B2/ja active Active
- 2019-12-04 EP EP19893622.1A patent/EP3891801A4/en active Pending
-
2022
- 2022-06-28 US US17/809,535 patent/US12295143B2/en active Active
-
2025
- 2025-04-02 US US19/098,739 patent/US20250234550A1/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| KR102761835B1 (ko) | 2025-02-05 |
| JP7526180B2 (ja) | 2024-07-31 |
| US12295143B2 (en) | 2025-05-06 |
| US20220328518A1 (en) | 2022-10-13 |
| JP2022510370A (ja) | 2022-01-26 |
| CN113169170A (zh) | 2021-07-23 |
| US11404431B2 (en) | 2022-08-02 |
| EP3891801A4 (en) | 2022-08-24 |
| EP3891801A1 (en) | 2021-10-13 |
| US20250234550A1 (en) | 2025-07-17 |
| US20200176468A1 (en) | 2020-06-04 |
| KR20210091822A (ko) | 2021-07-22 |
| WO2020117978A1 (en) | 2020-06-11 |
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