CN1128469C - 将电子器件连接到柔性电路载体的方法及柔性电子载体 - Google Patents

将电子器件连接到柔性电路载体的方法及柔性电子载体 Download PDF

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Publication number
CN1128469C
CN1128469C CN97120465A CN97120465A CN1128469C CN 1128469 C CN1128469 C CN 1128469C CN 97120465 A CN97120465 A CN 97120465A CN 97120465 A CN97120465 A CN 97120465A CN 1128469 C CN1128469 C CN 1128469C
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Prior art keywords
carrier
circuit carrier
flexible circuit
solder
electronic device
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CN1181619A (zh
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霍马兹德亚尔·M·达拉尔
肯尼斯·M·法龙
格内·J·高登兹
辛西亚·苏姗·米尔科维奇
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International Business Machines Corp
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International Business Machines Corp
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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Abstract

一种将器件或封装直接连接到低成本且具有高可靠性的柔性有机电路载体上的结构和方法。用于连接的IC芯片上实现了一种新的焊料互连结构。该结构包含一层淀积在高熔点的铅-锡焊料球顶上的纯锡。这些方法、技术和冶金学结构使得能够将任意复杂度的电子器件直接连接到任意基片及任意封装层次结构上。而且,采用其它连接技术的器件或封装,如SMT,BGA,TBGA等都可以连接到柔性电路载体上。

Description

将电子器件连接到柔性电路 载体的方法及柔性电子载体
相关申请
本专利申请与下列专利申请相关:美国专利申请系列号No.08/476,475,标题为“METHOD FOR FORMING REFLOWED SOLDERBALL WITH LOW MELTING POINT METAL CAP”,1995年6月7日提出专利申请;美国专利申请系列号No.08/476,474,标题为“REFLOWED SOLDER BALL WITH LOW MELTING POINTMETAL CAP”,1995年6月7日提出专利申请;美国专利申请系列号No.08/476,466,标题为“METHOD FOR MAKING DIRECT CHIP ATTACHCIRCUIT CARD”,1995年6月7日提专利申请;以及美国专利申请系列号No.08/476,472,标题为“DIRECT CHIP ATTACH CIRCUIT CARD”,1995年6月7日提出专利申请,现在,它们已转让给本申请的受让人并把它们所公开的内容作为参考引用至此。
技术领域
本发明一般涉及一种改进的节省成本的采用倒装片连接(FCA)技术在柔性电路载体上实现的直接芯片连接(DCA)。更为具体的是,本发明中包含一种结构,在该结构中至少一个集成电路芯片可以直接连接到一个柔性基片上。这种直接连接可以采用C4(控制重叠的芯片连接)技术,通过覆盖已回流的焊料球形成一个易熔的焊料混合体来实现的。同时也公开了这种将芯片直接连接到柔性卡上的方法。
背景技术
随着新技术的发展,半导体器件变得越来越小,密度也越来越高。但是,电路密度的提高对于改善芯片与芯片间的连接以保持竞争力也提出了相应的挑战。尽管通过减少工艺的不稳定性使得工艺技术得到了显著的提高,但仅仅改进工艺对于提高半导体产品的成品率和可靠性是不够的。此外,封装工艺一直都没能赶上IC(集成电路)芯片微型化的步伐以提高电路性能。
电子产品通常由大量的元件组成。这些元件是按照一种层次结构来进行封装的,其中包含半导体微器件的集成电路(IC)芯片连接到载体上(第一层封装),这些载体是利用包含一层或几层金属互连线的陶瓷或有机材料的叠层制成的。这些载体上也可能包含一些分立元件诸如电容,电阻等。这种有IC芯片及一些密封和冷却的方法的封装载体就叫做模块。
这些模块又连接到由有机材料的叠层制成的,在板的两面都有印刷电路卡(第二层封装)上。
然后,这些卡再连接到板上(第三层封装)。许多电子应用,例如,要求复杂功能的计算机CPU,都需要采用这种三级层次结构。
要提高目前IC芯片的集成度就需要将第一层、第二层或这两层封装一起消除掉从而实现产品的微型化。例如,在直接访问的存储盘(DASD)中,由一个输入卡上的IC芯片构成的静态区,这个静态区实现的读/写功能通过一个柔性的印制电路板交叉连接到一个动态区,这个动态区由存储器盘组成。为了提高这样一个DASD设备的性能就要求静态区和动态区更紧密地邻接,这就要求将IC芯片直接连接到与盘驱动相连的柔性电路载体上。
带式自动键合(TAB)是当前用来将芯片直接连接到柔性电路载体上的最常用的方法,因为它也是实现第一层封装最常用的方法,而且它适合于在柔性基片上进行装配。
但是,TAB技术不能充分利用超大规模集成的优越性,超大规模集成不但要求I/O压焊块更紧凑而且要求采用一种阵列形式来安排大量的I/O压焊块。
TAB本身是一种第一层封装,因此将芯片装配到柔性电路载体上的TAB方式将使TAB被排除在芯片直接连接技术之外。
TAB的另一个缺点是它需要附加的空间来安排引线,这就限制了它将静态区和动态区安排得更加紧凑的能力。
使用TAB的另一个限制因素是难以测试和/或老化这些已装配的芯片,这就限制了成品率从而导致产品昂贵。
而且另一个缺点是对装配进行修改在经济上是不可行的。
这些限制因素使得有必要采用一种类似于C4的技术来实现芯片到电路载体的连接。
C4或控制重叠的芯片连接技术已成功地运用于芯片到陶瓷载体上的第一层封装中。许多作者已详细地描述了C4技术,例如,可参阅Rao R.Tummala与Eugene J.Rymaszewski编撰的Microelectronics Packaginghandbook 366-391页(1989),这里将通过参考将其公开内容合并至此作为参考。
C4互连由两个主要部分组成:一个称为(焊料)球限制的金属化(BallLimiting Metallurgy,BLM)的焊料可湿润的压焊块以及一个焊料球。BLM包含一个附着层如铬或钛钨,以及一个焊料可回流层如铜或镍。通过合理地选择BLM材料以及其厚度,可以为互连结构提供良好而可靠的电学、力学和热学的稳定性。C4所采用的焊料最好是一个低百分比(大约百分之二到百分之十)的锡与铅进行熔合。这样的组合用于:
(i)防止在下一层次的封装互连中已回流的焊料球或C4熔化,
(ii)减少BLM中铜与锡之间的反应,因为过度的铜-锡金属间化合所产生的高的应力将传送到下面的钝化层形成一个高的应力集中点,而且,
(iii)可以通过低的锡百分比实现更好的热疲劳特性。
现在,存在两个问题限制了将目前的C4技术运用到第二层或更高层次的封装,或运用到卡上的芯片直接连接。首先它限制了到针通孔(PTH)技术的互连而且无法采用节省空间的表面封装技术(SMT),因为它需要采用一个比SMT焊料的熔点更高的连接温度。其次,在这种相对较高的连接温度下(处于约340℃到约380℃之间)将无法采用有机卡材料。
有两种方法可以降低DCA的连接温度。一种方法是在卡的金属化部分之上放置一种易熔(或低熔点)的焊料。与该方法相关的一种方法在Legg和Schrottke提出的美国专利No.4,967,950中有所描述,该专利目前已转让给本发明的受让人。Legg和Schrottke描述了利用C4将IC芯片连接到柔性衬底(叠层片)的一种全面的方案。在衬底的接触区用易熔材料的合金给衬底“镀锡”,而焊料球则放在芯片的基面上。
预覆盖卡或有机载体的方法是由Fallon等人提出的,相关的专利申请是美国专利申请系列号08/387,686,标题为“Process for SelectiveApplication of Solder to Circuit Packages”,1995年2月13日提交,这里将其公开内容合并至此以作参考。在这个方法中,易熔焊料将被精密电镀到印制版的铜导体上,芯片的C4凸起可以与之接触。
另一种在卡或有机载体上预覆盖的方法是由Nishimura提出的,相关的专利申请是美国专利号5,238,176,标题为“Method and apparatus forforming bump”,该专利已转让给本申请的受让人,这里将其公开内容合并至此以作参考。在这个方法中,精确数量的液态易熔焊料通过一个注入头注入到层叠结构的电路卡中铜导体的相应位置上,其中注入头开孔的数目适合于卡上的元件数目。上述方法的应用仅限于刚性衬底。
Milkovich等人提出了一种针对柔性衬底的方法,与Legg和Schrottke提出的在衬底上用易熔合金“镀锡”的方案相吻合。有关的描述见于美国专利申请系列号08/071,630,标题为“Manufacturing Flexible CircuitBoard Assemblies with Common Heat Spreaders”,1993年6月3日提交,并已转让给本申请的受让人,这里将其公开内容合并至此以作参考。在这个方法中,首先制作满足特定布局要求的由易熔焊料球构成的图案,然后将这个图案转印到柔性电路载体上。图案是通过在一个不锈钢平板上电镀焊料球来形成的。这个方法首先要求在柔性电路载体上覆盖一层光可成像的焊料掩膜,同时在这个掩膜中与焊料球的布局相对应的位置上开孔。焊料球图案的转印是通过将不锈钢平板倒转放置在柔性电路载体板上并进行回流来实现的。柔性印刷电路板是用聚酰亚胺来制作的,例如Pyralux(E.I.duPont de Nemours & Co.的商标)。采用这一技术,Milkovich等人在1993年6月43届IEEE ECTC会议录的16-23页上发表题为“DoubleSided Flexible Carrier with Discretes and Thermally EnchancedFCA/COF”的文章,文章论证了在柔性电路载体的两面加入电路和实现器件连接的方法,这里将其公开内容合并至此以作参考。这个方法的缺点之一是成品率较低。
降低芯片直接连接(DCA)的连接温度的第二种方法是实现一种低熔点的芯片上焊料(SOC)C4结构而不是在载片的导体上进行。Carey等人在美国专利号5,075,965和Agarwala等人在美国专利号5,251,806和5,130,799,这些专利目前都已转让给本申请的受让人,以及Eiii等在日本专利发表号62-117346中,均描述了在芯片上放置低熔点焊料的各种不同的方案。Carey等人在美国专利号5,075,965中公开了一种方法,在该方法中采用了一个底部含大量的铅-顶部含大量的锡且具有足够厚度的不同质的各向异性的柱体来形成易熔的合金。由此形成的非回流的柱体将用来与卡中的导体进行连接。
为了防止由热力学因素引起的相互扩散的发生,Agarwala等人在美国专利号5,251,806和5,130,779中提出了一种通过在中间放置阻挡金属层的办法分离低熔点成分和高熔点成分结构。在此结构中确实体现出一个焊料原料的层次结构,但是在这个结构中高熔点的焊料柱体永远不会回流。因为层叠的焊料没有进行回流,在焊料堆叠部分与BLM的附着压焊块之间不会发生冶金学反应,已经认识到BLM的附着压焊块会导致C4连接较差的力学完整性。
Eiji等人在日本专利发表号62-117346中描述了一种低和高熔点焊料构成的各向异性柱体结构。这个发明的基本目的实质上是提供一种高度有所增加的焊料连接而不是提出一个低熔点焊料连接方法。在Eiji等人的发明中,首先是将一层高熔点的金属层固定到芯片和基片上,然后再形成一层低熔点的金属层。这两层低熔点的金属层将进行连接从而将芯片连接到基片上。
W.A.Dawson等人在第11卷第11期的IBM Technical DisclosureBulletin(1969年4月)1528页发表题为“Indium-Lead-Indium ChipJoining”的文章,公开了用铟或锡覆盖铅以支持扩散键合的标准。为了减轻芯片凹下到基片表面的问题,这里采用了一个中间的温度。
本发明的目的就是避免使用完全由低熔点混合物构成的凸起,因为高含量的锡将与BLM附着层中所有的铜发生反应并形成一个厚的金属间化合层。已经认识到起反应的BLM中产生的高的应力会引起焊料键合区脱落并引起绝缘层破裂。这些易熔焊料的凸起也会具有差的电迁移特性和热疲劳寿命。人们还认识到低熔点的易熔焊料会因热迁移而形成引起电路失效的空隙。
此外不同质的、各向异性的焊料柱的另一个缺点是这个结构不利于在将芯片连接到载体上之前对电路进行电学测试,因为在测试过程中电学探针会穿入低熔点的金属帽中并毁坏金属帽。而且,对于芯片老化而言采用任何一种已知的多层焊料球都是不可行的,因为通常采用的老化温度都在约120℃到150℃之间,即使在连接操作开始之前这个温度也会引起低和高熔点部分之间的扩散。
发明内容
本发明广泛地与电子电路封装中的互连有关,而且更特别的是提出了一种新的焊料互连技术以便于实现在柔性有机电路载体上进行的芯片直接连接(DCA)。
根据本发明提出了一种支持器件直接连接的柔性电路载体卡的制造方法,器件直接连接将采用低熔点的芯片上的焊料(SOC),其中低熔点的易熔合金是在连接过程中形成的且它定位在标准的高熔点C4球的顶部。
本发明包含一种新的方法和结构,通过使用一种新的焊料互连方案,提供器件到柔性电路卡的直接连接。
因此,本发明的目的之一就是提出一种制备柔性电路载体卡的方法,以便通过采用一种新的焊料互连方案来实现器件的直接连接。
本发明的另一个目的就是提出一种通过采用芯片直接连接(DCA)/芯片上焊料(SOC)技术可以同时在柔性电路板上连接器件的方法,在运用该方法的时候,可以一同使用各种倒装片、表面封装(SMT)和/或球网格阵列(BGA)技术。
本发明另一个目的是提供一种可以采用一种或多种连接技术直接连接一个或多个器件,并且具有可以将采用不同技术连接的器件分别独立地拔出和替换的灵活性的方法。
本发明的另一个目的是提出一种具有更高性能的柔性电路卡/器件的封装形式。
此外本发明的另一个目的是提出一种低成本、易于制造且具有高可靠性的柔性电路载体卡。
另外本发明的另一个目的是提供一种安装器件的柔性电路载体卡,它的侧面低、设计紧凑且重量轻。
此外本发明的另一个目的是提供一种与圆片级电学测试和老化兼容的柔性卡。
因此,在某个方面,本发明包括一种将电子器件直接连接到柔性电路载体上的方法,所述的方法包括以下步骤:
(a)在所述的电子器件上制备至少一个回流焊料球,其中所述的回流焊料球上采用至少一种低熔点金属进行至少一层覆盖以形成一个金属帽,
(b)采用至少一种热熔塑胶粘合剂将至少一层由至少一种刚性薄片构成的层片粘贴到柔性板的至少一个表面上,
(c)在所述柔性卡的所述的至少一个表面上制备至少一个导电金属线,
(d)采用至少一种绝缘材料覆盖所述柔性载体上至少一个区域,去掉所述绝缘材料中的局部区域并暴露出所述金属线路的选择区域,从而形成一个柔性电路载体,
(e)涂布易熔焊膏以便于覆盖所述柔性电路载体上的指定位置,
(f)将所述柔性电路载体放置到一个封装夹具上以固定所述柔性电路载体,
(g)将至少一种焊料助熔剂涂布到所述柔性电路载体上的指定位置上,
(h)将所述电子器件对准并放置到所述柔性电路载体上,以便使具有金属帽的回流焊料球与所述的焊料助熔剂形成接触,然后通过加热在所述的电子器件和所述的柔性电路载体之间形成一个电学连接。
因此在另一个方面本发明包含了一个柔性电学载体,该载体由一个柔性器件载体和通过至少一个焊料球电学连接到柔性器件载体上的至少一个电子器件,其中所述焊料球上有一个包含至少一种低熔点金属的金属帽,它们形成一个易熔混合体。
附图说明
本发明的有关特点相信是新颖的,并在所附的权利要求书中专门提出了本发明的组成部分的特点。这些附图仅用作注解,并不是按实际比例绘制的。而且在这些附图中相同的参考数字代表相同的部件。但是,该发明本身包含操作的组织与方法两部分,最好的理解方式是参看安排在有关附图之后的详细描述。在这些附图中:
图1示出了一个柔性电路载体的截面图,该电路载体包含至少一层柔性层并在载体的至少一个表面上具有至少一个电路。
图2示出了在采用至少一种粘合剂将一个刚性层固定后图1中所示的柔性载体基片的截面图。
图3示出了在邻近电路的地方粘贴上至少一层有机材料后柔性电路载体基片的截面图。
图4示出了一个已经进行局部处理以便于连接至少一个电子器件的柔性电子电路载体。
图5示出了将图4中的柔性电路载体固定到一个支撑夹具上。
图6示出了将一个或多个电子器件固定到局部处理后的柔性电路载体卡上。
图7示出了一个固定到单金属压焊块上的具有至少一个金属帽的焊料球互连的放大视图。
图8示出了图7中焊料球互连在回流操作之后固定到金属压焊块上的一个放大的横截面视图。
图9示出了采用至少一种密封剂将图8中至少一个焊料互连密封后的一个放大的横截面视图。
具体实施方式
本发明基本上包括一个具有金属导线,如铜导线,的柔性电路载体。在将要采用具有一个金属帽的回流焊料把电子器件电学连接到载体上的有关位置上开孔。对柔性电路载体的表面进行打磨有利于提高密封剂的附着力和流动。可以涂布焊料膏来支持表面封装(SMT),放置焊料球来支持球网格阵列(BGA),或者是,通过注入焊料的方式来放置焊料球以支持各种倒装片连接方法。类似地,柔性电路载体的一个或两个表面都可以进行处理以便于固定不同的电子器件。
本发明也包括了在柔性电路载体的表面形成一个芯片直接连接(DCA)。这是通过将芯片上的具有一个低熔点金属帽的焊料互连结构与柔性电路载体上的相关位置相对准来实现的。然后把该组件放在约150℃的背景温度下,接着最好是在一个氮或氮氢混合气体环境中采用红外热源将各芯片加热到到约190℃到约220℃之间的温度。然后对整个组件进行冷却,芯片最好采用一种基于环氧树脂的密封剂进行密封,例如,可以采用HYSOL4511,美国加利福尼亚州的Dexter Hysol公司采用的商品名。
本发明的一个优点是该方法可以运用到所有层次的封装中,如最高层次的封装,包括芯片连接到母板上、连接到柔性电路载体卡或连接到PCMCIA(个人计算机存储器卡国际协会)卡上。
本发明基本上是一个未预料到的结果,它表明淀积在一个回流焊料块顶上的低熔点焊料只与足够数量的焊料块熔合形成一个易熔合金体。还发现在多次低共熔点熔解过程之后只发生了相对较少的或没有相互扩散现象。相信这是基于这样一个事实:位于焊料块顶部的低熔点物质的数量和与淀积的低熔点金属块相对应的易熔混合物的数量相等。因此,不需要一个阻挡层就可以在一个固态焊料块的顶上形成一个具有预期体积的低共熔点熔液。即使连接到电路载体的铜互连线之后,在连接温度上升到低共熔点温度时,仍然保持着一个低共熔点熔液体。这个位于连接界面上的熔液结构为在对板上的其他器件不产生机械或热学影响的情况下方便地拔出已连接的芯片以便于进行芯片替换提供了一个理想的条件。
如前所述采用带有一个低熔点金属帽的焊料球的焊料互连可以实现在一个较低的温度下将芯片直接连接到任意高层次的封装基片上。在采用标准方法形成焊料球之后,焊料球进行回流以便于在焊料球上形成一个光滑的表面。一层金属,例如锡,最好是纯锡,将淀积到焊料球顶上。即使经过多次的低温回流过程之后,这个结构均可以实现对通过低温连接过程在焊料球顶上形成的易熔合金的定位。
这个方法并不需要对芯片将要连接到其上的载体或基片镀锡,这就使该方法比较经济。
还应注意到不论何时温度上升到稍高于低共熔点温度时,这个结构总是在与铜导线之间的结合点周围形成一个液态的凸起。因为减少了连接界面上的应力,这种液态凸起结构显著地提高了热疲劳寿命;其次为拔出芯片以进行芯片替换和现场维护提供了一种简便的手段。
这些方法、技术和冶金学结构保证了任意复杂度的器件直接连接到任意的基片或封装层次中的任意一个层次上,这样就使得产品更加经济更加紧凑同时也获得了更好的性能。
现在参看附图,在所有这些附图中,相同的参考数字代表了相同或相似的部件。图1中示出了一个柔性片10,最好是一个基于聚酰胺的柔性材料,利用至少一种第一热塑熔胶粘合剂12将至少一种金属线,例如一层铜膜层压在柔性板上,然后对铜膜进行电路化处理以形成各种的电路14。柔性电路片10可以是有机基片、多层有机基片、陶瓷基片或多层陶瓷基片,这里只列举了一部分。对于熟练的技术人员而言,电路载体基片15显然可以由一层或多层层间连线(图中未示出),和/或在基片表面的一面或两面上的布线通道制作。为便于理解,电路14只示出了一个表面。
在形成电路载体基片15之后,至少一种刚性部件18,诸如金属箔18,或例如,铝箔,通过采用至少一种第二热熔塑胶粘合剂16,被层压在电路载体基片的背面上,图2中有清楚的图示。刚性层18的厚度最好取为至少约2mil,最好在约3mil至约5mil之间。刚性层18中至少一层可以选择铝、钼、硅、钽或钛,这里只列举了一部分。
如图3所示,一层光可成像的有机材料20,诸如,例如PSR4000(日本TaiYo公司采用的商品名)被涂布到电路载体基片15的表面,并在80℃下预烘。并不是必须采用PSR4000。对于本发明的方法,不需要采用焊料掩膜。这里采用的PSR4000是用作焊料隔墙以防止焊料的横向流动。然后对有机材料20进行曝光和显影。
下一步在150℃固化有机材料20。这个固化过程在与器件尺寸相对应的一个大的区域开孔。在与IC芯片上C4焊料球的连接位置相对应的点上开孔以便于实现器件的连接。如图3中清楚地示出那样,上述操作制成了一个柔性带或卡25。
图4中示出了柔性电路载体23的顶视图。它包含布线或电路14,以及在不同的连接技术下用来安装电子器件的电学互连22,24,26和28。例如,互连22,可以是一个用于DCA/SOC的连接压焊块22;互连24,可以是支持FCA(倒装片连接)的采用焊料注入方法来放置的焊料24;互连26,可以是涂布的焊料26,诸如BGA(球网格阵列)26;而互连28,可以是支持SMT(表面封装技术)的涂布的焊料28,等。
有机材料20的表面,可以在约130mT的压强下进行约30分钟的氧等离子体打磨。这将使有机材料20的表面变得粗糙,这种表面的粗糙可以提高下面将要使用的芯片密封剂的流动性。
图5示出了固定在专门设计的定位装置或夹具30上的柔性电路载体23。夹具或固定装置30最好是用一种加固的热固聚合物玻璃制成。采用这种夹具或装置30的目的是确保在回流操作中柔性电路载体板23是水平的。采用弹簧加载的夹子32和34将柔性电路载体23的四个角牢固地固定在夹具或装置30上。
图6中示出了将一个或多个电子器件42,44,46和48固定到已经定位的柔性电路载体23上,而载体本身又固定到夹具30上。根据将要采用的互连技术,易熔的铅-锡焊料被放置到互连或压焊块22,24,26和28上。最好是将易熔焊料膏涂布到SMT压焊块28上。易熔焊料球放置到球网格阵列压焊块26上,易熔焊料注入到支持FCA的压焊块24上,等。一种未提纯的焊料助焊剂涂布在DCA/SOC位置22上。
具有带锡帽43的C4焊料球41的IC芯片42,将与DCA/SOC芯片位置22对准。其他电子器件44,46和48将与它们的正确位置相对准,如图6所示。例如,具有互连45的电子器件44与互连24对准,电子器件46与互连26对准,具有互连49的电子器件48与互连28对准,等。对于从事实际工作的技术人员来说,电子器件显然可能是分立器件如电阻、电容、电源、IC芯片,也可能是另一种封装,如薄嵌块扁平封装(TQFP),球网格阵列(BGA),带球网格封装(TBGA),放大器件,电路载体板,等。
然后对封装进行回流,最好在一个带式炉中进行。但是,用于焊料回流的热量可以通过至少一个聚焦的红外线灯来提供。最好对传送带的速度和炉中的区域温度进行调整以便于产生这样一种温度分布,其中图6中的封装在约155℃以上加热约3分钟到约5分钟,在约190℃到约230℃的最高温度下加热约15秒至约75秒。焊料的最高回流温度处于约190℃到约230℃之间。在约150℃之上在约2到5秒之间焊料回流。在最高温度下焊料回流的时间处于约15至约90秒之间。最好在干氮、氮氢混合气体或氢其中之一的环境中进行焊料回流,应该注意到连接这个芯片所需的加热周期与SMT或球网格阵列连接中热分布的时间要求是相同的,这样就提供了可以同时回流连接SOC芯片以及SMT和/或BGA器件的优点。如果采用了较低的最高回流温度,则在此最高温度下将需要较长的加热时间。
图7中示出了芯片42以及图6中DCA/SOC互连或压焊块22的一个放大的视图。芯片或电子器件42有一个焊料球41,此球有一个低熔点金属43构成的帽。焊料球41自身通过一个BLM56固定到压焊块52上。最好采用一层绝缘层54来保护芯片42的表面。在加热期间,焊料球41上的低熔点金属帽43与焊料球41熔合,形成一个在约183℃下熔化的易熔混合物53。低共熔点熔液的体积足够大,可以包围柔性电路载体23中暴露的压焊块22,例如一个铜压焊块22。芯片42中的这个低共熔点熔液的表面张力确保了它到柔性电路载体23中暴露的铜压焊块22的自对准。在回流温度维持期间所有可能的保护层以及助焊剂都被蒸发掉了,从而不需要进行后清洗。
图8示出了通过芯片连接操作形成芯片在柔性载体之上的结构50之后,图7中单个互连的放大的横截面图。可以清楚地看到芯片42已固定到柔性电路载体23上,而且在互连压焊块22和焊料51之间已形成一个易熔焊料53。
图9是电子器件或芯片42在连接到柔性电路载体23形成柔性载体上芯片的结构50后的放大的视图。为了保护电子器件42,例如芯片42与柔性电路载体23之间的电学连接,可以在电子器件或芯片42的下面和上面加上合适的密封剂60,例如HYSOL4511或环氧树脂60,并进行固化。已经发现氧等离子体打磨工序显著地改善了芯片42下面密封剂的流动性。如图9所示,这个密封剂主要用来保护芯片42和柔性电路载体23之间形成的电学连接。
焊料球41最好是一种高熔点的焊料球,例如含约97%的铝和约3%锡的焊料球,它是在焊料球限制的金属化56上形成的。可以采用蒸发或电镀的方法进行焊料淀积来形成焊料球41。在本发明独创的工序运用到焊料球41上之前,最好是所有的半导体处理工序,诸如圆片测试、电学测试都已完成且焊料已经进行回流从而恢复它的球形形状。
很明显图中的IC芯片42可以是一个半导体圆片,在该圆片上的许多器件(图中未示出)已经通过常规方法制成且这些器件已通过一层或多层的IC芯片内部布线实现了互连。
芯片上的高熔点焊料球最好含约2%至约10%的锡,余下的成分是铅,并且加上至少一层的低熔点金属,例如锡的金属帽,从而在高熔点焊料球的尖端形成易熔焊料。
对于熟练的技术人员而言,很明显柔性电路载体基片10可以通过柔性的聚酰胺、聚酯或基于聚乙烯的材料制成,在基片中可以制作一层或多层的层间布线(图中未示出),和/或在基片表面的一面或两面上制作布线通道。
电子器件通常含有导电部件,例如压焊块、引腿等。其材料可以是金,钴,铬,铜,铁,镍,钛钨,整相的铬和铜,以及它们的合金。
最好是采用射频蒸发、电子束蒸发、电镀、化学镀或注入方法在焊料球上形成至少一层包含至少一种低熔点金属的金属帽。
而且至少一种低熔点金属可以是铋,铟,锡或它们的合金。
最好用至少一种低熔点金属帽覆盖焊料球暴露的表面的约10%至90%,较好的情况是覆盖焊料球暴露的表面的约20%至80%,更好的情况是覆盖焊料球暴露的表面的约30%至50%。但是,在一些情况下低熔点金属可以完全包围焊料球。
包含至少一种低熔点金属的金属帽的平均厚度约为15至50微米。
所述至少一种低熔点金属帽的厚度选择应满足易熔体的体积相当于所述焊料球体积的约5%至约50%之间,最好是相应于所述焊料球体积的约10%至约30%之间。
应该认识到也可以采用其它材料来制作柔性电路载体,例如制作柔性电路载体的材料可以是聚酰亚胺,聚四氟乙烯,聚酯或树脂浸渍纤维,这里只列举了一部分。
虽然这里已经结合优选实施方式对本发明作了详细的描述,很明显,由于上述描述的启发,熟练的技术人员可以很容易地对本发明进行替换、修改和变更。因此发明人期望附加的权利要求书将能包含所有属于本发明真正范围和精髓中的替换、修改和变更。

Claims (45)

1.一种直接将电子器件连接到柔性电路载体的方法,所述方法包含以下步骤:
(a)在所述的电子器件上放置回流焊料球,其中所述的回流焊料球上有包含低熔点金属的涂层,以形成一个金属帽,
(b)采用热熔塑胶粘合剂在柔性板的至少一个表面上粘贴上刚性片层,
(c)在所述的柔性板的所述至少一个表面上形成一层导电金属线,
(d)选定部分所述的柔性载体并在上面覆盖一种有机材料,有选择地去掉部分所述有机材料并暴露出所述金属线的选定部分,从而形成一个柔性电路载体,
(e)涂布易熔焊料膏来覆盖所述柔性电路载体的选定位置,
(f)将所述柔性电路载体放置到封装夹具上从而固定该柔性电路载体,
(g)在所述柔性电路载体的选定位置涂布助焊剂,
(h)将所述电子器件对准并放置到所述柔性电路载体上,从而使带有金属帽的回流焊料球与所述助焊剂接触,然后通过加热在所述电子器件与所述柔性电路载体之间形成电学连接。
2.权利要求1中的方法,其特征在于采用环氧树脂进行密封以保护所述电子器件和柔性电路载体之间的电学连接。
3.权利要求1中的方法,其特征在于对所述有机材料表面的部分作粗糙化处理。
4.权利要求3中的方法,其特征在于采用氧等离子体来作粗糙化处理。
5.权利要求1中的方法,其特征在于所述柔性电路载体的一部分将用易熔焊料来涂布和回流。
6.权利要求5中的方法,其特征在于可以选用焊料注入、电镀、化学镀和转印中的一种方法来淀积易熔焊料。
7.权利要求1中的方法,其特征在于所述柔性电路载体的一部分采用易熔焊料来涂布和回流,且所述易熔焊料用来实现涂布的球网格阵列的电学连接。
8.权利要求1中的方法,其特征在于所述电子器件可以是IC芯片、电容、电阻、电路载体卡、电源和放大器件。
9.权利要求1中的方法,其特征在于所述柔性片可以选择有机基片、多层有机基片、陶瓷基片或多层陶瓷基片。
10.权利要求1中的方法,其特征在于所述焊料球是高熔点焊料。
11.权利要求1中的方法,其特征在于所述焊料球在所述电子器件的导电部件上面。
12.权利要求11中的方法,其特征在于所述导电部件的材料可以选择金、钴、铬、铜、铁、镍、钛钨、整相的铬和铜,以及它们的合金。
13.权利要求11中的方法,其特征在于所述的导电部件与电子器件内部的至少一个导电部件相连接。
14.权利要求1中的方法,其特征在于易熔焊料可以选择铅、铋、铟、锡、银、金,以及它们的合金。
15.权利要求1中的方法,其特征在于所述焊料球包含铅-锡合金,并且所述合金含约2%至约10%的锡。
16.权利要求1中的方法,其特征在于可以选用蒸发、电镀和焊料注入其中的一种方法来在所述的电子器件上形成所述的焊料球。
17.权利要求1中的方法,其特征在于可以选用射频蒸发、电子束蒸发、电镀、化学镀和注入中的一种方法来在所述焊料球上形成包含低熔点金属的金属帽。
18.权利要求1中的方法,其特征在于所述的低熔点金属可以选择铋、铟、锡和它们的合金。
19.权利要求1中的方法,其特征在于所述低熔点金属完全包围所述焊料球。
20.权利要求1中的方法,其特征在于用于所述焊料回流的热量是由至少一个聚焦的红外灯提供的。
21.权利要求1中的方法,其特征在于所述含低熔点金属的金属帽的厚度在约15至约50微米之间。
22.权利要求1中的方法,其特征在于所述低熔点金属的金属帽覆盖所述焊料球的暴露表面约10%至约90%。
23.权利要求1中的方法,其特征在于所述低熔点金属的金属帽覆盖所述焊料球的暴露表面约20%至约80%。
24.权利要求1中的方法,其特征在于所述低熔点金属的金属帽覆盖所述焊料球的暴露表面约30%至约50%。
25.权利要求1中的方法,其特征在于所述低熔点金属帽的厚度选择应满足易熔体的体积相当于所述焊料球体积的约5%至约50%之间。
26.权利要求1中的方法,其特征在于所述低熔点金属帽的厚度选择应满足易熔体的体积最好是相当于所述焊料球体积的约10%至约30%之间。
27.权利要求1中的方法,其特征在于所述金属帽的部分被固定到所述柔性电路载体的一个导电部件上。
28.权利要求27中的方法,其特征在于所述导电部件的材料可以选择金、钴、铬、铜、铁、镍、钽、钛、钛钨、整相的铬和铜,以及它们的合金。
29.权利要求1中的方法,其特征在于所述柔性电路载体可以选择介入体(interposer)、第一层封装、PCMCIA卡、盘驱动、第二层封装和母板。
30.权利要求1中的方法,其特征在于所述焊料的最高回流温度在约190至230℃之间。
31.权利要求1中的方法,其特征在于所述的焊料回流步骤是在约150℃以上加热约2到5分钟。
32.权利要求1中的方法,其特征在于最高温度下焊料回流的时间是在约15至90秒之间。
33.权利要求1中的方法,其特征在于所述焊料回流选择在干氮、氮氢混合气体和氢其中一种环境中进行。
34.权利要求1中的方法,其特征在于所述柔性电路载体既可以是一个柔性有机层压板也可以是一个柔性无机层压板。
35.权利要求1中的方法,其特征在于所述柔性有机电路载体的材料可以选择聚酰胺、聚四氟乙烯、聚酯和树脂浸渍纤维。
36.权利要求1中将具有带锡帽的C4焊料球的电子器件连接到柔性电路载体的方法,其特征在于包含以下步骤:
(a)将所述电子器件上的C4球与所述柔性电路载体上的对应开孔相对准,
(b)利用助焊剂提供的表面张力将所述电子器件固定到位,并且,
(c)对所述的C4焊料进行回流从而将所述电子器件键合到柔性电路载体上。
37.权利要求36中的方法,其特征在于采用环氧树脂进行密封以保护所述电子器件和柔性电路载体之间的电学连接。
38.柔性电子载体,包含一个柔性器件载体和通过焊料球电学连接于其上的至少一个电子器件,其中所述的焊料球上具有由低熔点金属形成的易熔金属帽。
39.权利要求38中的载体,其特征在于所述柔性器件载体上有表面封装器件(SMT)固定在上面。
40.权利要求38中的载体,其特征在于所述柔性器件载体有一个球网格阵列。
41.权利要求38中的载体,其特征在于所述柔性器件载体有一个SMT连接。
42.权利要求38中的载体,其特征在于在部分所述柔性器件载体上覆盖有绝缘材料。
43.权利要求38中的载体,其特征在于采用环氧树脂进行密封以保护所述电子器件和柔性电路载体之间的电源连接。
44.权利要求38中的载体,其特征在于所述柔性器件载体的至少一面上固定有刚性层。
45.权利要求44中的载体,其特征在于所述的刚性层可以选择铝、钼、硅、钽和钛。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101573789B (zh) * 2006-12-28 2016-11-09 英特尔公司 包括其凸块形成位点上的焊料帽的微电子管芯及其制造方法

Families Citing this family (152)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19633486C1 (de) 1996-08-20 1998-01-15 Heraeus Sensor Nite Gmbh Verfahren zur Herstellung einer Leiterplatte mit dünnen Leiterbahnen und Anschluß-Kontaktierungsbereichen sowie deren Verwendung
US6117759A (en) * 1997-01-03 2000-09-12 Motorola Inc. Method for multiplexed joining of solder bumps to various substrates during assembly of an integrated circuit package
IT1291779B1 (it) 1997-02-17 1999-01-21 Magnetek Spa Procedimento per la realizzazione di circuiti stampati e circuiti stampati cosi'ottenuti
US5877560A (en) * 1997-02-21 1999-03-02 Raytheon Company Flip chip microwave module and fabrication method
US6330967B1 (en) 1997-03-13 2001-12-18 International Business Machines Corporation Process to produce a high temperature interconnection
US6551857B2 (en) 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
US5915167A (en) * 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
US6082610A (en) * 1997-06-23 2000-07-04 Ford Motor Company Method of forming interconnections on electronic modules
US6050481A (en) * 1997-06-25 2000-04-18 International Business Machines Corporation Method of making a high melting point solder ball coated with a low melting point solder
US6059172A (en) * 1997-06-25 2000-05-09 International Business Machines Corporation Method for establishing electrical communication between a first object having a solder ball and a second object
US6407461B1 (en) * 1997-06-27 2002-06-18 International Business Machines Corporation Injection molded integrated circuit chip assembly
US6297559B1 (en) * 1997-07-10 2001-10-02 International Business Machines Corporation Structure, materials, and applications of ball grid array interconnections
US6120885A (en) 1997-07-10 2000-09-19 International Business Machines Corporation Structure, materials, and methods for socketable ball grid
US6025649A (en) * 1997-07-22 2000-02-15 International Business Machines Corporation Pb-In-Sn tall C-4 for fatigue enhancement
US6074895A (en) * 1997-09-23 2000-06-13 International Business Machines Corporation Method of forming a flip chip assembly
US6730541B2 (en) * 1997-11-20 2004-05-04 Texas Instruments Incorporated Wafer-scale assembly of chip-size packages
US6121678A (en) 1997-12-19 2000-09-19 Stmicroelectronics, Inc. Wrap-around interconnect for fine pitch ball grid array
US6235996B1 (en) * 1998-01-28 2001-05-22 International Business Machines Corporation Interconnection structure and process module assembly and rework
US6607613B2 (en) 1998-07-10 2003-08-19 International Business Machines Corporation Solder ball with chemically and mechanically enhanced surface properties
US6056831A (en) * 1998-07-10 2000-05-02 International Business Machines Corporation Process for chemically and mechanically enhancing solder surface properties
US6250540B1 (en) 1999-04-30 2001-06-26 International Business Machines Corporation Fluxless joining process for enriched solders
US6337509B2 (en) 1998-07-16 2002-01-08 International Business Machines Corporation Fixture for attaching a conformal chip carrier to a flip chip
JP4239310B2 (ja) * 1998-09-01 2009-03-18 ソニー株式会社 半導体装置の製造方法
JP3351355B2 (ja) * 1998-09-29 2002-11-25 株式会社デンソー 電子部品の実装構造
US6329713B1 (en) * 1998-10-21 2001-12-11 International Business Machines Corporation Integrated circuit chip carrier assembly comprising a stiffener attached to a dielectric substrate
US6657313B1 (en) * 1999-01-19 2003-12-02 International Business Machines Corporation Dielectric interposer for chip to substrate soldering
US6657309B1 (en) * 1999-02-08 2003-12-02 Rohm Co., Ltd. Semiconductor chip and semiconductor device of chip-on-chip structure
US6404212B1 (en) 1999-02-18 2002-06-11 St Assembly Test Services Pte Ltd Testing of BGA and other CSP packages using probing techniques
US6524346B1 (en) * 1999-02-26 2003-02-25 Micron Technology, Inc. Stereolithographic method for applying materials to electronic component substrates and resulting structures
US6127731A (en) * 1999-03-11 2000-10-03 International Business Machines Corporation Capped solder bumps which form an interconnection with a tailored reflow melting point
JP3209977B2 (ja) * 1999-04-02 2001-09-17 沖電気工業株式会社 半導体モジュ−ル
JP3428488B2 (ja) * 1999-04-12 2003-07-22 株式会社村田製作所 電子部品の製造方法
US6341418B1 (en) * 1999-04-29 2002-01-29 International Business Machines Corporation Method for direct chip attach by solder bumps and an underfill layer
US6333209B1 (en) 1999-04-29 2001-12-25 International Business Machines Corporation One step method for curing and joining BGA solder balls
US6281576B1 (en) 1999-06-16 2001-08-28 International Business Machines Corporation Method of fabricating structure for chip micro-joining
US6805278B1 (en) 1999-10-19 2004-10-19 Fci America Technology, Inc. Self-centering connector with hold down
CA2313551A1 (en) * 1999-10-21 2001-04-21 International Business Machines Corporation Wafer integrated rigid support ring
US10388626B2 (en) * 2000-03-10 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming flipchip interconnect structure
CN1119830C (zh) * 2000-04-27 2003-08-27 中国科学院上海冶金研究所 一种器件转移方法
ATE365378T1 (de) * 2000-07-28 2007-07-15 Infineon Technologies Ag Verfahren zur kontaktierung eines halbleiterbauelementes
JP2002076589A (ja) 2000-08-31 2002-03-15 Hitachi Ltd 電子装置及びその製造方法
JP2002093853A (ja) * 2000-09-07 2002-03-29 Internatl Business Mach Corp <Ibm> プリント配線板およびフリップチップ実装方法
US6931723B1 (en) * 2000-09-19 2005-08-23 International Business Machines Corporation Organic dielectric electronic interconnect structures and method for making
WO2002093637A2 (en) * 2001-05-17 2002-11-21 Koninklijke Philips Electronics N.V. Product comprising a substrate and a chip attached to the substrate
JP3634773B2 (ja) * 2001-06-08 2005-03-30 アルプス電気株式会社 磁気ヘッド及びその製造方法
US6869831B2 (en) * 2001-09-14 2005-03-22 Texas Instruments Incorporated Adhesion by plasma conditioning of semiconductor chip surfaces
US7026708B2 (en) * 2001-10-26 2006-04-11 Staktek Group L.P. Low profile chip scale stacking system and method
US7656678B2 (en) 2001-10-26 2010-02-02 Entorian Technologies, Lp Stacked module systems
US6914324B2 (en) * 2001-10-26 2005-07-05 Staktek Group L.P. Memory expansion and chip scale stacking system and method
US20060255446A1 (en) 2001-10-26 2006-11-16 Staktek Group, L.P. Stacked modules and method
US6670071B2 (en) * 2002-01-15 2003-12-30 Quallion Llc Electric storage battery construction and method of manufacture
US6622380B1 (en) 2002-02-12 2003-09-23 Micron Technology, Inc. Methods for manufacturing microelectronic devices and methods for mounting microelectronic packages to circuit boards
US6877653B2 (en) * 2002-02-27 2005-04-12 Advanced Semiconductor Engineering, Inc. Method of modifying tin to lead ratio in tin-lead bump
USRE41914E1 (en) 2002-05-10 2010-11-09 Ponnusamy Palanisamy Thermal management in electronic displays
US6849935B2 (en) * 2002-05-10 2005-02-01 Sarnoff Corporation Low-cost circuit board materials and processes for area array electrical interconnections over a large area between a device and the circuit board
US6838114B2 (en) 2002-05-24 2005-01-04 Micron Technology, Inc. Methods for controlling gas pulsing in processes for depositing materials onto micro-device workpieces
US6821347B2 (en) * 2002-07-08 2004-11-23 Micron Technology, Inc. Apparatus and method for depositing materials onto microelectronic workpieces
WO2004015764A2 (en) * 2002-08-08 2004-02-19 Leedy Glenn J Vertical system integration
US6955725B2 (en) * 2002-08-15 2005-10-18 Micron Technology, Inc. Reactors with isolated gas connectors and methods for depositing materials onto micro-device workpieces
US6791845B2 (en) * 2002-09-26 2004-09-14 Fci Americas Technology, Inc. Surface mounted electrical components
DE10258798A1 (de) * 2002-12-16 2004-07-22 Siemens Ag Verfahren und Vorrichtung zum partiellen Aufbringen von Klebstoff auf elektronische Bauelemente, Bestückvorrichtung zum Bestücken von Bauelementen
DE10258800A1 (de) * 2002-12-16 2004-07-08 Siemens Ag Verfahren und Vorrichtung zum Aufbringen einer Klebstoffschicht auf flächige Bauelemente, Bestückvorrichtung zum Bestücken von flächigen Bauelementen
US6905342B2 (en) * 2003-04-01 2005-06-14 Hewlett-Packard Development Company, L.P. Protected electrical interconnect assemblies
US7335396B2 (en) * 2003-04-24 2008-02-26 Micron Technology, Inc. Methods for controlling mass flow rates and pressures in passageways coupled to reaction chambers and systems for depositing material onto microfeature workpieces in reaction chambers
US6913343B2 (en) * 2003-04-30 2005-07-05 Hewlett-Packard Development Company, L.P. Methods for forming and protecting electrical interconnects and resultant assemblies
US7083267B2 (en) 2003-04-30 2006-08-01 Hewlett-Packard Development Company, L.P. Slotted substrates and methods and systems for forming same
US7235138B2 (en) 2003-08-21 2007-06-26 Micron Technology, Inc. Microfeature workpiece processing apparatus and methods for batch deposition of materials on microfeature workpieces
US7344755B2 (en) * 2003-08-21 2008-03-18 Micron Technology, Inc. Methods and apparatus for processing microfeature workpieces; methods for conditioning ALD reaction chambers
TWI233682B (en) * 2003-08-22 2005-06-01 Advanced Semiconductor Eng Flip-chip package, semiconductor chip with bumps, and method for manufacturing semiconductor chip with bumps
US7422635B2 (en) 2003-08-28 2008-09-09 Micron Technology, Inc. Methods and apparatus for processing microfeature workpieces, e.g., for depositing materials on microfeature workpieces
JP2005086044A (ja) * 2003-09-09 2005-03-31 Citizen Electronics Co Ltd 高信頼性パッケージ
US7056806B2 (en) 2003-09-17 2006-06-06 Micron Technology, Inc. Microfeature workpiece processing apparatus and methods for controlling deposition of materials on microfeature workpieces
US7282239B2 (en) * 2003-09-18 2007-10-16 Micron Technology, Inc. Systems and methods for depositing material onto microfeature workpieces in reaction chambers
KR101025844B1 (ko) * 2003-10-01 2011-03-30 삼성전자주식회사 SnAgAu 솔더범프, 이의 제조 방법 및 이 방법을이용한 발광소자 본딩 방법
US7323231B2 (en) * 2003-10-09 2008-01-29 Micron Technology, Inc. Apparatus and methods for plasma vapor deposition processes
US7581511B2 (en) * 2003-10-10 2009-09-01 Micron Technology, Inc. Apparatus and methods for manufacturing microfeatures on workpieces using plasma vapor processes
US7647886B2 (en) * 2003-10-15 2010-01-19 Micron Technology, Inc. Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from reaction chambers
US8216930B2 (en) 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US8674500B2 (en) 2003-12-31 2014-03-18 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
WO2005048311A2 (en) 2003-11-10 2005-05-26 Chippac, Inc. Bump-on-lead flip chip interconnection
US8574959B2 (en) 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
US7901983B2 (en) * 2004-11-10 2011-03-08 Stats Chippac, Ltd. Bump-on-lead flip chip interconnection
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8129841B2 (en) 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
US20060216860A1 (en) 2005-03-25 2006-09-28 Stats Chippac, Ltd. Flip chip interconnection having narrow interconnection sites on the substrate
US8026128B2 (en) * 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
USRE44500E1 (en) 2003-11-10 2013-09-17 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
US20070105277A1 (en) 2004-11-10 2007-05-10 Stats Chippac Ltd. Solder joint flip chip interconnection
US8076232B2 (en) 2008-04-03 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
US8350384B2 (en) * 2009-11-24 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US7659633B2 (en) 2004-11-10 2010-02-09 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US7258892B2 (en) * 2003-12-10 2007-08-21 Micron Technology, Inc. Methods and systems for controlling temperature during microfeature workpiece processing, e.g., CVD deposition
US7167375B2 (en) * 2004-01-16 2007-01-23 Motorola, Inc. Populated printed wiring board and method of manufacture
US7906393B2 (en) * 2004-01-28 2011-03-15 Micron Technology, Inc. Methods for forming small-scale capacitor structures
US7613010B2 (en) * 2004-02-02 2009-11-03 Panasonic Corporation Stereoscopic electronic circuit device, and relay board and relay frame used therein
US7584942B2 (en) * 2004-03-31 2009-09-08 Micron Technology, Inc. Ampoules for producing a reaction gas and systems for depositing materials onto microfeature workpieces in reaction chambers
US20050249873A1 (en) * 2004-05-05 2005-11-10 Demetrius Sarigiannis Apparatuses and methods for producing chemically reactive vapors used in manufacturing microelectronic devices
US8133554B2 (en) 2004-05-06 2012-03-13 Micron Technology, Inc. Methods for depositing material onto microfeature workpieces in reaction chambers and systems for depositing materials onto microfeature workpieces
US7699932B2 (en) * 2004-06-02 2010-04-20 Micron Technology, Inc. Reactors, systems and methods for depositing thin films onto microfeature workpieces
TWI331370B (en) * 2004-06-18 2010-10-01 Megica Corp Connection between two circuitry components
US8067837B2 (en) 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
KR100701641B1 (ko) * 2004-08-02 2007-03-30 도레이새한 주식회사 진공증착에 의해 구리도금층을 형성하는 연성회로기판용 적층구조체의 제조방법 및 그 장치
US7760513B2 (en) 2004-09-03 2010-07-20 Entorian Technologies Lp Modified core for circuit module system and method
US7423885B2 (en) 2004-09-03 2008-09-09 Entorian Technologies, Lp Die module system
US7443023B2 (en) 2004-09-03 2008-10-28 Entorian Technologies, Lp High capacity thin module system
US7488896B2 (en) * 2004-11-04 2009-02-10 Ngk Spark Plug Co., Ltd. Wiring board with semiconductor component
US7383629B2 (en) * 2004-11-19 2008-06-10 Endicott Interconnect Technologies, Inc. Method of making circuitized substrates utilizing smooth-sided conductive layers as part thereof
CN100441069C (zh) * 2005-01-21 2008-12-03 财团法人工业技术研究院 电子元件安装及安装方法
US20060165873A1 (en) * 2005-01-25 2006-07-27 Micron Technology, Inc. Plasma detection and associated systems and methods for controlling microfeature workpiece deposition processes
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
US20060237138A1 (en) * 2005-04-26 2006-10-26 Micron Technology, Inc. Apparatuses and methods for supporting microelectronic devices during plasma-based fabrication processes
EP1880422B1 (en) 2005-05-04 2011-08-03 Nxp B.V. A device comprising a sensor module
NL1029954C2 (nl) * 2005-09-14 2007-03-15 Assembleon Nv Werkwijze voor het verwarmen van een strookvormige drager alsmede een dergelijke inrichting.
US7759776B2 (en) * 2006-03-28 2010-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. Space transformer having multi-layer pad structures
JP4902248B2 (ja) * 2006-04-07 2012-03-21 株式会社日本マイクロニクス 電気的接続装置
JP4841298B2 (ja) * 2006-04-14 2011-12-21 株式会社日本マイクロニクス プローブシートの製造方法
JP4884821B2 (ja) * 2006-04-14 2012-02-29 株式会社日本マイクロニクス プローブシートおよび電気的接続装置
US7635643B2 (en) * 2006-04-26 2009-12-22 International Business Machines Corporation Method for forming C4 connections on integrated circuit chips and the resulting devices
JP2008082912A (ja) * 2006-09-28 2008-04-10 Micronics Japan Co Ltd 電気的接続装置
TW200816421A (en) * 2006-09-29 2008-04-01 Novatek Microelectronics Corp Chip package, chip structure and manufacturing process thereof
US7417310B2 (en) 2006-11-02 2008-08-26 Entorian Technologies, Lp Circuit module having force resistant construction
CN101262744B (zh) * 2007-03-08 2011-01-19 奈电软性科技电子(珠海)有限公司 假贴机
US20110019378A1 (en) * 2009-07-27 2011-01-27 Tod A. Byquist Composite micro-contacts
CN101661916B (zh) * 2009-09-18 2012-05-09 可富科技股份有限公司 重新布线层于软膜覆晶封装的结构
US8304290B2 (en) * 2009-12-18 2012-11-06 International Business Machines Corporation Overcoming laminate warpage and misalignment in flip-chip packages
US20110186989A1 (en) 2010-02-04 2011-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Bump Formation Process
US9142533B2 (en) 2010-05-20 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
EP2641208B1 (en) 2010-11-19 2020-04-29 Nagravision S.A. Method to detect cloned software
CN102064117B (zh) * 2010-11-19 2013-09-11 上海凯虹电子有限公司 小尺寸芯片的封装方法
CN102225500A (zh) * 2011-05-30 2011-10-26 昆山元崧电子科技有限公司 保险丝辅助焊接夹具
CN102323451A (zh) * 2011-05-30 2012-01-18 华南理工大学 一种检测互连焊点电迁移性能的方法及装置
US8240545B1 (en) * 2011-08-11 2012-08-14 Western Digital (Fremont), Llc Methods for minimizing component shift during soldering
US9831170B2 (en) * 2011-12-30 2017-11-28 Deca Technologies, Inc. Fully molded miniaturized semiconductor module
US9646923B2 (en) 2012-04-17 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices
US9425136B2 (en) 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9299674B2 (en) 2012-04-18 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect
JP5502139B2 (ja) * 2012-05-16 2014-05-28 日本特殊陶業株式会社 配線基板
US9111817B2 (en) 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
TWI490508B (zh) * 2012-12-17 2015-07-01 Princo Corp 軟性測試裝置及其測試方法
US20140239569A1 (en) 2013-02-26 2014-08-28 International Business Machines Corporation Universal clamping fixture to maintain laminate flatness during chip join
TWI467711B (zh) * 2013-09-10 2015-01-01 Chipbond Technology Corp 半導體結構
US20160029486A1 (en) * 2014-07-24 2016-01-28 Samsung Electro-Mechanics Co., Ltd. Solder joint structure and electronic component module including the same
EP3258752A4 (en) * 2015-02-13 2018-10-17 Pi-Crystal Incorporation Method for forming laminated circuit board, and laminated circuit board formed using same
US9875988B2 (en) 2015-10-29 2018-01-23 Semtech Corporation Semiconductor device and method of forming DCALGA package using semiconductor die with micro pillars
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10403577B1 (en) * 2018-05-03 2019-09-03 Invensas Corporation Dielets on flexible and stretchable packaging for microelectronics
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
KR102692970B1 (ko) * 2020-03-11 2024-08-07 동우 화인켐 주식회사 터치 센서 모듈 및 이를 포함하는 화상 표시 장치
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62117346A (ja) * 1985-11-18 1987-05-28 Fujitsu Ltd 半導体装置
US4967950A (en) * 1989-10-31 1990-11-06 International Business Machines Corporation Soldering method
JPH0417390A (ja) * 1990-05-10 1992-01-22 Matsushita Electric Ind Co Ltd 電子部品のボンディング方法
US5251806A (en) * 1990-06-19 1993-10-12 International Business Machines Corporation Method of forming dual height solder interconnections
US5130779A (en) * 1990-06-19 1992-07-14 International Business Machines Corporation Solder mass having conductive encapsulating arrangement
JPH0499393A (ja) * 1990-08-08 1992-03-31 Nec Corp 混成集積回路への電子部品の半田付方法
US5075965A (en) * 1990-11-05 1991-12-31 International Business Machines Low temperature controlled collapse chip attach process
JP2940269B2 (ja) * 1990-12-26 1999-08-25 日本電気株式会社 集積回路素子の接続方法
JPH04297091A (ja) * 1991-03-26 1992-10-21 Furukawa Electric Co Ltd:The 半田コートプリント回路基板とその製造方法
JPH0666314B2 (ja) * 1991-05-31 1994-08-24 インターナショナル・ビジネス・マシーンズ・コーポレイション バンプ形成方法及び装置
US5261155A (en) * 1991-08-12 1993-11-16 International Business Machines Corporation Method for bonding flexible circuit to circuitized substrate to provide electrical connection therebetween using different solders
US5297333A (en) * 1991-09-24 1994-03-29 Nec Corporation Packaging method for flip-chip type semiconductor device
JPH05152733A (ja) * 1991-11-30 1993-06-18 Suzuki Motor Corp 表面実装用プリント配線基板
US5289631A (en) * 1992-03-04 1994-03-01 Mcnc Method for testing, burn-in, and/or programming of integrated circuit chips
US5489750A (en) * 1993-03-11 1996-02-06 Matsushita Electric Industrial Co., Ltd. Method of mounting an electronic part with bumps on a circuit board
US5478420A (en) * 1994-07-28 1995-12-26 International Business Machines Corporation Process for forming open-centered multilayer ceramic substrates
AU3415095A (en) * 1994-09-06 1996-03-27 Sheldahl, Inc. Printed circuit substrate having unpackaged integrated circuit chips directly mounted thereto and method of manufacture
US5634268A (en) * 1995-06-07 1997-06-03 International Business Machines Corporation Method for making direct chip attach circuit card

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101573789B (zh) * 2006-12-28 2016-11-09 英特尔公司 包括其凸块形成位点上的焊料帽的微电子管芯及其制造方法

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US5729896A (en) 1998-03-24
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