CN110911542A - 晶片封装构造及其晶片 - Google Patents

晶片封装构造及其晶片 Download PDF

Info

Publication number
CN110911542A
CN110911542A CN201811148616.8A CN201811148616A CN110911542A CN 110911542 A CN110911542 A CN 110911542A CN 201811148616 A CN201811148616 A CN 201811148616A CN 110911542 A CN110911542 A CN 110911542A
Authority
CN
China
Prior art keywords
electrode
limiting
wafer
limiting groove
limiting wall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201811148616.8A
Other languages
English (en)
Inventor
谢庆堂
施政宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chipbond Technology Corp
Original Assignee
Chipbond Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipbond Technology Corp filed Critical Chipbond Technology Corp
Publication of CN110911542A publication Critical patent/CN110911542A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/54—Encapsulations having a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02175—Flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02185—Shape of the auxiliary member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/0219—Material of the auxiliary member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/06102—Disposition the bonding areas being at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape

Abstract

一种晶片封装构造，其用于微细晶片电性连接于基板，尤其是运用于发光二极管，该晶片封装构造的晶片包含本体及至少一个电极，该电极设置于该本体的表面，且显露于该表面，该电极具有限位槽及位于该限位槽周边的限位墙，该限位墙用以限制胶体中的至少一个导电粒子于该限位槽，且该晶片借由位于该限位槽中的该导电粒子电性连接该电极及基板的导接垫。

Description

晶片封装构造及其晶片
技术领域
本发明是关于一种晶片封装构造及其晶片，特别是运用于微细发光二极管的封装构造。
背景技术
在现有习知的技术中，会以具有多个导电粒子的导电胶电性连接晶片及基板，然而当该晶片体积逐渐微细化时，相对地也造成该晶片的多个电极被缩小接合面积。
由于在压接该晶片及该基板的制造过程中，具有所述导电粒子的该导电胶会因制造过程环境而具有流动性，相对地也造成了所述导电粒子会随着该导电胶的树脂流动。
由于该晶片的所述电极被缩小接合面积，因此随着该树脂而流动的所述导电粒子若未被限位于该晶片的该电极与该基板的导接垫之间时，在该树脂固化后，会造成该晶片无法与该基板电性连接，尤其是当该晶片为微细发光二极管时，更容易造成该发光二极管的电极端无法与该基板电性连接。
发明内容
本发明的一种晶片封装构造及其晶片，其主要目的是运用于微细晶片的电性连接，尤其是运用于微细发光二极管的电性连接。
本发明的一种晶片封装构造包含基板、晶片以及胶体，该晶片包含本体及第一电极，该本体具有表面，该第一电极设置于该表面，且显露于该表面，该第一电极具有第一限位槽及位于该第一限位槽周边的第一限位墙，该第一限位墙具有第一高度，该胶体设置于该基板与该晶片之间，该第一限位墙的该第一高度不大于该胶体中的第一导电粒子的直径，该第一限位墙将该胶体中的至少一个第一导电粒子限制于该第一限位槽，且该晶片以位于该第一限位槽中的第一导电粒子电性连接该第一电极及该基板的第一导接垫。
前述的晶片封装构造，其中该晶片另包含第二电极，该第二电极设置于该表面，且显露于该表面，该第二电极具有第二限位槽及位于该第二限位槽周边的第二限位墙，该第二限位墙具有第二高度，该第二限位墙的该第二高度不大于该胶体中的第二导电粒子的直径，该第二限位墙将该胶体中的该第二导电粒子限制于该第二限位槽，且该晶片以位于该第二限位槽中的该第二导电粒子电性连接该第二电极及该基板的第二导接垫。
前述的晶片封装构造，其中该表面包含高表面及低表面，该第一电极设置于该高表面，该第二电极设置于该低表面，该第一电极的第一显露表面与该第二电极的第二显露表面之间具有高度差，该高度差不大于该第一导电粒子的该直径。
前述的晶片封装构造，该高度差小于该第一导电粒子的该直径。
前述的晶片封装构造，其中该高度差界于0μm至8μm之间。
前述的晶片封装构造，其中该第一电极具有第一显露表面，该第一限位墙设置于该第一显露表面。
前述的晶片封装构造，其中该第一限位墙包含多个第一凸肋，所述第一凸肋环设于该第一限位槽周边，且相邻的该第一凸肋间具有第一缺口。
前述的晶片封装构造，其中该第二电极具有第二显露表面，该第二限位墙设置于该第二显露表面。
前述的晶片封装构造，其中该第二限位墙包含多个第二凸肋，所述第二凸肋环设于该第二限位槽周边，且相邻的该第二凸肋间具有第二缺口。
本发明的一种晶片包含本体以及第一电极，该本体具有表面，该第一电极，设置于该表面，且显露于该表面，该第一电极具有第一限位槽及位于该第一限位槽周边的第一限位墙，该第一限位墙具有第一高度，该第一限位墙的该高度不大于胶体中的导电粒子的直径，该第一限位墙用以限制该胶体中的至少一个导电粒子，以使该导电粒子被限位于该第一限位槽。
前述的晶片，其另包含第二电极，该第二电极设置于该表面，且显露于该表面，该第二电极具有第二限位槽及位于该第二限位槽周边的第二限位墙，该第二限位墙具有第二高度，该第二限位墙的该第二高度不大于该胶体中的该导电粒子的该直径，该第二限位墙用以限制该胶体中的该导电粒子于该第二限位槽。
前述的晶片，其中该表面包含高表面及低表面，该第一电极设置于该高表面，该第二电极设置于该低表面，该第一电极的第一显露表面与该第二电极第二显露表面之间具有高度差，该高度差不大于该导电粒子的该直径。
前述的晶片，其中该高度差小于该导电粒子的该直径。
前述的晶片，其中该高度差界于0μm至8μm之间。
前述的晶片，其中该第一电极具有第一显露表面，该第一限位墙设置于该第一显露表面。
前述的晶片，其中该第一限位墙包含多个第一凸肋，所述第一凸肋环设于该第一限位槽周边，且相邻的该第一凸肋间具有第一缺口。
前述的晶片，其中该第二电极具有第二显露表面，该第二限位墙设置于该第二显露表面。
前述的晶片，其中该第二限位墙包含多个第二凸肋，所述第二凸肋环设于该第二限位槽周边，且相邻的该第二凸肋间具有第二缺口。
本发明的一种晶片包含本体以及电极，该本体具有表面，该电极显露于该表面，该电极具有限位槽及位于该限位槽周边的限位墙，该限位墙用以限制至少一个导电粒子，以使该导电粒子被限位于该限位槽。
前述的晶片，其中该限位墙包含多个凸肋，所述凸肋环设于该限位槽周边，且相邻的该凸肋间具有缺口。
本发明借由该第一电极的该第一限位墙限制该胶体中的至少一个导电粒子于该第一限位槽，使该晶片压接该基板时，该第一导电粒子不会随着该胶体被挤压流动而发生位移，以使该晶片能以位于该第一限位槽中的该第一导电粒子电性连接该第一电极及该基板的该第一导接垫，本发明能避免该晶片无法电性连接该基板，尤其是运用于微细发光二极管的电性连接。
附图说明
图1：本发明的晶片封装构造的剖视图。
图2：本发明的晶片的底视图。
图3：本发明的晶片的底视图。
图4：本发明的晶片未压接于基板的剖视图。
【主要元件符号说明】
10：机具
100：基板 110：第一导接垫
120：第二导接垫 200：晶片
210：本体 211：表面
211a：高表面 211b：低表面
220：第一电极 220a：第一显露表面
221：第一限位槽 222：第一限位墙
222a：第一凸肋 222b：第一缺口
230：第二电极 230a：第二显露表面
231：第二限位槽 232：第二限位墙
232a：第二凸肋 232b：第二缺口
300：胶体 310：第一导电粒子
320：第二导电粒子 X：高度差
D1：直径 D2：直径
H1：第一高度 H2：第二高度
具体实施方式
请参阅图1，本发明的一种晶片封装构造其至少包含基板100、晶片200以及胶体300，在本实施例的图式中，以该晶片200为发光二极管(Light-emitting diode，LED)说明，但不以此为限制。
请参阅图1，在本实施例中，该基板100具有第一导接垫110及第二导接垫120，请参阅图1及图2，该晶片200包含本体210、第一电极220及第二电极230，该本体210具有表面211，该第一电极220及该第二电极230分别设置于该表面211，且分别显露于该表面211，该第一电极220具有第一显露表面220a、第一限位槽221及位于该第一限位槽221周边的第一限位墙222，该第二电极230具有第二显露表面230a、第二限位槽231及位于该第二限位槽231周边的第二限位墙232。
请参阅图1及图2，该第一限位墙222及该第二限位墙232的材料可选自于高分子材料、金属材料、非金属材料，当该第一限位墙222、该第二限位墙232与该第一电极220、该第二电极230为同一金属材料时，是在蚀刻制造过程中蚀刻金属层以形成该第一电极220、该第二电极230、该第一限位墙222及该第二限位墙232，当该第一限位墙222、该第二限位墙232与该第一电极220、该第二电极230为不同材料时，是在蚀刻制造过程中蚀刻金属层以形成该第一电极220及该第二电极230之前或之后，以电镀、印刷等制造过程形成该第一限位墙222及该第二限位墙232，或者在不同的实施例中，以图案化一光阻材料层(如曝光、显影等制造过程)形成该第一限位墙222及该第二限位墙232。
请参阅图1及图2，在本实施例中，该表面211包含高表面211a及低表面211b，该第一电极220设置于该高表面211a，该第二电极230设置于该低表面211b，该第一电极220的该第一显露表面220a与该第二电极230的该第二显露表面230a之间具有一高度差X，该高度差X界于0μm至8μm之间，或者，在不同的实施例中，该高度差X界于0.1μm至8μm之间。
请参阅图1及图2，该第一限位墙222设置于该第一电极220的该第一显露表面220a，该第一限位墙222具有第一高度H1，该第二限位墙232设置于该第二电极230的该第二显露表面230a，该第二限位墙232具有第二高度H2。
请参阅图3，在另一实施例中，该第一限位墙222包含多个第一凸肋222a，所述第一凸肋222a环设于该第一限位槽221周边，且相邻的该第一凸肋222a间具有第一缺口222b，该第二限位墙232包含多个第二凸肋232a，所述第二凸肋232a环设于该第二限位槽231周边，且相邻的该第二凸肋232a间具有第二缺口232b。
请参阅图1及图4，该胶体300设置于该基板100与该晶片200之间，在本实施例中，该胶体300选自于异方性导电膜(Anisotropic Conductive Film,ACF)，该胶体300是由树脂及多个导电粒子混合合成。
请参阅图4，在本实施例中，在压合该晶片200及该基板100前，该胶体300为薄膜形态，当以机具10热压合该晶片200及该基板100时，该晶片200触压该胶体300，且在热加工环境中使该胶体300具有流动性，该第一限位墙222用以将该胶体300中的至少一个第一导电粒子310限制于该第一限位槽221，该第二限位墙232用以该胶体300中的至少一个第二导电粒子320限制于该第二限位槽231，该第一导电粒子310具有直径D1，该第二导电粒子320具有直径D2。
请参阅图1及图4，在本实施例中，该第一限位墙222的该第一高度H1不大于该胶体300中的该第一导电粒子310的该直径D1，且较佳地，该第一电极220的该第一显露表面220a与该第二电极230的该第二显露表面230a之间的该高度差X不大于该第一导电粒子310的该直径D1，更佳地，该高度差X小于该第一导电粒子310的该直径D1。
请参阅图1及图4，在本实施例中，该第二限位墙232的该第二高度H2不大于该胶体300中的该第二导电粒子320的该直径D2。
请参阅图1及图4，在压合该晶片200及该基板100时，该晶片200借由该第一限位墙222限制该第一导电粒子310于该第一限位槽221，以及借由该第二限位墙232限制该第二导电粒子320于该第二限位槽231，因此使得该第一导电粒子310及该第二导电粒子320不会随着具有流动性的该胶体300流动，以使该晶片200以位于该第一限位槽221中的该第一导电粒子310电性连接该晶片200的该第一电极220及该基板100的该第一导接垫110，且使该晶片200以位于该第二限位槽231中的该第二导电粒子320电性连接该第二电极230及该基板100的该第二导接垫120。
请参阅图1、图3及图4，由于相邻的该第一凸肋222a间具有该第一缺口222b，以及相邻的该第二凸肋232a间具有该第二缺口232b，因此在压合该晶片200及该基板100时，该晶片200触压具有流动性的该胶体300，并使位于该第一导电粒子310与该第一电极220之间的该胶体300的该树脂可经由该第一缺口222b被挤出该第一限位槽221，以及使位于该第二导电粒子320与该第二电极230之间的该胶体300的该树脂可经由该第二缺口232b被挤出该第二限位槽231，以避免位于该第一限位槽221中及该第二限位槽231的该树脂成为该晶片200与该基板100的压合阻力，而造成该晶片200倾斜。
本发明借由该第一电极220的该第一限位墙222限制该胶体300中的至少一个第一导电粒子310以及借由该第二电极230的该第二限位墙232限制该胶体300中的至少一个第二导电粒子320，使该晶片200压接该基板100时，该第一导电粒子310及该第二导电粒子320不会随着该胶体300被挤压流动而发生位移，即能避免导致该第一导电粒子310离开该第一电极220，或避免导致该第二导电粒子320离开该第二电极230，以确保该晶片200能以被限位于该第一限位槽221中的至少一个第一导电粒子310及被限位于该第二限位槽231中的至少一个第二导电粒子320电性连接该基板100。
以上所述，仅是本发明的较佳实施例而已，并非对本发明做任何形式上的限制，虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的技术内容做出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (20)

1.一种晶片封装构造，其特征在于包含：
基板；
晶片，包含本体及第一电极，该本体具有表面，该第一电极设置于该表面，且显露于该表面，该第一电极具有第一限位槽及位于该第一限位槽周边的第一限位墙，该第一限位墙具有第一高度；以及
胶体，设置于该基板与该晶片之间，该第一限位墙的该第一高度不大于该胶体中的第一导电粒子的直径，该第一限位墙将该胶体中的至少一个第一导电粒子限制于该第一限位槽，且该晶片以位于该第一限位槽中的该第一导电粒子电性连接该第一电极及该基板的第一导接垫。
2.根据权利要求1所述的晶片封装构造，其特征在于：其中该晶片另包含第二电极，该第二电极设置于该表面，且显露于该表面，该第二电极具有第二限位槽及位于该第二限位槽周边的第二限位墙，该第二限位墙具有第二高度，该第二限位墙的该第二高度不大于该胶体中的第二导电粒子的直径，该第二限位墙将该胶体中的该第二导电粒子限制于该第二限位槽，且该晶片以位于该第二限位槽中的该第二导电粒子电性连接该第二电极及该基板的第二导接垫。
3.根据权利要求2所述的晶片封装构造，其特征在于：其中该表面包含高表面及低表面，该第一电极设置于该高表面，该第二电极设置于该低表面，该第一电极的第一显露表面与该第二电极的第二显露表面之间具有高度差，该高度差不大于该第一导电粒子的该直径。
4.根据权利要求3所述的晶片封装构造，其特征在于：该高度差小于该第一导电粒子的该直径。
5.根据权利要求3所述的晶片封装构造，其特征在于：其中该高度差界于0μm至8μm之间。
6.根据权利要求1所述的晶片封装构造，其特征在于：其中该第一电极具有第一显露表面，该第一限位墙设置于该第一显露表面。
7.根据权利要求1所述的晶片封装构造，其特征在于：其中该第一限位墙包含多个第一凸肋，所述第一凸肋环设于该第一限位槽周边，且相邻的该第一凸肋间具有第一缺口。
8.根据权利要求2所述的晶片封装构造，其特征在于：其中该第二电极具有第二显露表面，该第二限位墙设置于该第二显露表面。
9.根据权利要求2所述的晶片封装构造，其特征在于：其中该第二限位墙包含多个第二凸肋，所述第二凸肋环设于该第二限位槽周边，且相邻的该第二凸肋间具有第二缺口。
10.一种晶片，其特征在于包含：
本体，具有表面；以及
第一电极，设置于该表面，且显露于该表面，该第一电极具有第一限位槽及位于该第一限位槽周边的第一限位墙，该第一限位墙具有第一高度，该第一限位墙的该高度不大于胶体中的导电粒子的直径，该第一限位墙用以限制该胶体中的至少一个导电粒子，以使该导电粒子被限位于该第一限位槽。
11.根据权利要求10所述的晶片，其特征在于：其另包含第二电极，该第二电极设置于该表面，且显露于该表面，该第二电极具有第二限位槽及位于该第二限位槽周边的第二限位墙，该第二限位墙具有第二高度，该第二限位墙的该第二高度不大于该胶体中的该导电粒子的该直径，该第二限位墙用以限制该胶体中的该导电粒子于该第二限位槽。
12.根据权利要求10所述的晶片，其特征在于：其中该表面包含高表面及低表面，该第一电极设置于该高表面，该第二电极设置于该低表面，该第一电极的第一显露表面与该第二电极第二显露表面之间具有高度差，该高度差不大于该导电粒子的该直径。
13.根据权利要求12所述的晶片，其特征在于：其中该高度差小于该导电粒子的该直径。
14.根据权利要求12所述的晶片，其特征在于：其中该高度差界于0μm至8μm之间。
15.根据权利要求10所述的晶片，其特征在于：其中该第一电极具有第一显露表面，该第一限位墙设置于该第一显露表面。
16.根据权利要求10所述的晶片，其特征在于：其中该第一限位墙包含多个第一凸肋，所述第一凸肋环设于该第一限位槽周边，且相邻的该第一凸肋间具有第一缺口。
17.根据权利要求11所述的晶片，其特征在于：其中该第二电极具有第二显露表面，该第二限位墙设置于该第二显露表面。
18.根据权利要求11所述的晶片，其特征在于：其中该第二限位墙包含多个第二凸肋，所述第二凸肋环设于该第二限位槽周边，且相邻的该第二凸肋间具有第二缺口。
19.一种晶片，其特征在于包含：
本体，具有表面；以及
电极，显露于该表面，该电极具有限位槽及位于该限位槽周边的限位墙，该限位墙用以限制至少一个导电粒子，以使该导电粒子被限位于该限位槽。
20.根据权利要求19所述的晶片，其特征在于：其中该限位墙包含多个凸肋，所述凸肋环设于该限位槽周边，且相邻的该凸肋间具有缺口。
CN201811148616.8A 2018-09-14 2018-09-29 晶片封装构造及其晶片 Pending CN110911542A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW107132548 2018-09-14
TW107132548A TWI671921B (zh) 2018-09-14 2018-09-14 晶片封裝構造及其晶片

Publications (1)

Publication Number Publication Date
CN110911542A true CN110911542A (zh) 2020-03-24

Family

ID=65279415

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811148616.8A Pending CN110911542A (zh) 2018-09-14 2018-09-29 晶片封装构造及其晶片

Country Status (7)

Country Link
US (1) US10797213B2 (zh)
EP (1) EP3624206B1 (zh)
JP (1) JP2020047909A (zh)
KR (1) KR102223668B1 (zh)
CN (1) CN110911542A (zh)
PT (1) PT3624206T (zh)
TW (1) TWI671921B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210019323A (ko) * 2019-08-12 2021-02-22 삼성전자주식회사 마이크로 엘이디 디스플레이 및 이의 제작 방법
CN111048499B (zh) * 2019-12-16 2022-05-13 业成科技（成都）有限公司 微发光二极管显示面板及其制备方法
US11901497B2 (en) * 2019-12-24 2024-02-13 Seoul Viosys Co., Ltd. Method of repairing light emitting device, apparatus for repairing light emitting device, and display panel having repaired light emitting device
KR20220164770A (ko) * 2020-05-14 2022-12-13 엘지전자 주식회사 반도체 발광소자 및 이를 포함하는 디스플레이 장치

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1093160A2 (en) * 1999-10-12 2001-04-18 Sony Chemicals Corporation Connecting material for anisotropically electroconductive connection
TW536823B (en) * 2000-11-30 2003-06-11 Koninkl Philips Electronics Nv Assembly with connecting structure
CN1624733A (zh) * 2003-10-24 2005-06-08 三星Sdi株式会社 互连器和等离子体显示装置以及其制造方法
CN1723590A (zh) * 2003-06-25 2006-01-18 日立化成工业株式会社 电路连接材料、使用其的薄膜状电路连接材料、电路构件的连接结构及其制造方法
CN1747143A (zh) * 2004-09-07 2006-03-15 日月光半导体制造股份有限公司 适用于透明封装的基板条
JP2007067134A (ja) * 2005-08-31 2007-03-15 Seiko Epson Corp 実装部品、実装構造、及び実装構造の製造方法
CN101478305A (zh) * 2009-01-08 2009-07-08 深圳市中显微电子有限公司 电容式触摸屏及其制作方法
TW200949390A (en) * 2008-05-27 2009-12-01 Hannstar Display Corp Metal bump structure and package structure using the same
JP2010027847A (ja) * 2008-07-18 2010-02-04 Sharp Corp 半導体素子の実装構造およびそれを備えた表示装置
CN102148170A (zh) * 2009-11-09 2011-08-10 友达光电股份有限公司 一种基板贴合方法
CN103715210A (zh) * 2012-10-09 2014-04-09 胜开科技股份有限公司 高解析相机模块的结构及制造方法
CN103943640A (zh) * 2013-01-22 2014-07-23 胜开科技股份有限公司 降低光学单元倾斜度的影像感测器制造方法
CN105934816A (zh) * 2014-02-03 2016-09-07 迪睿合株式会社 连接体
JP2017004715A (ja) * 2015-06-09 2017-01-05 デクセリアルズ株式会社 異方性導電接続構造体、異方性導電材料、および異方性導電接続方法
CN206497881U (zh) * 2017-01-25 2017-09-15 深圳市森邦半导体有限公司 一种芯片封装结构
CN108350320A (zh) * 2015-11-04 2018-07-31 日立化成株式会社 粘接剂组合物和结构体
CN108476591A (zh) * 2015-06-16 2018-08-31 迪睿合株式会社 连接体、连接体的制造方法、检测方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100232678B1 (ko) * 1996-12-18 1999-12-01 구본준 돌기가 형성된 범프 및 그 제조방법
JP2004158701A (ja) * 2002-11-07 2004-06-03 Seiko Epson Corp 素子チップ実装用のバンプ構造及びその形成方法
JP4115832B2 (ja) 2002-12-27 2008-07-09 東芝松下ディスプレイテクノロジー株式会社 半導体素子及び液晶表示パネル
JP2005072202A (ja) * 2003-08-22 2005-03-17 Seiko Epson Corp 端子電極、配線基板、半導体装置、半導体モジュール、電子機器、端子電極の製造方法および半導体モジュールの製造方法
KR101062568B1 (ko) * 2009-06-11 2011-09-06 주식회사 네패스 플립칩 반도체 패키지 및 그 제조 방법
JP5916334B2 (ja) * 2011-10-07 2016-05-11 デクセリアルズ株式会社 異方性導電接着剤及びその製造方法、発光装置及びその製造方法
JP2014179569A (ja) * 2013-03-15 2014-09-25 Nichia Chem Ind Ltd 発光装置およびその製造方法
JP5985414B2 (ja) 2013-02-19 2016-09-06 デクセリアルズ株式会社 異方性導電接着剤、発光装置及び異方性導電接着剤の製造方法
JP6349910B2 (ja) * 2014-04-23 2018-07-04 日亜化学工業株式会社 発光装置及びその製造方法
JP6945276B2 (ja) * 2016-03-31 2021-10-06 デクセリアルズ株式会社 異方性導電接続構造体

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1093160A2 (en) * 1999-10-12 2001-04-18 Sony Chemicals Corporation Connecting material for anisotropically electroconductive connection
TW536823B (en) * 2000-11-30 2003-06-11 Koninkl Philips Electronics Nv Assembly with connecting structure
CN1723590A (zh) * 2003-06-25 2006-01-18 日立化成工业株式会社 电路连接材料、使用其的薄膜状电路连接材料、电路构件的连接结构及其制造方法
CN1624733A (zh) * 2003-10-24 2005-06-08 三星Sdi株式会社 互连器和等离子体显示装置以及其制造方法
CN1747143A (zh) * 2004-09-07 2006-03-15 日月光半导体制造股份有限公司 适用于透明封装的基板条
JP2007067134A (ja) * 2005-08-31 2007-03-15 Seiko Epson Corp 実装部品、実装構造、及び実装構造の製造方法
TW200949390A (en) * 2008-05-27 2009-12-01 Hannstar Display Corp Metal bump structure and package structure using the same
JP2010027847A (ja) * 2008-07-18 2010-02-04 Sharp Corp 半導体素子の実装構造およびそれを備えた表示装置
CN101478305A (zh) * 2009-01-08 2009-07-08 深圳市中显微电子有限公司 电容式触摸屏及其制作方法
CN102148170A (zh) * 2009-11-09 2011-08-10 友达光电股份有限公司 一种基板贴合方法
CN103715210A (zh) * 2012-10-09 2014-04-09 胜开科技股份有限公司 高解析相机模块的结构及制造方法
CN103943640A (zh) * 2013-01-22 2014-07-23 胜开科技股份有限公司 降低光学单元倾斜度的影像感测器制造方法
CN105934816A (zh) * 2014-02-03 2016-09-07 迪睿合株式会社 连接体
JP2017004715A (ja) * 2015-06-09 2017-01-05 デクセリアルズ株式会社 異方性導電接続構造体、異方性導電材料、および異方性導電接続方法
CN108476591A (zh) * 2015-06-16 2018-08-31 迪睿合株式会社 连接体、连接体的制造方法、检测方法
CN108350320A (zh) * 2015-11-04 2018-07-31 日立化成株式会社 粘接剂组合物和结构体
CN206497881U (zh) * 2017-01-25 2017-09-15 深圳市森邦半导体有限公司 一种芯片封装结构

Also Published As

Publication number Publication date
EP3624206B1 (en) 2021-06-23
EP3624206A1 (en) 2020-03-18
TWI671921B (zh) 2019-09-11
JP2020047909A (ja) 2020-03-26
US10797213B2 (en) 2020-10-06
KR102223668B1 (ko) 2021-03-05
US20200091385A1 (en) 2020-03-19
KR20200031978A (ko) 2020-03-25
PT3624206T (pt) 2021-09-30
TW202011619A (zh) 2020-03-16

Similar Documents

Publication Publication Date Title
CN110911542A (zh) 晶片封装构造及其晶片
JP4568215B2 (ja) 回路装置および回路装置の製造方法
CN107799483B (zh) 半导体封装结构及其制造方法
JP4757790B2 (ja) 半導体素子の実装構造及びプリント回路基板
CN111211059A (zh) 电子封装件及其制法与散热件
JP2010097982A (ja) 発光装置
JP2017175093A (ja) 電子部品、接続体、電子部品の設計方法
JP2018010949A (ja) 半導体発光装置および半導体発光装置の製造方法
JP2015099874A (ja) 電子素子パッケージ、およびその製造方法
KR102348352B1 (ko) 발광 장치
WO2015076281A1 (ja) 発光装置、発光装置製造方法
KR101009187B1 (ko) 인쇄회로기판 및 그 제조방법
US20110127676A1 (en) Lead pin for semiconductor package and semiconductor package
JP4759357B2 (ja) Ｌｅｄ光源モジュール
US20130020607A1 (en) Led module and method for manufacturing the same
KR101450761B1 (ko) 반도체 패키지, 적층형 반도체 패키지 및 반도체 패키지의 제조방법
TWI425676B (zh) 半導體封裝結構
US20220216255A1 (en) Image sensor package having inner and outer joint members
CN209880583U (zh) 半导体封装结构
JP5834900B2 (ja) 電子機器、コネクタ、及びコネクタの製造方法
JP2000216193A (ja) フリップチップ接続構造および接続方法
CN105990155A (zh) 芯片封装基板、芯片封装结构及其制作方法
KR102427092B1 (ko) 열 정보 표지를 갖는 반도체 장치
JP4840305B2 (ja) 半導体装置の製造方法
JP2024031399A (ja) 半導体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20200324

WD01 Invention patent application deemed withdrawn after publication