TWI671921B - 晶片封裝構造及其晶片 - Google Patents

晶片封裝構造及其晶片 Download PDF

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TWI671921B
TWI671921B TW107132548A TW107132548A TWI671921B TW I671921 B TWI671921 B TW I671921B TW 107132548 A TW107132548 A TW 107132548A TW 107132548 A TW107132548 A TW 107132548A TW I671921 B TWI671921 B TW I671921B
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Prior art keywords
electrode
limiting
wall
wafer
disposed
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TW107132548A
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TW202011619A (zh
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謝慶堂
Chin-Tang Hsieh
施政宏
Cheng-Hung Shih
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頎邦科技股份有限公司
Chipbond Technology Corporation
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Application filed by 頎邦科技股份有限公司, Chipbond Technology Corporation filed Critical 頎邦科技股份有限公司
Priority to TW107132548A priority Critical patent/TWI671921B/zh
Priority to CN201811148616.8A priority patent/CN110911542A/zh
Priority to KR1020190009206A priority patent/KR102223668B1/ko
Priority to JP2019010249A priority patent/JP2020047909A/ja
Priority to US16/260,528 priority patent/US10797213B2/en
Priority to EP19154965.8A priority patent/EP3624206B1/en
Priority to PT191549658T priority patent/PT3624206T/pt
Application granted granted Critical
Publication of TWI671921B publication Critical patent/TWI671921B/zh
Publication of TW202011619A publication Critical patent/TW202011619A/zh

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Abstract

一種晶片封裝構造，其用於微細晶片電性連接於一基板，尤其是運用於發光二極體，該晶片封裝構造的一晶片包含一本體及至少一電極，該電極設置於該本體的一表面，且顯露於該表面，該電極具有一限位槽及一位於該限位槽周邊的限位牆，該限位牆用以限制一膠體中的至少一導電粒子於該限位槽，且該晶片藉由位於該限位槽中的該導電粒子電性連接該電極及一基板的一導接墊。

Description

晶片封裝構造及其晶片
本發明是關於一種晶片封裝構造及其晶片，特別是運用於微細發光二極體的封裝構造。
在習知的技術中，會以一具有複數個導電粒子的導電膠電性連接一晶片及一基板，然而當該晶片體積逐漸微細化時，相對地也造成該晶片的複數個電極被縮小接合面積。
由於在壓接該晶片及該基板的製程中，具有該些導電粒子的該導電膠會因製程環境而具有流動性，相對地也造成了該些導電粒子會隨著該導電膠的一樹脂流動。
由於該晶片的該些電極被縮小接合面積，因此隨著該樹脂而流動的該些導電粒子若未被限位於該晶片的該電極與該基板的一導接墊之間時，在該樹脂固化後，會造成該晶片無法與該基板電性連接，尤其是當該晶片為一微細發光二極體時，更容易造成該發光二極體的電極端無法與該基板電性連接。
本發明的一種晶片封裝構造及其晶片，其主要目的是運用於微細 晶片的電性連接，尤其是運用於微細發光二極體的電性連接。
本發明的一種晶片封裝構造包含一基板、一晶片以及一膠體，該晶片包含一本體及一第一電極，該本體具有一表面，該第一電極設置於該表面，且顯露於該表面，該第一電極具有一第一限位槽及一位於該第一限位槽周邊的第一限位牆，該第一限位牆具有一第一高度，該膠體設置於該基板與該晶片之間，該第一限位牆的該第一高度不大於該膠體中的一第一導電粒子的一直徑，該第一限位牆將該膠體中的至少一第一導電粒子限制於該第一限位槽，且該晶片以位於該第一限位槽中的該第一導電粒子電性連接該第一電極及該基板的一第一導接墊。
本發明的一種晶片包含一本體以及一第一電極，該本體具有一表面，該第一電極設置於該表面，且顯露於該表面，該第一電極具有一第一限位槽及一位於該第一限位槽周邊的第一限位牆，該第一限位牆具有一第一高度，該第一限位牆的該第一高度不大於一膠體中的一導電粒子的一直徑，該第一限位牆用以限制該膠體中的至少一導電粒子，以使該導電粒子被限位於該第一限位槽。
本發明的一種晶片包含一本體以及一電極，該本體具有一表面，該電極顯露於該表面，該電極具有一限位槽及一位於該限位槽周邊的限位牆，該限位牆用以限制至少一導電粒子，以使該導電粒子被限位於該限位槽。
本發明藉由該第一電極的該第一限位牆限制該膠體中的至少一導電粒子於該第一限位槽，使該晶片壓接該基板時，該第一導電粒子不會隨著該膠體被擠壓流動而發生位移，以使該晶片能以位於該第一限位槽中的該第一導電粒子電性連接該第一電極及該基板的該第一導接墊，本發明能避免該晶片無法電性連接該基板，尤其是運用於微細發光二極體的電性連接。
請參閱第1圖，本發明的一種晶片封裝構造其至少包含一基板100、一晶片200以及一膠體300，在本實施例的圖式中，以該晶片200為一發光二極體(Light-emitting diode，LED)說明，但不以此為限制。
請參閱第1圖，在本實施例中，該基板100具有一第一導接墊110及一第二導接墊120，請參閱第1及2圖，該晶片200包含一本體210、一第一電極220及一第二電極230，該本體210具有一表面211，該第一電極220及該第二電極230分別設置於該表面211，且分別顯露於該表面211，該第一電極220具有一第一顯露表面220a、一第一限位槽221及一位於該第一限位槽221周邊的第一限位牆222，該第二電極230具有一第二顯露表面230a、一第二限位槽231及一位於該第二限位槽231周邊的第二限位牆232。
請參閱第1及2圖，該第一限位牆222及該第二限位牆232的材料可選自於高分子材料、金屬材料、非金屬材料，當該第一限位牆222、該第二限位牆232與該第一電極220、該第二電極230為同一金屬材料時，是在一蝕刻製程中 蝕刻一金屬層以形成該第一電極220、該第二電極230、該第一限位牆222及該第二限位牆232，當該第一限位牆222、該第二限位牆232與該第一電極220、該第二電極230為不同材料時，是在一蝕刻製程中蝕刻一金屬層以形成該第一電極220及該第二電極230之前或之後，以電鍍、印刷等製程形成該第一限位牆222及該第二限位牆232，或者在不同的實施例中，以圖案化一光阻材料層(如曝光、顯影等製程)形成該第一限位牆222及該第二限位牆232。
請參閱第1及2圖，在本實施例中，該表面211包含一高表面211a及一低表面211b，該第一電極220設置於該高表面211a，該第二電極230設置於該低表面211b，該第一電極220的該第一顯露表面220a與該第二電極230的該第二顯露表面230a之間具有一高度差X，該高度差X介於0μm至8μm之間，或者，在不同的實施例中，該高度差X介於0.1μm至8μm之間。
請參閱第1及2圖，該第一限位牆222設置於該第一電極220的該第一顯露表面220a，該第一限位牆222具有一第一高度H1，該第二限位牆232設置於該第二電極230的該第二顯露表面230a，該第二限位牆232具有一第二高度H2。
請參閱第3圖，在另一實施例中，該第一限位牆222包含複數個第一凸肋222a，該些第一凸肋222a環設於該第一限位槽221周邊，且相鄰的該第一凸肋222a間具有一第一缺口222b，該第二限位牆232包含複數個第二凸肋232a，該些第二凸肋232a環設於該第二限位槽231周邊，且相鄰的該第二凸肋232a間具有一第二缺口232b。
請參閱第1及4圖，該膠體300設置於該基板100與該晶片200之間，在本實施例中，該膠體300選自於異方性導電膜(Anisotropic Conductive Film,ACF)，該膠體300是由樹脂及複數個導電粒子混合合成。
請參閱第4圖，在本實施例中，在壓合該晶片200及該基板100前，該膠體300為一薄膜形態，當以一機具10熱壓合該晶片200及該基板100時，該晶片200觸壓該膠體300，且在熱加工環境中使該膠體300具有流動性，該第一限位牆222用以將該膠體300中的至少一第一導電粒子310限制於該第一限位槽221，該第二限位牆232用以該膠體300中的至少一第二導電粒子320限制於該第二限位槽231，該第一導電粒子310具有一直徑D1，該第二導電粒子320具有一直徑D2。
請參閱第1及4圖，在本實施例中，該第一限位牆222的該第一高度H1不大於該膠體300中的該第一導電粒子310的該直徑D1，且較佳地，該第一電極220的該第一顯露表面220a與該第二電極230的該第二顯露表面230a之間的該高度差X不大於該第一導電粒子310的該直徑D1，更佳地，該高度差X小於該第一導電粒子310的該直徑D1。
請參閱第1及4圖，在本實施例中，該第二限位牆232的該第二高度H2不大於該膠體300中的該第二導電粒子320的該直徑D2。
請參閱第1及4圖，在壓合該晶片200及該基板100時，該晶片200藉由該第一限位牆222限制該第一導電粒子310於該第一限位槽221，以及藉由該第二限位牆232限制該第二導電粒子320於該第二限位槽231，因此使得該第一導電粒子310及該第二導電粒子320不會隨著具有流動性的該膠體300流動，以使該晶片200以位於該第一限位槽221中的該第一導電粒子310電性連接該晶片200的該第一電極220及該基板100的該第一導接墊110，且使該晶片200以位於該第二限位槽231中的該第二導電粒子320電性連接該第二電極230及該基板100的該第二導接墊120。
請參閱第1、3及4圖，由於相鄰的該第一凸肋222a間具有該第一缺口222b，以及相鄰的該第二凸肋232a間具有該第二缺口232b，因此在壓合該晶片200及該基板100時，該晶片200觸壓具有流動性的該膠體300，並使位於該第一導電粒子310與該第一電極220之間的該膠體300的該樹脂可經由該第一缺口222b被擠出該第一限位槽221，以及使位於該第二導電粒子320與該第二電極230之間的該膠體300的該樹脂可經由該第二缺口232b被擠出該第二限位槽231，以避免位於該第一限位槽221中及該第二限位槽231的該樹脂成為該晶片200與該基板100的壓合阻力，而造成該晶片200傾斜。
本發明藉由該第一電極220的該第一限位牆222限制該膠體300中的至少一第一導電粒子310以及藉由該第二電極230的該第二限位牆232限制該膠體300中的至少一第二導電粒子320，使該晶片200壓接該基板100時，該第一導電粒子310及該第二導電粒子320不會隨著該膠體300被擠壓流動而發生位移，即能避免導致該第一導電粒子310離開該第一電極220，或避免導致該第二導電粒子320離開該第二電極230，以確保該晶片200能以被限位於該第一限位槽221中的至少一第一導電粒子310及被限位於該第二限位槽231中的至少一第二導電粒子320電性連接該基板100。
本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。
10‧‧‧機具
100‧‧‧基板
110‧‧‧第一導接墊
120‧‧‧第二導接墊
200‧‧‧晶片
210‧‧‧本體
211‧‧‧表面
211a‧‧‧高表面
211b‧‧‧低表面
220‧‧‧第一電極
220a‧‧‧第一顯露表面
221‧‧‧第一限位槽
222‧‧‧第一限位牆
222a‧‧‧第一凸肋
222b‧‧‧第一缺口
230‧‧‧第二電極
230a‧‧‧第二顯露表面
231‧‧‧第二限位槽
232‧‧‧第二限位牆
232a‧‧‧第二凸肋
232b‧‧‧第二缺口
300‧‧‧膠體
310‧‧‧第一導電粒子
320‧‧‧第二導電粒子
X‧‧‧高度差
D1‧‧‧直徑
D2‧‧‧直徑
H1‧‧‧第一高度
H2‧‧‧第二高度
第1圖：本發明的晶片封裝構造的剖視圖。
第2圖：本發明的晶片的底視圖。
第3圖：本發明的晶片的底視圖。
第4圖：本發明的晶片未壓接於基板的剖視圖。

Claims (18)

  1. 一種晶片封裝構造，包含：一基板；一晶片，包含一本體及一第一電極，該本體具有一表面，該第一電極設置於該表面，且顯露於該表面，該第一電極具有一第一顯露表面、一第一限位槽及一位於該第一限位槽周邊的第一限位牆，該第一限位牆設置於該第一顯露表面且具有一第一高度；以及一膠體，設置於該基板與該晶片之間，該第一限位牆的該第一高度不大於該膠體中的一第一導電粒子的一直徑，該第一限位牆將該膠體中的至少一第一導電粒子限制於該第一限位槽，且該晶片以位於該第一限位槽中的該第一導電粒子電性連接該第一電極及該基板的一第一導接墊。
  2. 如申請專利範圍第1項所述之晶片封裝構造，其中該晶片另包含一第二電極，該第二電極設置於該表面，且顯露於該表面，該第二電極具有一第二限位槽及一位於該第二限位槽周邊的第二限位牆，該第二限位牆具有一第二高度，該第二限位牆的該第二高度不大於該膠體中的一第二導電粒子的一直徑，該第二限位牆將該膠體中的該第二導電粒子限制於該第二限位槽，且該晶片以位於該第二限位槽中的該第二導電粒子電性連接該第二電極及該基板的一第二導接墊。
  3. 如申請專利範圍第2項所述之晶片封裝構造，其中該表面包含一高表面及一低表面，該第一電極設置於該高表面，該第二電極設置於該低表面，該第一電極的一第一顯露表面與該第二電極的一第二顯露表面之間具有一高度差，該高度差不大於該第一導電粒子的該直徑。
  4. 如申請專利範圍第3項所述之晶片封裝構造，其中該高度差小於該第一導電粒子的該直徑。
  5. 如申請專利範圍第3項所述之晶片封裝構造，其中該高度差介於0μm至8μm之間。
  6. 如申請專利範圍第1項所述之晶片封裝構造，其中該第一限位牆包含複數個第一凸肋，該些第一凸肋環設於該第一限位槽周邊，且相鄰的該第一凸肋間具有一第一缺口。
  7. 如申請專利範圍第2項所述之晶片封裝構造，其中該第二電極具有一第二顯露表面，該第二限位牆設置於該第二顯露表面。
  8. 如申請專利範圍第2項所述之晶片封裝構造，其中該第二限位牆包含複數個第二凸肋，該些第二凸肋環設於該第二限位槽周邊，且相鄰的該第二凸肋間具有一第二缺口。
  9. 一種晶片，包含：一本體，具有一表面；以及一第一電極，設置於該表面且顯露於該表面，該第一電極具有一第一顯露表面、一第一限位槽及一位於該第一限位槽周邊的第一限位牆，該第一限位牆設置於該第一顯露表面且具有一第一高度，該第一限位牆的該第一高度不大於一膠體中的一導電粒子的一直徑，該第一限位牆用以限制該膠體中的至少一導電粒子，以使該導電粒子被限位於該第一限位槽。
  10. 如申請專利範圍第9項所述之晶片，其另包含一第二電極，該第二電極設置於該表面，且顯露於該表面，該第二電極具有一第二限位槽及一位於該第二限位槽周邊的第二限位牆，該第二限位牆具有一第二高度，該第二限位牆的該第二高度不大於該膠體中的該導電粒子的該直徑，該第二限位牆用以限制該膠體中的該導電粒子於該第二限位槽。
  11. 如申請專利範圍第10項所述之晶片，其中該表面包含一高表面及一低表面，該第一電極設置於該高表面，該第二電極設置於該低表面，該第一電極的一第一顯露表面與該第二電極一第二顯露表面之間具有一高度差，該高度差不大於該導電粒子的該直徑。
  12. 如申請專利範圍第11項所述之晶片，其中該高度差小於該導電粒子的該直徑。
  13. 如申請專利範圍第11項所述之晶片，其中該高度差介於0μm至8μm之間。
  14. 如申請專利範圍第9項所述之晶片，其中該第一限位牆包含複數個第一凸肋，該些第一凸肋環設於該第一限位槽周邊，且相鄰的該第一凸肋間具有一第一缺口。
  15. 如申請專利範圍第10項所述之晶片，其中該第二電極具有一第二顯露表面，該第二限位牆設置於該第二顯露表面。
  16. 如申請專利範圍第10項所述之晶片，其中該第二限位牆包含複數個第二凸肋，該些第二凸肋環設於該第二限位槽周邊，且相鄰的該第二凸肋間具有一第二缺口。
  17. 一種晶片，包含：一本體，具有一表面；以及一電極，顯露於該表面，該電極具有一顯露表面、一限位槽及一位於該限位槽周邊的限位牆，該限位牆設置於該顯露表面，用以限制至少一導電粒子，以使該導電粒子被限位於該限位槽。
  18. 如申請專利範圍第17項所述之晶片，其中該限位牆包含複數個凸肋，該些凸肋環設於該限位槽周邊，且相鄰的該凸肋間具有一缺口。
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