CN105051891A - 包含导电底部填充材料的半导体装置及封装以及相关方法 - Google Patents

包含导电底部填充材料的半导体装置及封装以及相关方法 Download PDF

Info

Publication number
CN105051891A
CN105051891A CN201480017220.3A CN201480017220A CN105051891A CN 105051891 A CN105051891 A CN 105051891A CN 201480017220 A CN201480017220 A CN 201480017220A CN 105051891 A CN105051891 A CN 105051891A
Authority
CN
China
Prior art keywords
conductive structure
substrate
thin space
semiconductor die
underfill
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201480017220.3A
Other languages
English (en)
Other versions
CN105051891B (zh
Inventor
杰斯皮德·S·甘德席
卢克·G·英格兰德
欧文·R·费伊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of CN105051891A publication Critical patent/CN105051891A/zh
Application granted granted Critical
Publication of CN105051891B publication Critical patent/CN105051891B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081Disposition
    • H01L2224/0812Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1182Applying permanent coating, e.g. in-situ coating
    • H01L2224/11822Applying permanent coating, e.g. in-situ coating by dipping, e.g. in a solder bath
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13023Disposition the whole bump connector protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13025Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout
    • H01L2224/1413Square or rectangular array
    • H01L2224/14131Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout
    • H01L2224/1413Square or rectangular array
    • H01L2224/14134Square or rectangular array covering only portions of the surface to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/165Material
    • H01L2224/16505Material outside the bonding interface, e.g. in the bulk of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171Disposition
    • H01L2224/1718Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/175Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29301Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29309Indium [In] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29301Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29311Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29301Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29316Lead [Pb] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29317Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29324Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29344Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29347Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29499Shape or distribution of the fillers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205Shape
    • H01L2224/32052Shape in top view
    • H01L2224/32054Shape in top view being rectangular or square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/3301Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/335Material
    • H01L2224/33505Layer connectors having different materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81011Chemical cleaning, e.g. etching, flux
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009Pre-treatment of the bump connector or the bonding area
    • H01L2224/81024Applying flux to the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81121Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/81122Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors by detecting inherent features of, or outside, the semiconductor or solid-state body
    • H01L2224/81125Bonding areas on the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901Pressing the bump connector against the bonding areas by means of another connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909Post-treatment of the bump connector or bonding area
    • H01L2224/81948Thermal treatments, e.g. annealing, controlled cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862Heat curing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83874Ultraviolet [UV] curing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544Design considerations for via connections, e.g. geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06582Housing for the assembly, e.g. chip scale package [CSP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06589Thermal management, e.g. cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894Materials of the insulating layers or coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811Extrinsic, i.e. with electrical conductive fillers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/146Mixed devices
    • H01L2924/1461MEMS
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/38Effects and problems related to the device integration
    • H01L2924/384Bump effects
    • H01L2924/3841Solder bridging

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)

Abstract

半导体装置及装置封装包含通过多个导电结构而电耦合到衬底的至少一个半导体裸片。所述至少一个半导体裸片可以是多个存储器裸片,且所述衬底可以是逻辑裸片。安置于所述至少一个半导体裸片与所述衬底之间的底部填充材料可包含导热材料。电绝缘材料安置于所述多个导电结构与所述底部填充材料之间。例如用于形成半导体装置封装的将半导体裸片附接到衬底的方法包含使用电绝缘材料来覆盖或涂布将所述半导体裸片电耦合到所述衬底的导电结构的至少外侧表面,及在所述半导体裸片与所述衬底之间安置导热材料。

Description

包含导电底部填充材料的半导体装置及封装以及相关方法
优先权主张
本申请案主张2013年3月27日申请的名称为“包含导电底部填充材料的半导体装置及封装以及相关方法(SEMICONDUCTORDEVICESANDPACKAGESINCLUDINGCONDUCTIVEUNDERFILLMATERIALANDRELATEDMETHODS)”的第13/851,788号美国专利申请案的权益。
技术领域
本发明的实施例涉及用于将半导体装置机械及电连接到衬底(例如使用导电底部填充材料来将具有细间距导电结构(例如焊球、金属支柱)的半导体装置连接到衬底或另一半导体装置)的封装技术。
背景技术
在电子工业中存在减小电子装置的组件的大小的趋势。这种大小上的减小可实现成本减小、效率提高及能量需求降低,以及其它益处。半导体装置封装(例如,存储器、处理器、发光二极管(LED)、微机电系统(MEMS)装置封装、其组合)已成为各种大小减小工作的对象。例如,减小由半导体装置封装覆盖的区域的一种方法包含将多个半导体设备彼此堆叠,且使用硅穿孔(TSV)来将多个半导体装置电耦合到下伏衬底。
一些常规半导体装置封装包含导电结构(例如,焊料凸块、铜柱),其将半导体装置彼此电耦合及/或电耦合到下伏衬底。底部填充材料安置于半导体装置之间的容积中,以将物理稳定性添加到封装且保护导电结构免于环境损害(例如,通过形成防潮层)。尽管可包含添加剂及填充材料以更改底部填充材料的机械、化学及/或热性质,但常规底部填充材料主要是电介质材料(例如,聚合物)。
半导体装置在操作期间产生非所要量的热量。例如,已知逻辑装置(例如,处理器)、动态随机存取存储器(DRAM)装置及互补金氧半导体(CMOS)装置会在操作期间产生显著热量。如果此类装置与其它半导体装置堆叠或由其覆盖,且被囊封、使用盖子来覆盖或两者(例如在包括多个半导体装置的半导体装置封装中),那么在半导体装置中的一或多者内,热量可滞留,且温度可上升到不可接受的水平。将热量从半导体装置封装中的半导体装置及衬底转移走可改善半导体装置的性能,且可减小对半导体装置造成热致损害的可能。
已知使用包含环氧成分及助焊剂成分的环氧助焊剂以在半导体装置的导电元件与衬底的接合垫之间的电连接的形成期间将氧化物从半导体装置的导电元件(例如,导电结构、焊球)移除。当在形成电连接时或之后,例如通过借助加热的蒸发而移除助焊剂成分。环氧助焊剂的环氧成分可同时或随后被固化,以形成可在结构上加固半导体装置与衬底的接合的固体环氧树脂。然而,环氧树脂的热阻相对较高(即,环氧树脂一般不是良好热导体),且热量可由热绝缘环氧树脂保留在封装的半导体装置中。此热量可损害半导体装置封装及/或减少半导体装置封装的性能。
已将填充剂添加到底部填充材料以增加通过底部填充材料的热传导。例如,已将陶瓷材料的颗粒用作填充剂以改善通过底部填充材料的热传递。然而,陶瓷填充剂(例如,氮化铝及氮化硼)难以以球形形式生产,且当以薄片形式被采用时,可造成难以实现均匀的、厚度可接受的接合线,且可在保护(例如,钝化)层上穿孔。导电颗粒(例如,金属颗粒)(其可展现比陶瓷颗粒或其它电绝缘颗粒更大的导热性)一般避免作为填充剂,或是以受限浓度使用,以抑制半导体装置封装的邻近导电结构之间的非所要电连通(例如,短路)。
附图说明
图1到7说明一种根据本发明的实施例的将半导体裸片附接到衬底以形成半导体装置封装的方法。
图1到3说明一种根据本发明的实施例的用于使用环氧助焊剂来涂布半导体裸片的细间距导电结构的工艺。
图4说明定位于衬底上方的半导体裸片,其中半导体裸片的经涂布的细间距导电结构与衬底的接合垫对准。
图5说明放置于衬底上的半导体裸片,其中经涂布的细间距导电结构定位于衬底的接合垫上方。
图6说明形成到衬底的导电特征的电连接的细间距导电结构。
图7说明包含安置于半导体裸片与衬底之间的容积中的底部填充材料的半导体装置封装的一部分。
图8是根据本发明的实施例的沿图7的线I-I取得的图7的半导体装置封装的部分的横截面俯视图。
图9是根据本发明的另一实施例的类似于图8的半导体装置封装的一部分的横截面俯视图。
图10是根据本发明的实施例的半导体装置封装的横截面侧视图。
具体实施方式
如文中所使用,参考给定参数的术语“实质上”表示且在所属领域的一般技术人员将了解的程度上涵盖满足了给定参数、性质或条件,同时有较小程度的偏差(例如在可接受制造公差内)。经由实例且无限制,“实质上”满足的参数可为至少约90%满足、至少约95%满足或甚至至少约99%满足。
如文中所使用,任何关系术语(例如“第一”、“第二”、“在上方”、“在上”、“顶部”、“底部”、“垂直”、“横向”等等)是为了清晰及方便理解本发明及附图而使用,且除了上下文另外清晰指示之处之外,不表示或取决于任何特定偏好、定向或顺序。
以下描述提供特定细节,例如材料类型及处理条件,以便提供对本发明的实施例的透彻描述。然而,所属领域的一般技术人员将了解,本发明的实施例可在不采用这些特性细节的情况下实施。当然,本发明的实施例可结合行业中所采用的常规半导体制造技术而实施。另外,下文所提供的描述可能未形成用于制造半导体装置及封装的完整工艺流程。下文所描述的结构无需形成完整半导体装置或封装。在下文仅详细描述理解本发明的实施例所需的工艺动作及结构。形成完整半导体装置、封装及系统的额外动作可通过常规制造技术执行。因此,在文中仅描述理解本发明的实施例所需的方法及半导体装置结构。
在以下详细描述中,对附图进行参考,所述附图形成本发明的一部分,且其中经由说明来展示其中可实施本发明的特定实施例。足够详细地描述这些实施例,以使得所属领域的一般技术人员能够实施本发明。然而,可利用其它实施例,且可在不背离本发明的范围的情况下做出结构、逻辑、方法及组成上的改变。文中所呈现的说明不希望是任何特定系统、装置、结构或封装的真实视图,而仅为经采用以描述本发明的实施例的理想化的表示。文中所呈现的图式无需按照比例绘制。另外,图式之间的共用元件可保留相同数字名称。然而,编号中的任何相似性不表示结构或组件需要在大小、组成、配置或其它性质上相同。
本发明的实施例包含(例如)将半导体裸片电及机械连接到衬底(例如,另一半导体裸片(例如,存储器裸片、逻辑裸片)、印刷电路板、插入器等等)以形成半导体装置封装的方法。所述方法包含使用底部填充材料,其可包含导热及导电填充材料以促进通过底部填充材料的热量转移。使用此底部填充材料可在半导体裸片及衬底中的至少一者中维持足够低的温度,以改善或维持其性能及可靠性。另外,本发明的实施例包含使用此类底部填充材料来形成半导体装置封装的方法。为避免或减少用于将半导体裸片连接到衬底的导电结构(例如,焊料凸块、导电支柱、金属支柱、铜柱)之间的电短路,在将底部填充材料引入半导体裸片与衬底之间的容积中之前,导电结构可至少部分涂布有环氧助焊剂。环氧助焊剂的环氧成分可在导电结构与任何邻近导电底部填充材料之间形成电绝缘屏障。本发明的方法可尤其对将半导体裸片附接到衬底(其中多个细间距导电结构用于形成半导体裸片与衬底之间的电连接)有用。因此,本发明的实施例可实现使用底部填充材料中的导电填充材料(例如,金属填充材料)来实质上增强导热性。
图1到7说明一种将半导体裸片100附接到衬底的方法。参考图1,半导体裸片100可以是常规半导体裸片,其包含(例如)动态随机存取存储器(DRAM)裸片、快闪裸片、逻辑裸片(例如,处理器裸片)、互补金氧半导体(CMOS)裸片等等。因此,本发明的方法不限于任何特定类型的半导体裸片100。半导体裸片100可包含从主要表面突出以用于将半导体裸片100附接及电耦合到衬底的多个导电结构102。经由实例且无限制,导电结构102中的每一者可以是形成于半导体裸片100的对应导电垫104上的导电凸块或支柱,例如焊料凸块(例如,包含银锡合金的凸块)、金属支柱、铜柱、尖端有焊料的金属支柱等等。导电结构102可(例如)跨半导体裸片100的主要表面而布置于所谓的“球栅阵列”(BGA)中。
在一些实施例中,多个导电结构102可以细间距形成。间距是用于描述邻近(例如,重复)特征的大小的概念,且一般被定义为一个特征的宽度加上所述特征与紧邻特征之间的距离。如文中所使用,词组“细间距”是指特征具有相对较小的间距。因此,以细间距形成的导电结构102可以是相对较小导电结构102,且/或彼此相对接近而定位。经由实例且无限制,本发明的导电结构102可具有约1000微米或更小的间距,例如在约40微米与约500微米之间。在一些实施例中,导电结构102可具有在约40微米与约100微米之间的间距。在其它实施例中,可以增大的间距(即,并非细间距)形成多个导电结构102。当然,所列出的间距值仅作为实例而提供,且本发明的实施例可包含高于或低于所列出的值的间距。
如图1中所示,半导体裸片100可由所谓的“拾取及放置”装置的拾取头106(例如)通过真空力固持于半导体裸片100的与导电结构102相对的一侧上。拾取头106可用于将半导体裸片100定位于包含液体环氧助焊剂110的贮槽的液体容器108(例如,所谓的“助焊剂托盘”)上方。液体环氧助焊剂110可包含环氧成分及助焊剂成分。环氧成分可包含(例如)环氧树脂及环氧固化剂。环氧树脂可以是电绝缘材料。助焊剂成分可以是用于在接合工艺期间移除或抑制在导电结构102的表面上形成金属氧化物的化学成分,如所属领域的一般技术人员所知。例如,助焊剂成分可包含羧酸。其它常规成分可包含于液体环氧材料110中,例如胶粘剂成分、增稠剂、催化剂材料、助流剂、助粘剂、染料等等。
环氧助焊剂110可购得或可针对特定应用而被特别配制。在一些实施例中,可作为环氧助焊剂110使用的可购得的材料的实例包含以下:可从德国杜塞尔多夫的汉高公司(HenkelCorporation)购得的部件号FF6000;可从乔治亚州萨沃尼的阿尔法先进材料公司(AlphaAdvancedMaterials)购得的商标名为STAYCHIPTMPRL50-5D的材料;可从日本东京的千住金属工业有限公司(SenjuMetalIndustryCo.,Ltd.)购得的商标名为JPK8的材料;可从北卡罗莱纳州喀里的洛德公司(LORDCorporation)购得的商标名为EXP10067的材料;及都可从伊利诺斯州伊塔斯加的凯斯特公司(Kester,Inc.)购得的商标名为JL-8-22-4及JL8-106-1的材料。
参考图2,拾取头106可经降低以定位导电结构102使其至少部分与液体容器108中的液体环氧助焊剂110接触。液体容器108的深度D(图1)可与导电结构102从半导体裸片100的主要表面延伸的距离L(图1)相关,且与将要涂布导电结构102的液体环氧助焊剂110的所要容积相关。可基于在半导体裸片100与衬底(半导体裸片100将被接合到其)之间的所要接合线厚度而选择导电结构102从半导体裸片100的主要表面延伸的长度L,如下文更详细讨论。在一些实施例中,深度D可小于长度L,以使得半导体裸片100能够被降低(或升高液体容器108),直到导电结构102接触液体容器108的底部。在其它实施例中,深度D可大于长度L,且半导体裸片100可被降低(或可升高液体容器108),直到所要量的导电结构102及/或半导体裸片100的主要表面由液体环氧助焊剂110接触。如果深度D大于长度L,那么半导体裸片100可被降低(或可升高液体容器108),直到在导电结构102的横向外部的半导体裸片100的主要表面接触液体容器108的顶面。
液体容器108中的液体环氧助焊剂110的粘度及粘性可经调整,以使得所要量的液体环氧助焊剂110能够形成于导电结构102且使得导电结构102能够浸渍于液体环氧助焊剂110中,且能够在不陷入液体环氧助焊剂110中的情况下被移除。例如,液体环氧助焊剂110可经加热以减小其粘度或经冷却以增大其粘度。替代地或另外,液体环氧助焊剂110的化学成分可经选择,使得液体环氧助焊剂110展现所要粘度及粘性。另外,可更改导电结构102定位于液体容器108中的时间量,以更改形成于导电结构102上的液体环氧助焊剂110的量。
参考图3,拾取头106可被抬起以从液体容器108移除导电结构102。导电结构102的外表面的至少一部分可由某量的液体环氧助焊剂110覆盖。如图3中所示,每一导电结构102可至少部分由单独量的液体环氧助焊剂110覆盖。在其它实施例中,液体环氧助焊剂110也可在导电结构102之间(例如在导电结构102之间的半导体裸片100的主要表面上)形成,使得单一连续量的液体环氧助焊剂110可覆盖导电结构102中的一者以上或甚至全部。
尽管已参考通过将导电结构102浸入液体容器108中的液体环氧助焊剂110中而使用液体环氧助焊剂110来覆盖导电结构102而描述图1到3,但本发明并非如此受限。例如,在其它实施例中,液体环氧助焊剂110可(例如)通过将液体环氧助焊剂110喷射于导电结构102上方、将液体环氧助焊剂110印刷于导电结构上方或在导电结构102上形成液体环氧材料的任何其它方法而形成于导电结构102上方。
参考图4,在某量的液体环氧助焊剂110形成于导电结构102的至少一部分上之后,半导体裸片100可被定位于衬底112上方,且导电结构102可与衬底112的相应接合垫114对准。衬底112可以是与半导体裸片100物理及电耦合的任何衬底。经由实例且无限制,衬底112可以是印刷电路板(PCB)、插入器、逻辑裸片、处理器裸片、引线框或实质上类似于半导体裸片100的另一半导体裸片。衬底112可包含接合垫114,其在衬底是PCB或任何插入器的情况下可替代地被表征化为端子垫114,被布置于对应于多个导电结构102的图案的图案中。另外,衬底可包含阻焊剂116(例如经配置以抑制焊接材料围绕接合垫114横向流动的电介质材料)。衬底112还可包含其它组件、结构及材料,例如(取决于衬底112的结构及功能且无限制)晶体管、电容器、电介质材料、导电迹线、导电通孔、重分配层、累积层、钝化层等等,如技术领域中已知。
参考图5,半导体裸片100可被放置于衬底112上。导电结构102可被放置于接合垫114上,且通过液体环氧助焊剂110接触接合垫114。如果液体环氧助焊剂110可充分流动,那么半导体裸片100的重量、拾取头106的力或其组合可致使液体环氧助焊剂110流动,且导电结构102中的一或多者可直接接触相应一或多个接合垫114。如图5中所示,在将半导体裸片100放置于衬底112上之后,拾取头106可释放半导体裸片100且被收回。
参考图6,半导体裸片100可通过多个导电结构102电耦合到衬底112,导电结构112可经定位于半导体裸片100与衬底112之间的容积中。经由非限制实例,半导体裸片100可被压向衬底112(如使用表示施力的箭头120所示),以使得导电结构102物理及电接触接合垫114。在一些实施例中,热量还可被施加到结构以至少部分软化或熔化导电结构102或其部分,从而在导电结构102与接合垫114之间形成接合。当导电结构102被压抵着接合垫114及/或被熔化时,液体环氧助焊剂110可从接合界面流走,且流向导电结构102的外侧表面。因此,导电结构102与接合垫114之间的接合界面可实质上无环氧助焊剂110,使得可在导电结构102与相应接合垫114之间形成直接物理及电接合。另外,液体环氧助焊剂110可沿导电结构102的外侧表面,从焊接掩模116实质上连续延伸到面向容积的半导体裸片100的主要表面,以围绕导电结构102中的每一者形成屏障。
导电结构102与接合垫114之间的物理接合的形成可形成多个机械及电连接,所述连接通过导电结构102从导电垫104延伸且到接合垫114。因此,可通过导电结构102在半导体裸片100与衬底112之间建立还提供机械附接点的电连通路径。
热量可被施加到图6中所说明的结构以至少部分固化液体环氧助焊剂110。热量可诱发化学反应以使环氧树脂成分交联。此交联可硬化及机械强化环氧助焊剂110的环氧成分。另外,环氧助焊剂110的任何挥发性成分(例如助焊剂成分)可在暴露于固化工艺的热量中时至少部分蒸发。归因于助焊剂成分及(可能)其它成分的损耗,环氧助焊剂110可在体积、厚度及质量上缩小。例如,在施加热量及固化环氧助焊剂110之后剩余的环氧助焊剂110的环氧成分可为最初应用于导电结构102时的环氧助焊剂110的约10重量%与约25重量%之间。因此,环氧助焊剂110可通过施加热量而从液体环氧助焊剂110转换成经硬化环氧树脂110A(见图7到9)。
在一些实施例中,例如在所谓的“热压”工艺中,可将热量的至少一部分施加到结构,同时将半导体裸片100压向衬底112。在其它实施例中,可将足够热量施加到结构以在所谓的“回焊”工艺中熔化或软化导电结构102或其部分,所述工艺可涉及在比热压工艺更长的时间量内施加热量。回焊工艺可结合或不结合朝向衬底112对半导体裸片100施力(由箭头120指示)而执行。在一些实施例中,可在半导体裸片100被压向衬底112之后施加额外热量(热压工艺及/或回焊工艺),以更完全固化环氧助焊剂110且以蒸发其助焊剂成分的至少一部分。取决于(例如)所选环氧助焊剂110的特定化学成分,所属领域的一般技术人员将能够选择足以固化环氧助焊剂110的特定温度及时间量。
参考图7,在导电结构102接合到接合垫114且环氧助焊剂110经固化变为环氧树脂110A之后,可将底部填充材料130安置于半导体裸片100与衬底112之间的容积中且邻近导电结构102。可使用常规技术(例如)通过接近半导体裸片100的一或多个边缘分配液体底部填充材料130且允许毛细力将底部填充材料130吸入容积中来将底部填充材料130引入容积中。在一些实施例中,可通过施加大于大气压力的压力以迫使底部填充材料130进入容积中或通过施加经减小的压力(例如真空)以吸取容积外的任何气体(例如空气)及吸取底部填充材料130进入容积中而辅助此毛细管作用及减少孔隙的形成。底部填充材料130可至少实质上填充半导体裸片100与衬底112之间的容积,且邻近且横向围绕导电结构102。沿导电结构102的外侧表面的环氧树脂110A可在导电结构102与底部填充材料130之间形成物理及绝缘(例如,电介质)屏障。环氧树脂110A可横向囊封导电结构102,通过介入底部填充材料130而实质上减少或甚至防止导电结构102之间的短路的可能。环氧树脂110A还可将机械支撑提供到导电结构102,且将机械强度提供给半导体裸片100与衬底112之间的连接。
底部填充材料130可包含聚合物基质及导热材料(即,填充材料),其可呈颗粒的形式。如文中所使用,术语“导热材料”表示且涵盖展现至少比基质材料(导热材料在其中分散)的导热性更大的导热性的材料。与不具有此导热材料的底部填充材料比较,导热材料可用于改善通过底部填充材料130的热传递。展现相对较高导热性的许多材料(例如,金属)也是导电的。因此,在一些实施例中,底部填充材料130的导热材料可以是或包含金属或另一材料的导电颗粒。
底部填充材料130的聚合物基质可以是或包含(例如)环氧材料、硅酮材料、改质硅酮材料或丙烯酸脂材料。经由实例且无限制,导热材料可以是金属或金属合金材料。经由另一实例,导热材料可包含银、金、铜、锡、铟、铅、铝、其合金、焊接合金及其组合中的至少一者。底部填充材料130的导热材料可呈任何形状的颗粒的形式。例如,导热材料的颗粒可呈球体、薄片、纤维或不规则形状的形式。颗粒中的每一者的表面可以是平滑或粗糙的。导热材料的量在固化之前可至少为底部填充材料130的约50重量%。在一些实施例中,导热材料的量可在底部填充材料130的约60重量%与约95重量%之间。在一些实施例中,导热材料的量可在底部填充材料130的约75重量%与约90重量%之间。在特定实施例中,导热材料的量可以是底部填充材料130的约86重量%。此高负载量的导热材料可大体上致使底部填充材料130(整体上)是导电以及导热的。然而,导电结构102与底部填充材料130之间的由环氧树脂110A形成的电绝缘屏障可允许将此导电底部填充材料130用于包含细间距导电结构102的半导体装置封装。因此,环氧树脂110A可允许实现使用十分导热的底部填充材料130,而没有针对其导电性的限制。
为促进底部填充材料130(包含导热材料)流入半导体裸片100与衬底112之间的容积中,导热材料的颗粒的平均直径可约为接合线厚度的三分之一或更少。接合线厚度可由跨半导体裸片100与衬底(不包含导电结构102)之间的体积的最短垂直距离界定。换句话说,接合线厚度等于半导体裸片100与衬底112之间的底部填充材料130的薄膜厚度。经由实例且无限制,半导体裸片100与衬底之间的接合线厚度可在约10微米与约100微米之间,例如在约20微米与约30微米之间。导热材料的颗粒的大小可实质上小于接合线厚度,以防止桥接及损坏接合线并且防止横向囊封导电结构102的环氧树脂110A的机械应力诱发穿孔。因此,在一些实施例中,导热材料的最大粒度(例如直径)可约为30微米或更小,例如小于约20微米、小于约3微米或甚至小于约1微米。其中接合线的深度为约20微米与约30微米之间,最大粒度可小于约3微米。在一些实施例中,导热材料的最大粒度可在约500纳米与约25微米之间。
包含导热材料的底部填充材料130可在市场上采购或可针对特定应用而特别配制。在一些实施例中,可用作底部填充材料130的可购得的材料的实例包含以下:商标名为EN-4920T_U-5677-011(具有丙烯酸脂基质及银粉填充剂,银粉填充剂构成材料的约86重量%)及EN-4620K(具有环氧基质及银粉填充剂,银粉填充剂构成材料的约75重量%与约95重量%之间)的材料,两者都可从日本东京的日立化学有限公司(HitachiChemicalCo.,Ltd.)购得;商标名为MT-315及MT-141(各自具有环氧基质及银填充剂,银填充剂构成材料的约75重量%与约80重量%之间)的材料,两者都可从北卡罗莱纳州喀里的洛德公司(LORDCorporation)购得;商标名为H20S(具有环氧基质及银片填充剂)及H20S-D(具有环氧基质及银片填充剂,银片填充剂构成材料的约60重量%与约75重量%之间)的材料,两者都可从马萨诸塞州比勒利卡的环氧树脂技术公司(EpoxyTechnology,Inc.)购得;商标名为84-1LMISR4(具有环氧基质及银填充剂)的材料,其可通过德国杜塞尔多夫的汉高公司(HenkelCorporation)的品牌购得;商标名为260C(具有环氧基质及铜及锡合金填充剂,铜及锡合金填充剂构成材料的约86重量%)的材料,其可从加州圣地亚哥的奥美特电路公司(OrmetCircuits,Inc.)购得;商标名为DA-6534(具有改质硅酮基质及银片填充剂,银片填充剂构成材料的约60重量%)的材料,其可从密歇根州米德兰的道康宁公司(DowCorningCorporation)购得;商标名为X-23-7835-5(具有硅酮基质及铟填充剂)的材料,其可从日本东京的信越化学有限公司(Shin-EtsuChemicalCo.,Ltd).购得;及商标名为APS1E(具有环氧基质及铜及焊接填充剂,铜及焊接填充剂构成材料的约80重量%与约90重量%之间)的材料,其可从新泽西州莫里斯镇的霍尼韦尔国际公司(HoneywellInternationalInc.)购得。
经由实例且无限制,尽管底部填充材料的聚合物基质可展现相对较低导热性(例如约1.3W/mK),但所选底部填充材料130(整体上)可展现高达(例如)约300.0W/mK的导热性。在一些实施例中,底部填充材料130可展现至少约1.0W/mK的导热性,例如在约10.0W/mK与约30.0W/mK之间。在一些实施例中,底部填充材料130可展现在约10W/mK与约200.0W/mK之间的导热性。在一些实施例中,底部填充材料130可以是常规地用于填充组件(例如半导体装置)与散热器之间的界面中的间隙的热界面材料(“TIM”)。
导电材料(例如TIM)并未常规地用作底部填充材料,特别是在具有如文中所描述的所述结构的细间距导电结构102的半导体装置封装中,这是因为其导电性将具有致使导电结构102通过底部填充材料而非所要地彼此电连通(即,形成电连接)的较高可能性,如上文所描述。然而,如上文所提及,沿本发明的导电结构102的外侧表面由环氧树脂110A形成的电绝缘屏障允许实现使用与非导电及/或不包含导电填充材料的底部填充材料相比的也高度导热的导电底部填充材料130。
在底部填充材料130安置于半导体裸片100与衬底112之间的容积中之后,底部填充材料130可被固化(例如凝固)。取决于所使用的底部填充材料130的类型,底部填充材料130可通过(例如)施加热量或暴露于辐射(例如紫外线辐射)中而固化。在一些实施例中,底部填充材料130的固化可使得底部填充材料130的聚合物基质化学键接到环氧树脂110A。如果存在,那么此类化学键接可抑制底部填充材料130与环氧树脂110A之间的界面处的孔隙及/或应力集中点的形成。
因此,本发明包含将半导体裸片附接到衬底的方法。根据此类方法,半导体裸片可使用多个细间距导电结构来电耦合到衬底。多个细间距导电结构中的每一细间距导电结构的至少外侧表面可由电绝缘材料覆盖。导热材料可安置于半导体裸片与衬底之间。导热材料可包含多个导热颗粒及聚合物基质。
另外,本发明包含形成半导体装置封装的方法。根据此类方法,半导体装置的多个细间距导电结构可至少部分涂布有电绝缘材料。多个细间距导电结构可电耦合到衬底的对应多个接合垫。底部填充材料可安置于半导体装置与衬底之间的容积中。底部填充材料可具有分散于其中的多个导热颗粒。
参考图8,展示沿图7的线I-I穿过半导体裸片100与衬底112之间的容积取得的图7的结构的横截面俯视图。如图8中所示,在一些实施例中,多个导电结构102中的每一导电结构102可具有沿其外侧表面的相异量的环氧树脂110A。底部填充材料130可安置于衬底112上方(包含在多个导电结构102的紧邻导电结构102之间)。
参考图9,展示类似于图8的视图的横截面俯视图,不过多个导电结构102中的一个以上导电结构102可具有围绕其外侧表面的共同量的环氧树脂110A。因此,底部填充材料130可能不安置于多个导电结构102中的至少一些紧邻导电结构102之间。
在额外实施例中,单一连续量的环氧树脂110A可覆盖导电结构102中的一者以上,但可能不完全填充半导体裸片100(图7)与衬底112之间及紧邻导电结构102之间的容积。在此情况下,导电结构102中的一者以上可由单一连续量的环氧树脂110A覆盖,但一些底部填充材料130仍可安置于紧邻导电结构102之间的未填充容积中。
参考图10,说明半导体装置封装200,其包含被堆叠且通过第一多个导电结构202(其可具有细间距)电耦合的多个半导体存储器(例如DRAM)裸片201A到201H。多个半导体存储器裸片201A到201H可堆叠于半导体逻辑裸片212上方。半导体逻辑裸片212可以是处理器,例如专用集成电路(ASIC)处理器或中央处理单元(CPU)处理器。半导体存储器裸片201A到201H可通过第二多个导电结构202(其可具有细间距)而电耦合到半导体逻辑裸片212。半导体逻辑裸片212可通过(例如)第三多个导电结构224(其可具有细间距,尽管第三多个导电结构224的间距可大于第一多个导电结构202及第二多个导电结构202的间距)而电耦合到印刷电路板(PCB)222。PCB222可包含第四多个导电结构226以将PCB222电耦合到更高层级衬底,例如母板。第四多个导电结构226也可具有细间距,尽管第四多个导电结构226的间距可大于第一多个导电结构202及第二多个导电结构202及/或第三多个导电结构224的相应间距。在一些实施例中,第四多个导电结构226可能不具有细间距。
散热器228(例如铜板)可定位于半导体存储器裸片201A到201H的堆叠上方以从半导体存储器裸片201A到201H及半导体逻辑裸片212抽走热量。热界面材料(TIM)232可安置于顶部半导体存储器裸片201H与散热器228之间以改善其间的热传递。
经配制为上文所描述或其它导电配方的底部填充材料130中的一者以提供所要导热性的底部填充材料230可安置于半导体裸片之间(例如在半导体存储器裸片201A到201H中的任何者与半导体逻辑裸片212之间)、半导体裸片与衬底之间(例如在半导体逻辑裸片212与PCB222之间)及在衬底与更高层级衬底之间(例如在PCB222与母板之间)的容积中的任何者或全部中。如上文所解释,底部填充材料230可包含也可以是导电材料的导热材料,使得底部填充材料230整体上可以是导电的。在底部填充材料230安置于其中的任何容积中,对应导电结构202、224及/或226的至少外侧表面可由电绝缘材料210(例如,环氧树脂)覆盖,如上文参考环氧助焊剂110及环氧树脂110A所描述。尽管第二多个导电结构202、第三多个导电结构224及/或第四多个导电结构226的外侧表面可替代地或额外由电绝缘材料210覆盖,但为简单起见,电绝缘材料210在图10中被展示为仅覆盖第一多个导电结构202。
在一些实施例中,半导体存储器裸片201A到201H中的每一者之间的容积可填充有底部填充材料230(包含导电及导热材料)。另外,更低半导体存储器裸片201A与半导体逻辑裸片212之间的容积可填充有底部填充材料230。将半导体存储器裸片201A到201H彼此电耦合且电耦合到半导体逻辑裸片212的导电结构202中的每一者的外侧表面可由电绝缘材料210覆盖。因此,可减小半导体裸片(包含半导体逻辑裸片212及半导体存储器裸片201A到201H)的堆叠的整体热阻,且半导体装置封装200的组件(例如半导体存储器裸片201A到201H及半导体逻辑裸片212)的操作温度可比不包含底部填充材料230(其包含导电及导热材料)的半导体装置封装更低。因此,与常规半导体装置封装相比,底部填充材料230可通过使得半导体装置封装200能够在更低裸片温度中操作而改善半导体装置封装200的性能、刷新率及可靠性。
因此,本发明包含半导体装置,所述装置包含衬底及通过多个细间距导电结构而电耦合到衬底的至少一个半导体裸片。底部填充材料可安置于衬底与至少一个半导体裸片之间的容积中且邻近多个细间距导电结构。底部填充材料可包括导热材料。半导体装置还可包含安置于多个细间距导电结构与底部填充材料之间的电绝缘材料。
另外,本发明包含半导体装置封装,所述装置封装包含半导体逻辑裸片及堆叠于半导体逻辑裸片上方的多个半导体存储器裸片。多个导电结构可将多个半导体存储器裸片及半导体逻辑裸片中的邻近裸片彼此电耦合。电绝缘材料可覆盖多个导电结构中的每一导电结构的外侧表面。导热及导电材料可安置于半导体逻辑裸片及多个半导体存储器裸片中的邻近裸片之间的聚合物基质中。
上文所描述及附图中所说明的本发明的实施例不限制本发明的范围,这是由于这些实施例仅为本发明的实施例的实例。本发明由所附权利要求书及其合法等效物定义。任何等效实施例处在本发明的范围内。当然,除了文中所示及所描述的所述修改之外,所属领域的一般技术人员将从描述明白本发明的多种修改,例如所描述的元件的替代性的有用组合。此类修改及实施例也处在所附权利要求书及其合法等效物的范围内。

Claims (20)

1.一种半导体装置,所述装置包括:
衬底;
至少一个半导体裸片,其通过多个细间距导电结构而电耦合到所述衬底;
底部填充材料,其经安置于所述衬底与所述至少一个半导体裸片之间的容积中且邻近所述多个细间距导电结构,所述底部填充材料包括导热材料;以及
电绝缘材料,其安置于所述多个细间距导电结构与所述底部填充材料之间。
2.根据权利要求1所述的半导体装置,其中所述衬底包括逻辑裸片及实质上类似于所述至少一个半导体裸片的另一半导体裸片中的一者。
3.根据权利要求1所述的半导体装置,其中所述电绝缘材料包括环氧材料。
4.根据权利要求1所述的半导体装置,其中所述底部填充材料展现在约1.0W/mK与约300.0W/mK之间的导热性。
5.根据权利要求1所述的半导体装置,其中所述电绝缘材料经化学键接到所述底部填充材料。
6.根据权利要求1所述的半导体装置,其中所述底部填充材料进一步安置于所述多个细间距导电结构中的紧邻细间距导电结构之间的容积中。
7.根据权利要求1所述的半导体装置,其中所述导热材料包括小于所述半导体裸片与所述衬底之间的所述容积的厚度的约三分之一的颗粒。
8.根据权利要求1所述的半导体装置,其中所述多个细间距导电结构以约1000微米或更小的间距定位。
9.根据权利要求1所述的半导体装置,其中所述电绝缘材料横向囊封所述多个细间距导电结构中的每一细间距导电结构。
10.根据权利要求1所述的半导体装置,其中所述至少一个半导体裸片包括堆叠于所述衬底上方的多个半导体裸片。
11.根据权利要求1到10中任一权利要求所述的半导体装置,其中所述底部填充材料的所述导热材料包括导电材料。
12.根据权利要求11所述的半导体装置封装,其中所述导电材料包括多个导电颗粒。
13.一种将半导体裸片附接到衬底的方法,所述方法包括:
使用多个细间距导电结构来将半导体裸片电耦合到衬底;
使用电绝缘材料来覆盖所述多个细间距导电结构中的每一细间距导电结构的至少外侧表面;以及
将包含多个导热颗粒及聚合物基质材料的导热材料安置于所述半导体裸片与所述衬底之间。
14.根据权利要求13所述的方法,其中使用电绝缘材料来覆盖所述多个细间距导电结构中的每一细间距导电结构的至少外侧表面包括:
使用环氧助焊剂来覆盖每一细间距导电结构的至少所述外侧表面;以及
固化所述环氧助焊剂。
15.根据权利要求14所述的方法,其中固化所述环氧助焊剂包括将热量施加到所述环氧助焊剂,以固化其环氧成分及蒸发其助焊剂成分的至少一部分。
16.根据权利要求13所述的方法,其中使用多个细间距导电结构来将半导体裸片电耦合到衬底包括将所述多个细间距导电结构电耦合到所述衬底的对应多个接合垫。
17.根据权利要求16所述的方法,其中将所述多个细间距导电结构电耦合到所述衬底的对应多个接合垫包括将所述半导体裸片热压接合到所述衬底和使所述多个细间距导电结构在一段时间内经受温度以至少部分熔化及回焊所述细间距导电结构的材料中的至少一者。
18.根据权利要求13所述的方法,进一步包括选择所述导电材料以包含所述多个导热颗粒的至少约50重量%。
19.根据权利要求13到18中任一权利要求所述的方法,进一步包括选择所述导热材料以包含多个导热及导电颗粒。
20.根据权利要求19所述的方法,进一步包括选择所述导电材料以包括具有约30微米或更小的最大粒度的所述多个导热及导电颗粒。
CN201480017220.3A 2013-03-27 2014-03-25 包含导电底部填充材料的半导体装置及封装以及相关方法 Active CN105051891B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/851,788 US20140291834A1 (en) 2013-03-27 2013-03-27 Semiconductor devices and packages including conductive underfill material and related methods
US13/851,788 2013-03-27
PCT/US2014/031668 WO2014160675A1 (en) 2013-03-27 2014-03-25 Semiconductor devices and packages including conductive underfill material and related methods

Publications (2)

Publication Number Publication Date
CN105051891A true CN105051891A (zh) 2015-11-11
CN105051891B CN105051891B (zh) 2019-07-05

Family

ID=51620003

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480017220.3A Active CN105051891B (zh) 2013-03-27 2014-03-25 包含导电底部填充材料的半导体装置及封装以及相关方法

Country Status (5)

Country Link
US (2) US20140291834A1 (zh)
KR (1) KR101825278B1 (zh)
CN (1) CN105051891B (zh)
TW (1) TWI538120B (zh)
WO (1) WO2014160675A1 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108633181A (zh) * 2017-03-23 2018-10-09 德尔福技术有限公司 电气设备粘合剂屏障
CN110557937A (zh) * 2018-05-31 2019-12-10 铟泰公司 有效抑制在bga组合件的不润湿开口的助焊剂
CN112185911A (zh) * 2019-07-03 2021-01-05 美光科技公司 包含垂直集成电路的半导体组合件及其制造方法
CN112838079A (zh) * 2020-12-31 2021-05-25 湖北长江新型显示产业创新中心有限公司 显示模组及其制作方法

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110309481A1 (en) * 2010-06-18 2011-12-22 Rui Huang Integrated circuit packaging system with flip chip mounting and method of manufacture thereof
US9209149B2 (en) 2013-11-14 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace structures with high assembly yield
US9870843B2 (en) * 2014-03-11 2018-01-16 The Hong Kong University Of Science And Technology Electrical and thermal conductive paste composition and method of reducing percolation threshold and enhancing percolating conductivity using the same
US9691746B2 (en) 2014-07-14 2017-06-27 Micron Technology, Inc. Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths
US9548289B2 (en) * 2014-09-15 2017-01-17 Mediatek Inc. Semiconductor package assemblies with system-on-chip (SOC) packages
US20160079205A1 (en) * 2014-09-15 2016-03-17 Mediatek Inc. Semiconductor package assembly
US9397078B1 (en) * 2015-03-02 2016-07-19 Micron Technology, Inc. Semiconductor device assembly with underfill containment cavity
US9601374B2 (en) 2015-03-26 2017-03-21 Micron Technology, Inc. Semiconductor die assembly
CN113257766A (zh) * 2015-08-21 2021-08-13 意法半导体有限公司 半导体装置及其制造方法
DE112015006855T5 (de) * 2015-08-28 2018-08-16 Intel IP Corporation Mikroelektronik-Packages mit hochintegriertem Mikroelektronik-Dice-Stapel
KR101787832B1 (ko) * 2015-10-22 2017-10-19 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지
WO2018063415A1 (en) * 2016-10-01 2018-04-05 Intel Corporation Indium solder metallurgy to control electro-migration
US10424559B2 (en) * 2016-12-22 2019-09-24 Intel Corporation Thermal management of molded packages
US11201066B2 (en) * 2017-01-31 2021-12-14 Skyworks Solutions, Inc. Control of under-fill using a dam on a packaging substrate for a dual-sided ball grid array package
US20180286704A1 (en) * 2017-04-01 2018-10-04 Intel Corporation Processes and methods for applying underfill to singulated die
CN110660809B (zh) * 2018-06-28 2023-06-16 西部数据技术公司 包含分支存储器裸芯模块的垂直互连的半导体装置
US10861714B2 (en) * 2019-01-15 2020-12-08 Asm Technology Singapore Pte Ltd Heating of a substrate for epoxy deposition
US10764989B1 (en) * 2019-03-25 2020-09-01 Dialog Semiconductor (Uk) Limited Thermal enhancement of exposed die-down package
US11404390B2 (en) * 2020-06-30 2022-08-02 Micron Technology, Inc. Semiconductor device assembly with sacrificial pillars and methods of manufacturing sacrificial pillars
US11862591B2 (en) * 2021-08-25 2024-01-02 Micron Technology, Inc. Conductive buffer layers for semiconductor die assemblies and associated systems and methods

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5956605A (en) * 1996-09-20 1999-09-21 Micron Technology, Inc. Use of nitrides for flip-chip encapsulation
US6232563B1 (en) * 1995-11-25 2001-05-15 Lg Electronics Inc. Bump electrode and method for fabricating the same
CN1738042A (zh) * 2004-08-20 2006-02-22 国际商业机器公司 集成电路结构及其形成方法
CN101176200A (zh) * 2005-05-17 2008-05-07 松下电器产业株式会社 倒装片安装方法、倒装片安装装置及倒装片安装体
US20100065790A1 (en) * 2006-05-08 2010-03-18 Diemat Conductive Composition
US20110180920A1 (en) * 2010-01-28 2011-07-28 International Business Machines Corporation Co-axial restraint for connectors within flip-chip packages

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100309957B1 (ko) * 1997-09-08 2002-08-21 신꼬오덴기 고교 가부시키가이샤 반도체장치
US6002168A (en) * 1997-11-25 1999-12-14 Tessera, Inc. Microelectronic component with rigid interposer
US20070241303A1 (en) * 1999-08-31 2007-10-18 General Electric Company Thermally conductive composition and method for preparing the same
JP2001093938A (ja) * 1999-09-20 2001-04-06 Nec Kansai Ltd 半導体装置及びその製造方法
JP3813797B2 (ja) * 2000-07-07 2006-08-23 株式会社ルネサステクノロジ 半導体装置の製造方法
TW498506B (en) * 2001-04-20 2002-08-11 Advanced Semiconductor Eng Flip-chip joint structure and the processing thereof
US6686664B2 (en) * 2001-04-30 2004-02-03 International Business Machines Corporation Structure to accommodate increase in volume expansion during solder reflow
US6677179B2 (en) * 2001-11-16 2004-01-13 Indium Corporation Of America Method of applying no-flow underfill
US6610559B2 (en) * 2001-11-16 2003-08-26 Indium Corporation Of America Integrated void-free process for assembling a solder bumped chip
TW571375B (en) * 2002-11-13 2004-01-11 Advanced Semiconductor Eng Semiconductor package structure with ground and method for manufacturing thereof
US7252514B2 (en) * 2004-09-02 2007-08-07 International Business Machines Corporation High density space transformer and method of fabricating same
US20090108472A1 (en) * 2007-10-29 2009-04-30 International Business Machines Corporation Wafer-level underfill process using over-bump-applied resin
US8390117B2 (en) * 2007-12-11 2013-03-05 Panasonic Corporation Semiconductor device and method of manufacturing the same
US8106520B2 (en) 2008-09-11 2012-01-31 Micron Technology, Inc. Signal delivery in stacked device
US8314499B2 (en) * 2008-11-14 2012-11-20 Fairchild Semiconductor Corporation Flexible and stackable semiconductor die packages having thin patterned conductive layers
US9236277B2 (en) * 2012-08-10 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit with a thermally conductive underfill and methods of forming same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6232563B1 (en) * 1995-11-25 2001-05-15 Lg Electronics Inc. Bump electrode and method for fabricating the same
US5956605A (en) * 1996-09-20 1999-09-21 Micron Technology, Inc. Use of nitrides for flip-chip encapsulation
CN1738042A (zh) * 2004-08-20 2006-02-22 国际商业机器公司 集成电路结构及其形成方法
CN101176200A (zh) * 2005-05-17 2008-05-07 松下电器产业株式会社 倒装片安装方法、倒装片安装装置及倒装片安装体
US20100065790A1 (en) * 2006-05-08 2010-03-18 Diemat Conductive Composition
US20110180920A1 (en) * 2010-01-28 2011-07-28 International Business Machines Corporation Co-axial restraint for connectors within flip-chip packages

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108633181A (zh) * 2017-03-23 2018-10-09 德尔福技术有限公司 电气设备粘合剂屏障
CN108633181B (zh) * 2017-03-23 2021-05-07 安波福技术有限公司 电气设备粘合剂屏障
CN110557937A (zh) * 2018-05-31 2019-12-10 铟泰公司 有效抑制在bga组合件的不润湿开口的助焊剂
CN110557937B (zh) * 2018-05-31 2021-08-06 铟泰公司 有效抑制在bga组合件的不润湿开口的助焊剂
CN112185911A (zh) * 2019-07-03 2021-01-05 美光科技公司 包含垂直集成电路的半导体组合件及其制造方法
US11664291B2 (en) 2019-07-03 2023-05-30 Micron Technology, Inc. Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same
CN112838079A (zh) * 2020-12-31 2021-05-25 湖北长江新型显示产业创新中心有限公司 显示模组及其制作方法
CN112838079B (zh) * 2020-12-31 2022-06-10 湖北长江新型显示产业创新中心有限公司 显示模组及其制作方法

Also Published As

Publication number Publication date
KR20150129768A (ko) 2015-11-20
TW201448134A (zh) 2014-12-16
US20140291834A1 (en) 2014-10-02
KR101825278B1 (ko) 2018-02-02
TWI538120B (zh) 2016-06-11
CN105051891B (zh) 2019-07-05
US20160351530A1 (en) 2016-12-01
WO2014160675A1 (en) 2014-10-02

Similar Documents

Publication Publication Date Title
CN105051891A (zh) 包含导电底部填充材料的半导体装置及封装以及相关方法
JP4155999B2 (ja) 半導体装置および半導体装置の製造方法
US8901732B2 (en) Semiconductor device package and method
US20020025602A1 (en) Microelectronic assembly with pre-disposed fill material and associated method of manufacture
US20110018115A1 (en) Pop precursor with interposer for top package bond pad pitch compensation
US8937385B2 (en) Electronic component and fabrication process of this electronic component
JP2010103244A (ja) 半導体装置及びその製造方法
US8373991B2 (en) Metal thermal interface material and thermal module and packaged microelectronic component containing the material
US8274153B2 (en) Electronic component built-in wiring substrate
JP6242231B2 (ja) 半導体装置及びその製造方法
CN112310063A (zh) 半导体装置封装及其制造方法
KR101208028B1 (ko) 반도체 패키지의 제조 방법 및 이에 의해 제조된 반도체 패키지
CN112054007A (zh) 半导体封装载板及其制法与电子封装件
CN101521170A (zh) 焊接触点及其形成方法
CN108807288B (zh) 电子封装件及其制法
CN209880589U (zh) 半导体封装结构
CN103794568A (zh) 集成电路底部填充方案
JP2008192815A (ja) 積層型半導体装置
CN112117243A (zh) 半导体封装结构及其制备方法
CN209880583U (zh) 半导体封装结构
CN105990155A (zh) 芯片封装基板、芯片封装结构及其制作方法
US20210351097A1 (en) Method for fabricating electronic structure with conductive elements arranged for heating process
JP7366337B2 (ja) 光源装置の製造方法および光源装置
JP6985599B2 (ja) 電子装置及び電子装置の製造方法
CN104576568A (zh) 半导体封装件及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant